TW527539B - Fine-grained PCI slot control apparatus for partitioned systems - Google Patents

Abstract

A system and method for partitioning and allocating individual PCI slots within a primary host bridge (PHB) in a partitioned computer system. The system includes an innovative PHB system which allows a PCI slot to be assigned to one and only one partition at a given time, which reduces system device conflicts between multiple operating systems competing for the same resource.

Description

527539 V. Description of the Invention (1) Background of the Invention 1. Technical Field The present invention relates generally to multi-processor computer systems, and more particularly to resource allocation among processors in a multi-processor system. More specifically, the preferred embodiment relates to a system for partitioning and allocating individual PCI sockets in a multiprocessor computer system. 2. Relevant technical description The computer system for processing daggers is well known in the art, and such multiple computer systems divide the processing work to several different system processors and provide stronger processing capabilities. In traditional systems, each processor can use all system resources; that is, all system processors share all system resources such as memory and If device. Each processor can usually access some parts of system resources. For example, although each processor will have access to a shared memory, the memory is divided into each processor with its own working space. • Recently, the Dong F-type multi-processor (Symmetric CUr, SMP for short) system has been divided, so that the operation of the system is like multiple independent electrical systems. For example, a single-system with eight processors can be set: two to two: the quasi-system of eight processors (or multiple groups of one or more processors) will have its own operating system, And then; ^ and become-the processing cluster ίΓ or each system can work together for better reliability U; this processing can provide high-performance processing and in the evening processor system, usually also has _lf service "

527539 V. Description of the invention (2) The device is used to manage the startup and operation of the overall system, including the system, and, ~, and, and two. The data is routed in and out of each specific bus and device Processor.

The configuration settings of several virtual systems in a two-symmetric multiprocessor (SMP) system must be provided with software support when operating in a cluster mode so that each cluster node and each other in the SMP The nodes communicate with each other, and use any cluster communication technology to perform the required negotiation and authentic communication, and perform other specified functions. When the above tasks are completed, if one of the processors A failure has occurred and the cluster is absent. Using this node, the work previously assigned to the node can be reassigned to the remaining processors (nodes) using standard clustering techniques. A multiprocessor system is usually divided into multiple When virtual systems, each virtual system has its own operating system, and each virtual system uses the same operating system. Because each processor executes the same operating system, it is easier to provide between such processors Resource allocation. However, 'there is currently a market demand for more than one operating system to run on several virtual systems. For example, a user may want A partition executing a variant version of the UNIX operating system, and performs a n Windows "type operating system in a second divided region. This demand raises specific issues related to resource allocation; although the memory is usually supported in the hardware—partitions in the SMP system—but are managed by the operating system such as the interconnection of peripheral components (Peripherai c. mpQnent Interconnect (referred to as PC I) slot and other resources allocation. Because each of the multiple partitions can perform a different operating system, there is a need for a

Page 5 527539 V. Description of the Invention (3) Device for operating system and allocating system resources. In particular, there is currently a need for a solution that is independent of the operating system, which can allocate a system resource such as a PC I slot to multiple partitions in an SMP computer system. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a system for operating a multiprocessor computer system. Another object of the present invention is to provide a system for allocating resources in a multi-processor computer system in a better way. Another object of the present invention is to provide a system for dividing and allocating individual PC I slots in a multi-processor computer system. How to achieve the above items will now be explained. The present invention provides a system for dividing and allocating individual PCI slots in a first main bridge (Pr i mar y o s t B r i d g e; abbreviated as P Η B) in a split computer system. The system includes an innovative PHS system, which can assign a PC I slot to a partition and can only be assigned to a partition at a specific time, thereby reducing multiple jobs competing for the same resource System device conflict between systems. The above and other objects, features, and advantages of the present invention will be more easily understood with reference to the following detailed description. Brief Description of the Drawings The innovative features of the present invention are described in the scope of the final patent application. However, if you refer to the detailed description of an embodiment below and cooperate with the accompanying drawings, it will be easier to understand the present invention, its preferred mode of use, other purposes, and advantages. These drawings include:

527539 Fifth invention description (4) Block diagram = 1: An exemplary computer system diagram according to a preferred embodiment of the present invention; FIG. 2 is a high-order block diagram according to the present invention; FIG. 3 is a detailed block diagram according to the present invention. Figure 4 shows a preferred embodiment of a split-type computer system according to the present invention. An eight-processor computer is a modified embodiment of a preferred embodiment of the PC. The invention group 5 Figure δ is a description table of a partition where the priest is too old, and the flow chart; X month—a system configuration setting program of the preferred embodiment-according to the present invention-preferred implementation For example, the description of the preferred embodiment of the device is started. The following description details several of the invention, but those skilled in the art will understand that the operation and characteristics are supported by the definition of the invention. The scope of the invention is not the same as the scope of the invention. How to explain to the world too: Please read the diagrams, and especially refer to Figure 1. In the figure-'this & a preferred embodiment of the data processing can not be implemented (IBMKArmonk, New Y. rk) supply :: a table of Si Hung 527 539 5. Description of invention (5) Plastic model. The data processing system 100 includes processors 101 and 102. In this embodiment, each of these processors is connected to the second-order (L 2) cache memories 1 0 3 and 104, and L 2 Cache memories 103 and 104 are connected to a system bus 106. The system memory 108 and the first main bridge (PHB) 1 2 2 are also connected to the system bus 106. PHB 1 22 couples I / 0 bus 11 2 to system bus 1 106, and transfers data transactions from one bus and / or converts to another bus. In this embodiment, the data processing system 100 includes a graphic interface card 118 connected to the I / 0 bus 1 12 to receive user interface information of the display 2 2. Non-volatile storage devices such as a hard disk drive 1 1 4 and keyboard / pointing devices 1 16 that can include a conventional mouse, a trackball, and other peripheral devices are passed an industry standard architecture (IndllStry

(Architecture; ISA for short) bridge 121 and connected to the I / O bus 112. The PHB 122 is also connected to each PCI slot 124 via an I / O bus 112. The embodiment shown in FIG. 1 is provided only for the convenience of explaining the present invention, and those skilled in the art will understand that various changes in form and function are possible. For example, the data processing system can also include a CD-ROM, or a digital video disc drive (DVD), a sound card, and a variety of other optional components. All such variations remain within the spirit and scope of the invention. The data processing system 丨 〇 〇 and will be described below: The divided computer system is provided for ease of explanation only, and is intended to limit the architecture of the present invention. Referring to FIG. 2, there is shown a segmentation according to a preferred embodiment of the present invention.

Page 8 527539 V. Description of the Invention (7) The I / O bus 350 provides the ability to connect a large number of PCI slots 314-317 in order to support a scalable high-performance system. Up to four PCI master bridges 310-313 are supported. These PCI master bridges 310-313 are all connected to each peer PCI bus section.

In the preferred embodiment, all PCI slots have hot plug capability. Since the PCI hot-swap control logic circuit and the partition control logic circuit are integrated into PHB 310-313, the external isolation circuit that is a FET in this preferred embodiment can be used to isolate each slot on a transaction-by-transaction basis. To perform a fine division of 1/0. Each partition can have one to all system processors and zero to all PCI slots. The figure also shows various 1/0 devices connected via PHB 31〇. These I / O devices include a SCSI controller 340, a LAN connection device 341, and a picture card; a face card 3 42. An I s A bridge 3 4 3 is used to connect any traditional I / 〇, set to 3j4, these traditional 1 / 〇 devices 344 can especially include a keyboard, mouse, serial ports, parallel ports, sound effects Device, a floppy disk drive, a compact disc drive, and a real-time clock. ^ Please refer to FIGS. 4 to 6, which shows an improved PCI main bridge. The improved PC I main bridge provides a PC I partitioning capability according to a preferred embodiment of the present invention.

PjB 400 provides a number of individual requirements for outbound and inbound transactions that occur simultaneously in either direction. Each outbound transaction is issued by an intermediary device (ag ^ nt) on the I / O bus 401, which means that these outbound transactions are from the core ^, the circuit (representing one of the eight processors) or From another PHB transmitted in a one-to-one application-PC 1 memory transaction. PC I bus

Page 10 527539 V. Description of the invention (8) The pair of equal-valued PCI sinks after these inbound transactions and an intermediary device issue each inbound transaction, [, 穸 穸. 4 / 由, β 1―

An intermediary device on 403 sends to the system t? Overturn r · 4? L J: Streaming section J:, and P C I slots

The PHB issues pci arbitration on all of its bus segments and provides hot-pluggable PCi insertion / splitting. Writes and delayed transactions. It is necessary to distribute the memory writes that are sent out, and you can choose to distribute or defer I / 〇 writes, and both I / 〇 and memory reads will cause a deferred response. The deferred response means: the parent queue is removed from the processor's sequential queue, the transaction is placed in the deferred transaction queue, and the processor is notified of the transaction's completion later. PHB 40 0 will put the deferred transaction into its send request queue 426, and when a read and write transaction is completed on the PCI bus, the PHB will send a deferred reply to the transaction to the request Processor. Incoming memory writes are necessarily distributed, and memory reads are delayed. The delayed transaction for incoming read means that the PHB will put the transaction into its PCI input buffer 429, and terminate the transaction issued by the PCI, and will try again. This transaction is passed to I / O bus 401 to read the data, and the read transaction is placed in the request queue 428 before retrying the PCI transaction. Once the transaction is retried, the pHB completes the transaction and obtains the data. 1/0 bus transaction 1/0 bus issued from one of the eight system processors 527539 Description of the invention (9) — The row transaction will contain the resource address (丨 / 〇 bit type information, and It is called i:,;), the busbar transaction class 45. . It is based on which sideband signal on the front-end bus, which is a 77-bit code. PB 40 0 identifies the request; y; / ;; some sideband signals, and makes the front-side bus (Front Side Bus) member partition. The-a decentralized loop priority bus: the required intermediary devices follow the architecture in order to identify the core logic devices. The -division zone is assigned to the heart: the place :; the identification code of the issuing zone of the hidden stream transaction defines the subdivision zone =, and it is a new 'two' recognition by the sub-core logic circuit of the division zone: Ma is -It is set in this generation, so that it can be too temporary with f-file, to support the sideband signal to only apply the innovative segmentation technology of the present invention. 设定 Set the score at or before starting. Configuration, and the register building is a static 音, sound ;: the register is moved, otherwise the register file will not be changed :: 杪 n: the device partition ID 2 generated by the system restart The number will be counted, so the width of the partition ID register register = the processor can support 8-way SMp, and send out all the necessary information, and it needs 3 digits, H is the 3 partition ID Sideband bus 疋 3 coded signals to identify one of the eight partitions. PHB 400 Receives a bus with 1 / () ^ ^ ^ ^ ^ ^ ^ In addition, J j side kb to determine Which -pc ^ slot resource on the peer pci confluence is started as a member of the target partition. The p: package

527539 V. Description of the invention (10)--'--SPCI slot partitions insert stone %% # D Γ T 4 / Λ? Day and day detail code as part of its PCI configuration space, and the PC I Slot partition;, +, ^ ^ χ 0, Putian escape code contains the programmable information described below, and it is at the time of system startup or Zhi # ~ τ & ] Σ and the group of the PCI plug-in 77 partition description code. # Identifier

/ Target partition identification supports 0 to "n" partitions, where, "n" is the number of processors supported in this system. 0 PCi slots to all PCI slots can be assigned to each partition In this embodiment, a PCI slot and all of its target resources can be members of one and only one partition. The I / Q and Igdg body address information of the L ^ IJf slot are registered in the register. PHB uses these range registers to deterministically decode the address resource of%! Slot declared as a transaction target. Each set of range registers will contain a start (base) address and an end address. 丨 / 〇 The register will support a minimum division of the range of 256 bytes that can be specified in the system address mapping table, and the memory register will support 1 million bytes that can be specified in the system address mapping table A minimum degree of segmentation of the range. The number of non-contiguous address resources supported by each PC I slot requires at least two I / 0 and two memory range register pairs. These registers are used to determine decoding For the purpose of making the pHB accept the I / 0 bus and target A specific I / 〇 cut zone transaction. Before the PHB can definitely accept and respond to one of the outbound transactions issued as an I / O bus, the following conditions must occur. The following conditions are referred to as one of the outbound transactions Determine the partition response (Positive Partition Response; PPR for short). 1 · The I / 0 bus of an existing transaction must issue a partition identifier.

Page 13 527539 V. Description of the invention (12) Therefore, the slot in a divided area on the same PCI bus is started, but it may be necessary to monitor the bus transactions of a specific device and shoot the relationship of the device. pC 丨 partition core logic circuit 4 is further mapped to each PCI slot of the PCI peer bus section of the PQB. The device partition ID and target device partition are sent out for PC I delivery; the comparison. Doesn't the clock cycle matter? (: 1 wasted by arbitration; at the time of the current 4-yard transaction, the arbiter grants the bus to the next bus master's order, but the master control device detects that the PCI bus is idle No. 1 will not obtain the master control of the bus. Then please note that in this preferred embodiment, if it is to be guaranteed that there will be no competition, the PCI bus needs at least one idle bus between transactions. It is sad to perform fast continuous transactions. The pc 丨 specification defines two continuous transactions at t speed; when the target device of a master control device and the target device of the current transaction are the same, the first device is completed. One type is fast, the other is easy, and the second type of fast continuous transaction requires each target device that can perform fast continuous transactions to ensure that there is no conflict with the target device's response signal. The PfL specification requires only the PCI command register. One of the configuration bits is used to support the second mechanism. The preferred embodiment requires that the second mechanism must not be activated, but the second mechanism can support the first type of fast and continuous transactions to the same device. Mechanism. The PCI idle clock cycle is used as a turning cycle to avoid conflicts when a PC I intermediary device stops driving a signal and another intermediary device starts driving the signal. The preferred embodiment requires a bus transaction Idle clock cycle. This is because it starts / stops at this steering cycle.

Page 15 527539 V. Description of the invention (15) Each pc I slot 4 4 0-4 4 4 of the PCI peering bus section sends the P c I out to the device partition ID and the target device Comparison of partition identifiers. The PCI arbiter 421 grants the master control of the bus to the PHB, and obtains the master control of the bus when the ρΗβ ^ detects that the PC I bus is idle. The FET switches 41 0-414 are activated in the idle steering clock cycle before the PHB takes control of the pc I bus. The PQB initiates the read transaction, and the target device on the activated PCI slot provides data. If the data is successfully retrieved from the PCi target device, the deferred reply transaction is normally ended, and the § purchase data is supplied in the data stage I again. If a pc I target device ends abnormally or a parity check error does not successfully read the data from the PC target device, the response phase of the deferred reply transaction will indicate a hard failure response and generate a machine check exception End (MCA). Partitioning Partition Response (PPR), which is a target of an inbound transaction initiated by the PCI bus, is obviously simpler than an outbound transaction. It is generated in the PCI arbiter 421 of the PHB that the PCI bus sending device partition identification code is generated. The pci arbiter 421 connects the signals REQ0: 4 and GNT0: 4 to the PC 1 slots 440-4 44 in a point-to-point manner (ie, without going through an intermediate logic circuit or an isolation FET 41 0-414). REQO: 4 are the PCI bus request signal lines for slots 440-444, and GNT0: 4 are the PCI bus grant and signal lines for these slots. These signals must not be bused or isolated because the arbiter must be able to receive requests to 'give bus mastership' and also to close a particular slot and otherwise isolate that slot from the PHB. Check the status of each slot in other ways. During the current transaction, the arbiter granted the bus master control to the next bus master control device, but in the PC I intermediary device debt

527539 V. Description of the invention (16) Until it is detected that the PCI bus is idle, the PCI intermediary device will not obtain master control of the bus. Only according to which PCI slot M 4 4 0-4 4 4 is to be given master control of the bus, and according to the partition description of the PCI slot, it is known which I / 0 is the PC I plug. The members of the partition can generate the p CI bus to issue the identification code of the partition. The partition core logic circuit 423 receives the PCI bus and sends a device partition identification code, and compares the identification code with all target partition identification codes supported by the ρ Η B. When supporting peer-to-peer transaction communication, start all slots in a partition on the same PCI bus. The partition core logic circuit 423 indicates which PCI slots are to be activated, and instructs the generation 1 hot-plug control logic circuit. In the idle clock cycle before the PCI bus issuing device acquires the master bus control, the FET switches 41-414 are activated.佥 Sent-in memory writes Memory writes are distributed in the PCI feed buffer 429, and once there is available storage space, these memory writes are moved to the feed request queue 428. At this time, the transaction is not removed from the buffer into the buffer 429. When the transaction is placed in the input request queue 4, 28, the I / 0 bus or issuing device / target device control logic circuit 424 requests the master control of the I / O bus 401. The PHB initiates a memory read transaction on the I / O bus, and once the bus mastership is granted, the target is placed in the system memory or the PC memory on another pHB. Delayed delivery

In this embodiment, it can be downloaded from PC I S I G (address is 2 5 7 5 NE

Kathryn St # 17 Hillsboro, OR 97124) to support a memory read as defined by the delayed transaction mechanism defined in the PCI 2.1 specification.

Page 19 527539 V. Description of the invention (17) The PCI 2.1 specification is cited for reference. The pHB will latch all the pC! Bus transaction information, and put the internal memory read into its pc 1 into the buffer 4 2 9 ′ and terminate the p c I transaction with retry. Then, when there is available storage space, the transaction is moved to the request queue 428. At this time, the PCI transaction is removed from the PCI input buffer 429. When the transaction is placed in the input request queue 428, the PCI bus issuing device / target device control logic circuit 424 requests the master control of the I / O bus 401. Once the master control of the 1/0 bus is granted to the ρ Η B, the P 即 B initiates a memory read transaction on the I / 〇 bus that targets the system memory or PC memory. When returning the read data, the PQB will maintain the consistency of the data in the requesting column 428. When the PCI bus intermediary device tried the same memory location again as a delayed transaction, the PHB moved the data to the PCI input buffer 429 'in order to respond with the data and became a delay on the PC I bus. transaction. System startup and configuration settings One of the better ways to start and configure a partitioned computer system configuration is to use the system's service processor to create the initial partition. During the basic system configuration setting, the partition description code is set first. In the preferred method shown in FIG. 6 'after a power-on reset or hard start in step (6 1 0)', when each processor is still in the reset state, the service processor is in step (6 2 0) to start the system startup. The work performed by the service processor is especially to establish the partitioning of the system. In step (63), according to whether the system is not determined to use a system preset split configuration, the service processor will

(6 4 0) use the stored information or interact in step (6 5 0)

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527539 V. Description of the invention (18) Obtain segmentation information from an operator. The service processor neutralizes the basic memory mapping table of the system which includes the location of each PHB in step (660), and sets the partition information to the partition description code temporarily in step (670). Then each system processor is started in step (680), and each prince then uses pci interpolation processing assigned to the processor in step (690) to operate in the partition area assigned to the processor. The description of the reef in the whole area is shown in Figure 5. The partition description shown in Figure 5 contains the partition. In this table, each-slot data item contains the genus V2, which is the slot. In this embodiment, each slot belongs to a partition. , F)) Please refer to ㈣ and 7B. The figure shows a simplified example of the procedure of P Η B according to an example of the present invention. 1 «Ι7Λ-Φ South Gate machine particle diagram (the detailed process has been explained in the text) Figure 7A No processor sends an unidentified ρρτ life L path The processor initiates the write \ Start: 1: / ;. The request is written in step ii) and the code is received in step. The PHB then starts receiving the partition of the processor to identify the slot's partition description in the step (7), and compares the partition identification code with each-(starting bribe! Plug-in should be done, and suddenly. The slot opened in) belongs to each PCI slot of the same partition as that of the PCI slot indicated by the requesting cutting-edge area description code, and in step (725). In the preferred embodiment, Zhong Zuo does not belong to each PCI slot of the partition.

Page 21 527539 V. Description of the invention (19) FIG. 7B shows a memory write initiated by a PCI device. In the figure, after the PCI device initiates the write in step (750), the?叩 The request is received in step (75 5), and the partition description code of the PCI slot is read in the step to determine which partition the PCI slot belongs to. After performing the above steps, the PHB starts all pC I slots belonging to the partition in a dream step (765), and suppresses all slots not belonging to the partition in step (77 0). Finally, in step (775), the PHB transmits the write request to the // bus. Of course, many modifications and changes can be made to the disclosed system and method without departing from the spirit and scope of the present invention. For example, although the description above specifically discussed the allocation of peripheral component interconnect (PCI) connections, these techniques can include unique partitioning and selective isolation of slot connections, etc. ί 1: Different computer architectures and system. Other changes are, of course, within the skill of the educator, and can be expected to be covered by the application of the present invention. Although a reference has been made to a better but familiar to the person skilled in the art, the embodiment of the present invention can still be shown in detail It will be understood that the present invention has been made and described in various forms and details without departing from the spirit of the invention and various changes.

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Claims (1)

527539 Amendment No. 89105704 6. Scope of Patent Application 1. A computer system comprising: a plurality of system processors divided into a plurality of processing partitions, each partition having at least one system processor and a unique partition description code ; At least one memory connected to the job for writing and reading by the processors; one I / 0 controller connected to communicate with the system processors; managed by the I / 0 controller The plurality of I / 0 connections, each I / 0 connection is assigned to at least one of the processing partitions; and the plurality of I / 0 devices connected to the I / 0 connections; The I / 0 controller only allows communication between each system processor and each I / 0 connection belonging to the same processing partition. 2. The system according to item 1 of the scope of patent application, wherein when a processor belonging to a specific processing partition is communicating with an I / 0 device, all I / 0 lines not belonging to the partition are connected to the Wait for processor isolation. 3. If the system of item 1 of the scope of patent application is applied, the isolation is performed by using a field effect transistor. 4. A computer system comprising: at least one system processor; one of which is connected and written and read by the system processors Memory; an I / 0 controller connected to communicate with the memory and the processors; connected to the device via one of a plurality of device connections O: \ 63 \ 63357-910718.ptc Page 26 527539 Amendment No. 89105704 6. At least one peripheral device for patent application scope I / 0 controller communication; wherein the system performs the following steps: In the I / 0 controller Receiving a request to write to the peripheral device from a system processor; receiving a partition identification code corresponding to the system processor in the I / 0 controller, according to whether the plurality of connections belong to one corresponding to the Partition the group of identification codes and connect at least one of the connections; and send the write request to the device. P 5. The system as claimed in item 4 of the patent application, wherein the connection of these devices is a > PCI slot. 6. If the system of item 4 of the patent application is applied, when the connection of these devices is disconnected, an effect transistor is used to isolate the connection of these devices from the I / 0 controller. 7. In the case of the system under item 4 of the patent application, all such connections not belonging to the group are disconnected. · 8 · — A computer system comprising: a plurality of system processors; at least one memory connected to be written and read by the system processors; one connected to the memory and the processors An I / 0 controller for communication; and connected to the device via one of a plurality of device connections O: \ 63 \ 63357-9l0718.ptc Page 27 527539 Amendment_Case No. 89105704 VI. At least one peripheral device for patent application scope I / 0 controller communication; ': Ί.year: month u HI. I which should be The system executes the following steps: receiving a write request from the device in the I / 0 controller; reading a partition description code corresponding to the connection of the device in the I / 0 controller, according to the Whether the device connection belongs to a group corresponding to the partition description code, and at least one of the device connections is connected; the connection of all the devices not belonging to the group is disconnected; and A write request is transferred from the device to the memory. 9. The system according to item 8 of the patent application, wherein the device connection is a PCI slot. 10. If the system of item 8 of the patent application is applied, when the connection of these devices is disconnected, a device is used to isolate the connection of these devices from the I / 0 controller. 11. A computer system comprising: a plurality of system processors; at least one memory connected to be written and read by the system processors; one connected to communicate with the memory and the processors An I / 0 controller; and at least one peripheral device connected to communicate with the I / 0 controller via one of a plurality of device connections; wherein the system performs the following steps: O: \ 63 \ 63357-910718.ptc P.28 527539 YA Wu Zheng Case No. 89105704 VI. Patent Application Scope Assign each of these plural system processors to a processing partition, and assign a separate partition ID For each of these processing partitions, assign each of these device connections to one of the processing partitions, ^ stored in a memory to identify which processing each device connection belongs to The poor information of the partition, and the communication between the system processors and the devices belonging to the same processing partition, and not the communication between the system processors and the devices that do not belong to the same processing partition. . 12. The system of claim 11 in the scope of patent application, wherein when a system processor belonging to a specific processing partition is communicating via a device that belongs to the same processing partition, all the devices that do not belong to the processing partition are communicated. Device connection is broken. 13 3. The system of item 11 in the scope of patent application, wherein when the device connection is disconnected, a field effect transistor is used to isolate the device connection from the I / 0 controller. O: \ 63 \ 63357-910718.ptc Page 29