TW521342B - Method for planarization of wafers with high selectivity - Google Patents

Abstract

A method for p1anarization of a semiconductor wafer with a high selectivity is described. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method has performing a chemical mechanical polishing (CMP) process on the barrier layer so as to expose the stop layer, and removing the stop layer. The polishing selectivity of the barrier layer relative to the stop layer is greater than 50. Since the material of stop layer is different from the material of barrier layer, the high selectivity is easily achieved. Thus, the surface of semiconductor wafer can be highly planarized.

Description

521342 V. Description of the invention α) Field of the invention The present invention provides a flattening method, especially a flattening method having a high selection ratio, which is applied in a semiconductor process. Background Description Nowadays, when semiconductor processes enter the field of deep sub-micro, the planarization requirements of the surface of each deposited layer have become an increasingly important issue. As far as the existing planarization methods are concerned, Chemical Mechanical Polishing (CMP) can be said to be an indispensable process in the interconnect process of the Back End Of the Line (BE0L). technology. Especially the copper interconnect process, because the current copper etching technology is not fully mature, in order to form copper wires, the chemical mechanical polishing process is still one of the most important key technologies used in copper interconnect process today. . Please refer to FIG. 1, which is a schematic diagram of a conventional copper-damascene structure 10. As shown in FIG. 1, the conventional copper mosaic structure 10 includes a first dielectric layer 12, a first conductive layer 14, and a cap layer 16. A second dielectric layer 18, a hard mask 20 ', a barrier layer 22, a second conductive layer 24, and a via plug 26. Among them, the first conductive layer 14 is made of a metal material 521342 5. The description of the invention (2), as for the cover layer 16 is usually made of s 丨 N. In addition, the second dielectric layer 18 is composed of a low dielectric constant material (i0w dielectric constant material), and the hard cover 20 is composed of a fluorinated silicate glass with a low dielectric constant. , FSG), or commonly used photoresist materials, such as Si02, SiN, SiON, SiCO, or SiOCN. As for the barrier layer 22. Or TaN and other commonly used barrier layer materials, and the second conductive layer 24 and the interposer plug 26 are formed using metallic copper. Subsequently, a chemical-mechanical polishing process was started on the copper damascene structure to remove the second conductive layer 24 and the barrier layer 22 on the surface of the hard mask 20 to complete the production of copper interconnects.

Then at this time, in order to ensure that the barrier layer 22 can be completely removed, when the grinding of the early layer J2 of the barrier J1 is performed, a moderate overpolling of the copper damascene structure 10 is required. However, since the chemical reaction characteristics of the currently used abrasives (blurry) on the barrier layer 22 and the hard mask 20 are similar, the chemical mechanical polishing process is effective for the barrier layer 22 and the hard mask 202: ff The rate will be very close. Therefore, p and the research of the barrier layer 22 and the hard mask 20 will be small. The so-called polishing selection ratio is defined as the ratio of the polishing rate of the barrier layer 22 and the hard mask 20. Usually, this grinding selection is around 5. Therefore, it is known that the grinding resistance of the chemical mechanical polishing process is Γ. Second calendar: The hard cover 20 will inevitably be ground, so that the hard cover loss may be as high as 300 to 100A. In addition, the mechanical: after the second pass of grinding, the average sentence degree of the surface will also exceed the electrical performance of the postal dagger _ shirt ring copper mosaic structure 10 electrical performance. What's more, in multiple layers

521342 Five 'invention description (3) 丨 --- (mu 11 i-1 eve 1) Metal internal entanglement Yanshi recognition system, Λ t human must 1 reverse line structure manufacturing process, will also lead to high-level ( high level). SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a planarization method with a high selectivity ratio to solve the above-mentioned conventional chemical mechanical polishing.

Mechanical Polishing (CMP) process. According to the patent application scope of the present invention, a method for planarizing a semiconductor wafer is disclosed. The semiconductor wafer includes a hard mask ', a stop layer provided on the hard mask layer, and a P and barrier layer provided on the stop layer. The planarization method first performs a first chemical mechanical polishing process on the barrier layer to expose the read stop layer, and then removes the stop layer. Wherein, the barrier layer has a polishing selection ratio greater than 50 to the contention layer. According to the application specific scope of the present invention, selecting the appropriate stop layer material can increase the grinding selection to more than 100. = The flattening method of the present invention is that a read stop layer is provided between the hard mask and the barrier layer, and the material of the stop layer and the barrier layer have a significant difference in grinding rate, so it is possible to avoid the conventional In the manufacturing process, the hard cover is lost too much because the grinding selection ratio is too low. At the same time, by means of the high selection ratios provided by the present invention, the surface of the semiconductor wafer can thus be made highly flat.

521342 V. Description of the invention (4) Effect of transformation. In addition, the process margin (m a r g i η) can be greatly increased, which can effectively control the quality of the semiconductor wafer. Detailed description of the invention Please refer to FIG. 2A to FIG. 2F. FIG. 2A to FIG. 2F are schematic diagrams of the planarization method of the present invention. As shown in FIG. 2A, the planarization method firstly provides a semiconductor wafer 30 on which a first dielectric layer 32, a first conductive layer 34, and a cover are formed. Layer (cap layer) 36. Then, a second dielectric layer 38 is gradually formed on the cover layer 36, a hard mask 40 is formed on the second dielectric layer 38, and a stop layer 4 is formed. 2 on the hard screen 40. Among them, the first conductive layer 34 is made of a metal material, and the capping layer 36 is usually made of silicon nitride (s i 1 i con n i t r de, S i N). In addition, the second dielectric layer 38 is made of a low dielectric constant material (i0w.dielectric constant material). For example, SiLKT ^ is FLARETM, and hard mask 40 is a commonly used photoresist material. Such as s 丨 〇2, s 丨 N,

It is made of SiON, SiC, SiCO, or SiOCN, and its thickness is less than 1000 A. In addition, the formation method of the above layers is well known to those skilled in the art, so it is not described here. As for the stop layer 42 of the present invention, it is composed of an organic polymer material. According to a preferred embodiment of the present invention, the organic polymer material may be an aromatic high 521342. 5. Description of the Invention (5) Molecular materials, such as Si LKTM, or a fluorocarbon (fiuorocarb). n) Polymer materials such as FLARE TM. In addition, the stop layer 42 may be formed by a chemical vapor deposition (CVD) method or a spin-on-deposition (SOD) method. At the same time, the thickness of the stop layer 42 formed is less than 1000 A, and the preferred thickness is between 2000 and 400 A. Then, as shown in FIG. 2B, a via of an interposer is defined in the semiconductor wafer 30 (8, 811, 1111, 11) 4 4 extends from the stop layer 4 2 to the cover layer 36 until the first conductive layer 3 4 Of: up to the surface. The formation of the interlayer opening 4 4 can be completed by a conventional photolithography (lithography) and etching process. (See FIG. 2C ') After the formation of the via opening 44, a barrier layer 4 6 is deposited on the surface of the stop layer 42 and the sidewall and bottom surface of the via opening 44. Subsequently, a second conductive layer 48 is formed on the barrier layer 46 and filled in the via opening 44 to form a via plug (via plu ^ 5 (). According to a preferred embodiment of the present invention, The material of the barrier layer 46 may be TaN,

Ta, Ti, TiN, TiSiN, W, WN, or a combination of the above-mentioned commonly used materials for the barrier layer 46, and its thickness is less than 1000 A. As for the second conductive sound & 8 and the interposer plug 50, they are formed using metallic copper. It can be formed by a wet steel electroplating (ECP) process or other copper deposition methods. Then, as shown in FIG. 2D, the second conductive layer 48 is started, that is, copper

521342 V. Description of the invention (6) The layer ′ is subjected to a first chemical mechanical polishing (CMP) process, so that the barrier layer and the interposer plug 50 are exposed. After the copper chemical mechanical polishing process is completed, the process is advanced to the part shown in FIG. 2E, that is, a second chemical mechanical polishing process is performed on the barrier layer 46, so that the stop layer 4 is exposed. . Regarding this second chemical-mechanical polishing mechanism, 'the main thing is to control the pH value of the slurry and the related oxidizer to produce a chemical reaction with the surface of the barrier layer 46' and then match An appropriate organic solvent (solvent) allows the surface of the barrier layer 46 to have a good affinity with the abrasive particles in the abrasive. At this time, it is provided by the polishing pad (polishing pad). A mechanical force of 0.5 to 10 psi enables the first chemical mechanical polishing process to proceed smoothly. According to a preferred embodiment of the present invention, the grinding machine may be a Mirra Mes a grinding machine produced by Applied Materials or a Model 776 grinding machine manufactured by SpeedFam-IPEC. The polishing pad can be a K-XY GROOVE polishing pad made of Rode 1 IC series made of polyurethane foam (PU foam). As for the polishing agent, two Silicon oxide (Si-I-Ca) is an alkaline abrasive Rode 1-1 501 of abrasive particles. Of course, the present invention is not limited to the above-mentioned polishing machine, polishing pad ', polishing agent, and the like. As far as the abrasive is concerned, in order to achieve a high polishing selection ratio, the chemical composition of the abrasive in the polishing barrier layer 46 cannot produce a chemical reaction to the stop layer 42, and is applicable to the present invention. With the present invention

Page 10 521342 V. Description of the invention (Ό In the preferred embodiment, if the barrier layer 46 is made of a nitride button (TaN), the grinding selection ratio of the barrier layer 4 6 to the stop layer 4 2 is It can be greatly increased to more than 100, so the purpose of avoiding the loss of the stop layer can be achieved. In addition, when grinding the barrier layer 46, the grinding pressure generally used will be at least lower than the mechanical strength of the material of the stop layer 42. 100 times. Therefore, by properly controlling the polishing conditions, the possibility that the material of the stop layer 42 will peel off during polishing (de 1 am i nat i on) can be effectively avoided. Please refer to Figure 2F. After the barrier layer 46 is polished, the stop layer 42 is removed. According to a preferred embodiment of the present invention, the stop layer 42 can be removed by a third chemical mechanical polishing process. Among them, in order to make the stop layer 42 hard to The grinding selection ratio of the mask 40 is greater than 5, and an acidic abrasive, Cabot-420, which uses alumina as abrasive particles, can be selected as the abrasive in the third chemical mechanical polishing process of the present invention. Similarly, the so-called grinding selection ratio is defined as stop The ratio of the grinding rate of 42 to the grinding rate of hard mask 40. In addition, the stop layer 42 can also be removed by a dry etching process or a clear-cut process. At this time, the comparison according to the present invention is The preferred embodiment 'when a dry etching process is used, it is performed using a mixed gas based on N 2/0', while the wet etching process may be performed using a fluorine base solvent. Please refer to FIG. 3, FIG. The third is the relationship diagram of the grinding selection ratio of the barrier layer 46 to the hard mask 40 material and the stop layer 42 material. As shown in the third embodiment, the hard mask 40 material includes Fluorosilicate glass

Page 11 521342 V. Description of the invention (8) (F 1 u ○ rinated Si 1 icate G 1 ass (FSG)), nitride silicon (Si 1 ic ο η nitride, SiN), and silicon carbide (silicon carbide, SiC), and the material of the stop layer 42 is S i LKTM formed by a chemical deposition method. The vertical axis shows the polishing selection ratio of the barrier layer 46 made of TaN for each of the above materials. Incidentally, the results in Figure 3 are obtained by using the Mirra Mesa grinding machine from Applied Materials, and K-XY GROOVE ^ grinding of the Rode 1 IC series, combined with the use of stone dioxide. Obtained as an abrasive abrasive particle Rode 1-15 0 1. It can be clearly seen from Fig. 3 that regardless of the material of the hard mask 40, the polishing selection of the hard mask 40 by the barrier layer 46 is less than 5. In contrast, the polishing selection ratio of the barrier layer 46 to the stop layer 42 can be greater than 100. Therefore, forming a stop layer 4 2 ′ between the hard mask 40 and the barrier layer 4 6 according to the present invention can indeed make the flattening method of the present invention achieve an extremely high selection ratio. For the conventional chemical mechanical polishing process, the chemical reaction characteristics of the currently used abrasives for the barrier layer and the hard cover are similar. Therefore, the 'chemical mechanical polishing process for the barrier layer and the hard cover The grinding rate of the curtain will be very close, that is, the grinding selection ratio is small, and usually it is less than about 5. In this way, when the chemical mechanical polishing process grinds the barrier layer, the hard mask is unavoidably grinded, and the thickness loss of the hard mask may be as high as 300 to Around 1000A. At the same time, the uniformity of the surface polished by the chemical mechanical polishing process will be more than X 1 0%. Therefore, the electrical performance of the copper-clad structure polished by the conventional chemical mechanical polishing process will be significantly affected. Negative effects. In addition, Xi

521342 V. Description of the Invention (9) During the manufacturing process of multi-level metal interconnect structure, it will also lead to high-level manufacturing difficulties. Compared with the conventional chemical mechanical polishing process, the planarization method of the present invention is provided with a stop layer between the hard mask and the barrier layer, and since the material of the stop layer is greatly different from the barrier layer, the conventional method can be avoided In the manufacturing process, the hard cover is lost too much because the grinding selection ratio is too low. At the same time, with the high selection ratio provided by the present invention, the surface of the semiconductor wafer can thus be highly flattened. In addition, the process margin (m a r g i η) is greatly increased, and the quality of the semiconductor wafer can be effectively controlled. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 13 521342 Simple illustration of the diagram Simple illustration of the diagram Figure 1 is a schematic diagram of the conventional copper-damascene structure. 2A to 2F are schematic diagrams of a planarization method according to the present invention. FIG. 3 is a diagram showing the relationship between the polishing selection ratio of the barrier layer to the hard mask material and the stop layer material according to the present invention. Explanation of symbols in the figure 10 Copper damascene structure 12 '32 First dielectric layer 14, 34 First conductive layer 16' 3 6 Cover layer 18> 38 Second dielectric layer 20 '4 0 Hard mask 11, 46 Barrier layer 2 core 48 second conductive layer 26 ^ 50 via plug 3 0 semiconductor wafer 42 stop layer 4 4 via • layer opening σ

Page 14

Claims (1)

521342 VI. Application Patent Scope 1. A method for planarizing a semiconductor wafer, the semiconductor wafer includes a hard mask, a stop layer is provided on the hard mask layer, and a resist A barrier layer is disposed on the stop layer. The planarization method includes the following steps: A first chemical mechanical polishing (CMP) process is performed on the barrier layer to expose the stop layer. ; And removing the stop layer; wherein the barrier layer has a polishing selection ratio of greater than 50 to the stop layer. 2. The planarization method according to item 1 of the scope of the patent application, wherein the stop layer is composed of an organic polymer material. 3. The planarization method as described in item 2 of the scope of patent application, wherein the organic molecular material is an aromatic polymer material. 4 · The planarization method as described in item 2 of the patent scope, wherein the organic * molecular material is a fluorocarbon (^ 111〇1'〇〇31 ^ 〇11) polymer material. The flattening method as described in item 1 of the patent scope of 5.5%, wherein the stop layer is formed by a chemical vapor deposition (CVD) method. Page 15 521342 6. Scope of patent application 6. The planarization method as described in item 1 of the scope of patent application, wherein the stop layer is formed by a spin on deposition (SOD) method. 7. The planarization method as described in item 1 of the scope of patent application, wherein the thickness of the stop layer is less than 100 A. 8. The planarization method according to item 1 of the patent application scope, wherein the semiconductor wafer further includes a conductive layer disposed on the barrier layer. 9. The planarization method according to item 8 of the scope of patent application, wherein the conductive layer is made of copper. 10. The planarization method according to item 1 of the scope of patent application, wherein the stop layer is removed by a second chemical mechanical polishing process. 1 1. The flattening method as described in item 1 of the scope of patent application, wherein the stop layer is removed by a surname engraving process. 1 2. The planarization method according to item 1 of the scope of patent application, wherein the barrier layer comprises TaN, Ta, Ti, TiN, TiSiN, W, WN, or a combination of the above materials. 1 3. The planarization method according to item 12 of the scope of patent application, wherein the resistance Page 16 521342 VI. Scope of patent application The thickness of the barrier layer is less than 1000A. 1 4 · A planarization method with a high selectivity ratio, the planarization method includes the following steps: providing a semiconductor wafer on which a first dielectric layer and a cap layer are formed; forming A second dielectric layer on the cover layer; forming a hard mask on the second dielectric layer; forming a stop layer on the hard mask; forming a A barrier layer is formed on the stop layer; a conductive layer is formed on the barrier layer; a first chemical mechanical polishing (CMP) process is performed on the conductive layer,俾 causing the barrier layer to be exposed; performing a second chemical mechanical polishing process on the barrier layer to expose the stop layer; and removing the stop layer; wherein the barrier layer has a polishing option for the stop layer The ratio is greater than 50. 15 · The planarization method according to item 14 of the scope of patent application, wherein the stop layer is composed of an organic polymer material. 1 6 · The flattening method described in item 15 of the scope of patent application, wherein 521342 6. Scope of patent application The organic polymer material is an aromatic t i c polymer material. 17 · The planarization method according to item 15 of the scope of patent application, wherein the organic polymer material is a fluorocarbon polymer material. 18 · The planarization method as described in item 14 of the scope of patent application, wherein the stop layer is formed by a chemical vapor deposition (CVD) method. 19. The planarization method according to item 14 of the scope of patent application, wherein the stop layer is formed by a spin on deposition (SOD) method. 20. The planarization method according to item 14 of the scope of patent application, wherein the thickness of the stop layer is less than 100A. 2 1 · The planarization method according to item 14 of the scope of patent application, wherein the conductive layer is made of copper. 2 2. The planarization method according to item 14 of the scope of the patent application, wherein the stop layer is removed by a third chemical mechanical polishing process. 2 3. The planarization method according to item 14 of the scope of patent application, wherein the stop layer is removed by an etching process. Page 521342 6. Application for Patent Scope 2 4. The planarization method as described in Item 14 of the Patent Application Scope, wherein the barrier layer comprises TaN, Ta, Ti, TiN, TiSiN, W, WN, or the above A combination of materials. 25. The planarization method as described in item 24 of the scope of patent application, wherein the thickness of the barrier layer is less than 1,000 people. Page 19