經濟部智慧財產局員工消費合作社印製 521184 4〇24twf.doc/〇〇5 A 7 B7 五、發明説明（I ) 本發明是有關於一種pci匯流排相容之裝置，且特別 是有關於一種與PCI匯流排相容，並可同時對多個主控器 (master)之讀取要求進行資料準備，以大量縮短要求資料之 延遲時間之多延遲讀取交易（Multi delay read transaction)之 裝置及其操作方法。 拜半導體技術大幅進步之賜，電腦已普及至生活中的 每一'個角洛’成爲日常生活中不可或缺的有用工具。而圖 形取向之操作系統，如WINDOWS或OS/2等需要在中央 處理器與週邊的裝置之間進行大量的資料傳輸。假如週邊 裝置的傳輸頻寬無法與中央處理器匹配的話，便造成資料 傳送的瓶頸。爲了解決此瓶頸問題，各種高速的區域匯流 排（local bus)的架構便被提出。週邊裝置連接匯流排 (peripheral component interconnection bus，PCi 細§)便是 其中^一*種。 第1圖所繪示的便是在電腦架構中使用PCI系統的 一種架構。中央處理器10經由主橋接器（host bridge)12 耦接到PCI匯流排14。PCI匯流排14則可以耦接多數個 PCI相容之週邊裝置的主控器（master)，其可以如圖所示 之圖形介面（graphic adapter)〗6a、延展匯流排橋接器 (expansion bus bridge)16b、網路介面（LAN adapter) 16c 與 小型電腦系統主匯流排介面（SCSI host bus adapter )16d等 等。每一主控器均可以送出要求訊號（request，RST)要求 使用PCI匯流排Μ，而主橋接器12中的匯流排仲裁器 (arbiter)則可送出同意訊號（grant，GNT)給主控器，同意 3 '^張尺度適用中國國^^((：叫/^4規格（21〇/297公釐） ^〜 -------r-H--Γ 裝------、{^------..線 (請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521184 4024twf.doc/005 八7 B7 五、發明説明（〆） 其使用PCI匯流排14。 PCI相容裝置（如主控器或電腦晶片組中之北橋）之間 的資料傳送主要係由下列之介面控制訊號所控制。週期框 (cycle frame’ FRAME)係由起始器（其可以是主控器或北橋) .所送出，用以指示一存取操作的開始與持續期間。FRAME 訊號送出時，表示透過PCI匯流排的資料交易（transaction) 開始進行，當FRAME訊號維持在低準位則表示資料交易 持續進行。此時，位址匯流排AD便會在位址週期期間送 出有效位址（valld address)，同時會在命令/位元組致能 (command/byte enable，CBE[3:0])線送出有效的匯流排命 令（滿足PCI規格），用以對目標裝置指出起始器所要求的 資料交易型態，其中命令/位元組致能線係以4位元編碼 成16種不同的命令，其在PCI規格中有詳細定義。緊接 所送出的有效位址後，位址匯流排AD便送出要傳送的資 料，此時期稱爲資料週期，同時於CBE線送出編碼後匯 流排命令之位元組致能訊號，藉以傳送資料。當FRAME 訊號停止送出，就表示交易狀態爲最後一筆資料傳送，或 是已經完成貪料傳送。起始器備妥訊號（initiator ready, IRDY)與目標裝置備妥訊號（target ready，TRDY)，兩者配 合使用，用以分別指示起始裝置與目標裝置已經備妥而可 以進行資料傳送。在一讀取動作進行時，IRDY訊號表示 起始器準備好接收資料；而在進行一寫入操作時，TRDY 訊號表示目標裝置準備好接收資料。停止訊號（stop， STOP)，用以指示目標裝置要求起始器停止目前的資料交 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -------^1--Γ裝-------訂-------線 (請先閱讀背面之注意事項再填寫本頁) 521184 4024twf. doc/005 A 7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（々） 易行爲。 請參考第2圖，其繪示以PCI匯流排介面進行一讀 取操作進行時的操作時序圖。以PCI匯流排進行並完成資 料轉移的期間稱爲一^匯流排父易週期（bus transaction)2〇 ’ 其包括一^ 位址週期（address phase) 22 與數 個資料週期（data Phase)，如24a、24b與24c。每一個資 料週期24a/b/c又分別區分爲等待週期（wait cycle) 26a/b/c 與資料轉移週期（data transfer cycle) 28a/b/c。接著配合第 2圖的時序圖，以一讀取操作來做爲PCI系統操作之簡單 說明以及前文所述之PCI規格控制訊號的作用。 在週期T1時，起始器送出FRAME訊號，表示一資 料轉移將開始進行。並在AD匯流排送出開始位址（start address)，用以指定一目標裝置，同時於CBE線送出一讀 取命令。緊接著送出的讀取命令，CBE線會送出經過編碼 後命令的位元組致能訊號（byte enable)，此位元組致能訊 號在整個資料週期期間（包括24a、24b與24c)會一直持續 送出。在週期T2時，起始器送出備妥訊號IRDY，表示 可以開始收送資料，然此時目標裝置並未能備妥’此時期 爲資料週期2 4 a之等待週期2 6 a，係起始器等待目標裝置 將資料備妥。在週期T3時，目標裝置已經備妥並且送出 備妥訊號TRDY，因此在IRDY與TRDY訊號均送出的資 料轉移週期28a期間，起始器從目標裝置讀取資料。目標 裝置在週期T4結束送出TRDY訊號，以表示結束資料傳 送，並且開始準備第二筆資料，此時爲資料週期24b之等 I------i--r 裝-- (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 521184 4〇24twf.doc / 〇〇5 A 7 B7 V. Description of the Invention (I) The present invention relates to a PCI bus compatible device, and in particular to a PCI bus compatible device. Compatible with PCI buses, and can prepare data for reading requests from multiple masters at the same time, in order to greatly reduce the delay time of the requested data, Multi delay read transaction (Multi delay read transaction) device and Its operation method. Thanks to the great advancement of semiconductor technology, computers have spread to every corner of life and become an indispensable and useful tool in daily life. Graphically oriented operating systems, such as Windows or OS / 2, require a large amount of data to be transferred between the CPU and peripheral devices. If the transmission bandwidth of the peripheral devices cannot match the central processing unit, it will cause a bottleneck in data transmission. To solve this bottleneck, various high-speed local bus architectures have been proposed. Peripheral device connection bus (PCi detailed §) is one of them. Figure 1 shows an architecture using a PCI system in a computer architecture. The central processing unit 10 is coupled to the PCI bus 14 via a host bridge 12. The PCI bus 14 can be coupled to the master of most PCI-compatible peripheral devices. It can be shown in the graphic adapter (graphic adapter) 6a, the expansion bus bridge (expansion bus bridge) 16b, LAN adapter 16c and small computer system main bus interface (SCSI host bus adapter) 16d, etc. Each master can send a request (RST) request to use the PCI bus M, and the bus arbiter in the main bridge 12 can send a grant (GNT) to the master , Agree that 3 '^ Zhang scale is applicable to China ^^ ((: called / ^ 4 specification (21〇 / 297 mm) ^ ~ ------- rH--Γ installed ------, { ^ ------ .. line (please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521184 4024twf.doc / 005 8 7 B7 V. Description of Invention (〆) It uses PCI bus 14. The data transmission between PCI compatible devices (such as the host controller or the North Bridge in the computer chipset) is mainly controlled by the following interface control signals. The cycle frame (FRAME) is controlled by The initiator (which can be the main controller or the Northbridge). It is sent to indicate the start and duration of an access operation. When the FRAME signal is sent, it means that the data transaction (transaction) through the PCI bus starts. If the FRAME signal stays at a low level, it means that the data transaction continues. At this time, the address bus AD will be in the address cycle. During this time, a valid address (valld address) will be sent, and at the same time, a valid bus command (which meets the PCI specifications) will be sent on the command / byte enable (CBE [3: 0]) line to target the target. The device indicates the type of data transaction required by the initiator. The command / byte enable line is encoded in 4 bits into 16 different commands, which are defined in the PCI specification in detail. After the address, the address bus AD sends the data to be transmitted. This period is called the data cycle. At the same time, the byte enable signal of the bus command is sent on the CBE line to transmit data. When the FRAME signal stops sending, , It means that the transaction status is the last data transmission, or the material transmission has been completed. The initiator ready signal (IRDY) and the target device ready signal (target ready, TRDY) are used together. To indicate that the starting device and the target device are ready for data transmission. When a read operation is performed, the IRDY signal indicates that the initiator is ready to receive data; and when performing a write operation, T The RDY signal indicates that the target device is ready to receive data. A stop signal (stop, STOP) is used to instruct the target device to request the initiator to stop the current data submission. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)- ------ ^ 1--Γ installed ------- order ------- line (Please read the precautions on the back before filling in this page) 521184 4024twf. Doc / 005 A 7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (々) Easy behavior. Please refer to FIG. 2, which shows the operation timing diagram when a read operation is performed using the PCI bus interface. The period during which the PCI bus is used to complete and transfer data is called a ^ bus transaction 2 0 ', which includes a ^ address phase 22 and several data phases, such as 24a, 24b, and 24c. Each data cycle 24a / b / c is divided into a wait cycle (26a / b / c) and a data transfer cycle (28a / b / c). Then, in conjunction with the timing diagram of Figure 2, a read operation is used as a simple description of the operation of the PCI system and the role of the PCI specification control signal described above. At cycle T1, the initiator sends a FRAME signal, indicating that a data transfer will begin. A start address is sent on the AD bus to specify a target device, and a read command is sent on the CBE line. Immediately after the read command is sent, the CBE line will send a byte enable signal after the encoding command. This byte enable signal will be maintained during the entire data cycle (including 24a, 24b, and 24c). Keep sending. At cycle T2, the initiator sends a ready signal IRDY, indicating that it can start sending data, but the target device is not ready at this time. 'This period is the data cycle 2 4 a and the waiting period 2 6 a, which is the start The device waits for the target device to prepare the data. At cycle T3, the target device is ready and sends a ready signal TRDY. Therefore, during the data transfer period 28a that both IRDY and TRDY signals send, the initiator reads data from the target device. The target device sends a TRDY signal at the end of cycle T4 to indicate the end of data transmission and start to prepare the second data. At this time, the data cycle is equal to 24b. I ------ i--r equipment-- (Please read first (Notes on the back then fill out this page)
、1T 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 521184 A7 4024twf.doc/005 ____B7 五、發明説明（畛） 待週期26b。在週期T5時，TRDY再度送出，表示資料 已經備妥，並在IRDY與TRDY訊號均送出的資料轉移週 期2 8b期間，起始器從目標裝置讀取資料。當起始器來不 及讀取資料時，起始器於週期T6結束送出IRDY訊號， .此時因爲TRDY訊號仍送出，所以此等待週期26c係由起 始器所發動。等起始器備妥後，於週期T7再送出IRDY 訊號，此時在IRDY與TRDY訊號均送出的資料轉移週期 28c期間，起始器從目標裝置讀取資料。至此，完成一讀 取操作。 一般系統，在任何特定的匯流排週期中，只有一個主 控器可經由匯流排而通訊。因此，想要交易資料的各裝置 在進行交易之前，首先必須要求並接收到匯流排主控權之 授與。在習知之簡單系統中，主控器在完成資料交易前， 不會釋放出匯流排的主控權。然而，在一些情況下，可能 迫使主控器讓出匯流排的主控權，例如··當目標裝置無法 即時回應主控器之要求時，目標裝置可發出適當之訊號， 來通知主控器讓出匯流排主控權。 在PCI匯流排協定規格（如版本2.1)中，有一種稱爲 延遲交易（delayed transaction)的資料交易方法。所謂延 遲交易係指目標裝置（Target)在PCI規格（PCI specification)之定義下，無法完成起始資料週期（initial data phase)，所採用的操作程序。主要有兩種裝置會處理 延遲交易操作··輸入/輸出控制器（I/O controller)與橋接器 (bridge) ° 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -------1--ί裝-------訂------線 (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 521184 4024twf.doc/005 A7 B7 五、發明説明（f) 延遲交易操作程序係包含三個時相：1.由主控器在 pci匯流排發出存取目標裝置的要求，目標裝置記憶此要 求後，目標裝置在PCI匯流排上開始一具有重試之目標啓 動終止（Target Initiated Termination with Retry)，又叫做 延遲交易終止（Delay Transaction Termination)，來主動結 束此要求；接著，2·由目標裝置備妥主控器所發出的要 求；最後，3.由主控器主動重新發出原先存取目標裝置的 要求’以完成資料交易。在整個延遲交易進行期間，主控 器會持續不斷發出PCI匯流排詢問訊號，以及佔據PCI匯 流排的使用權限，並且不斷對目標裝置發出類似輪詢 (polling)的操作。 對於主控器的存取方式來說，較早期的做法爲無延遲 (No delay)之資料交易方式。舉例來說，請再同時參照第1 圖與第2圖，當主控器(起始器）例如網路介面16c發出一讀 取要求，要讀取系統記憶體11的資料，如果主橋接器12(目 標裝置）無法立即由系統記憶體11讀取並備妥資料，此時 主橋接器12持續使TRDY訊號維持不動作，亦即使資料 週期24a之等待週期26a拉長，一直到主橋接器12將資 料備妥，主橋接器12送出TRDY訊號後，網路介面16c才 能開始真正進行讀取資料。 由於網路介面16c在進行讀取操作時，PCI匯流排14 因網路介面16c之讀取要求而被佔住，此時若有另一主控 器例如SCSI介面16d也要讀取系統記憶體11的資料、或 與圖形介面16a相互通訊時，其將不會被允許使用PCI匯 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -------1--f 裝------IT------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521184 A7 4024twf.d〇c/00 5 __B7___ 五、發明説明（t ) 流排14，亦即所發出的任何要求將會被視爲無效，必須等 到網路介面16c完成讀取操作而釋放出PCI匯流排14後， SCSI介面16d才能經由PCI匯流排14透過主橋接器12來 進行讀取操作。因此，此種無延遲的資料交易方法已不符 合效率的要求。 習知另一種方法爲單一延遲（single delay)之延遲交易 方式。所謂的單一延遲係指目標裝置雖具有處理延遲交易 的能力，卻只能處理一個延遲交易的需求，亦即當目標裝 置發出延遲交易終止後，且在對應此延遲交易終止之資料 未真正傳送前，其他對此目標裝置的資料交易需求，雖仍 然獲得此目標裝置以延遲交易終止回應，但目標裝置視同 從未收過這些資料交易需求。舉例來說，請同時參照第1 圖與第3圖，第3圖繪示的是當多個主控器在同一目標裝 置要求資料，利用單一延遲之延遲交易的匯流排耗時圖。 首先，當網路介面16c(第一主控器）發出讀取要求以 讀取系統記憶體11的資料後，主橋接器12(目標裝置）無法 1即由系統記憶體11讀取並備妥資料，此時主橋接器12 發出具有重試之目標啓動終止，亦即發出延遲交易終止， 以通知網路介面16c釋放出PCI匯流排14,從網路介面16c 發出讀取要求到其釋放出PCI匯流排14，佔據PCI匯流排 共T1 r的時間。此後’主橋接器12開始由系統記憶體U 讀取資料，約需Td的時間方可備妥資料。 因爲SCSI介面16d(第二主控器)也要存取系統記憶體 11的資料時，所以SCSI介面16d也以主橋接器π爲目標 8 本^^^度適用中關^準（CNS ) A4規格（2跑297公蔆1 --------- -------^--rt--------IT-----ά. (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521184 4024twf.doc/005 八7 B7 五、發明説明（q) (請先閱讀背面之注意事項再填寫本頁) 裝置，發出讀取要求，此時，由於主橋接器12係僅能處理 單一延遲的裝置，故主橋接器12根本無法處理此要求，此 時主橋接器12同樣發出具有重試之目標啓動終止，以使 SCSI介面16d釋放出PCI匯流排14，從SCSI介面16d發 .出讀取要求到其釋放出PCI匯流排14，佔據PCI匯流排共 T2rl的時間。 當主橋接器12備妥對應於網路介面16c所要求之資料 後，但是因爲網路介面16c不會剛好立即來詢問主橋接器 12是否備妥資料，假設必須再等Tlw的時間，網路介面16c 才再發出讀取要求，主橋接器12與網路介面16c便真正開 始傳送資料，經過Tit的資料傳輸時間後，才結束此延遲 交易。對於此次資料讀取交易，共需要T1的時間，其中 Tl=Tlr+Td+Tlw+Tlt 〇 經濟部智慧財產局員工消費合作社印製 接著，若SCSI介面16d再發出讀取要求，距離上一 次結束讀取要求，已經經過T2wl的時間，如同上述般，主 橋接器12發出具有重試之目標啓動終止，耗費PCI匯流 排共T2r2的時間後，才會再開始準備要求之資料。再經Td 的時間後，主橋接器12的資料備妥，同樣再等T2w2的時 間，SCSI介面16d才再發出讀取要求，主橋接器12與SCSI 介面16d利用T2t的時間真正傳輸資料後，此延遲交易結 束。對於此次資料讀取交易，共需要T2的時間，其中 T2=T2rl+T2wl+T2r2 + Td+T2w2 + T2t。 由前述可知，網路介面16c之資料交易的延遲時間 (latency)爲ΤΥατι= Td+T〗w，但是SCSI介面I6d之資料交 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 521184 4024twf.d〇c/005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（？） 易的延遲時間卻爲TLAT2=T2wl+T2r2 + Td+T2w2。而在一般 情況，由於T2wl大於真正傳輸時間Tit，且資料傳輸時 間Tit又大於資料準備時間Td，故SCSI介面16d之資料 交易的延遲時間TLAT2約大於2 Td+T2r2 + T2w2。因此，習 .知單一延遲之延遲交易方式，雖然在準備網路介面16c所 需資料的同時，其他主控器仍可透過釋放出之PCI匯流排 14相互通訊，然而一旦SCSI介面16d也要讀取系統記憶體 11的資料時，反而比先前無延遲交易的方式更加耗費時 間。 有鑒於此，本發明的目的就是在提供一種多延遲讀取 交易之裝置及其操作方法，以改善習知單一延遲交易方式 造成延遲時間過長的問題。 本發明的另一目的，提出一種多延遲讀取交易之裝置 及其操作方法，可同時對多個主控器之讀取要求，進行資 料找取的動作，以縮短個別主控器之要求資料的延遲時 間。 爲達成上述和其他目的，本發明提供一種多延遲讀取 交易之裝置，接在PCI匯流排上，而PCI匯流排上接有至少 一個主控器，形成一種PCI匯流排系統，此種多延遲讀取交 易之裝置包括：要求佇列、資料資源集以及控制器。耦接 至PCI匯流排之要求佇列，可儲存這些主控器之複數個要求 訊號中之複數個位址，以及儲存對應這些位址之複數個資 料訊息。耦接至要求佇列之資料資源集，其可依據這些要 求訊號之位址取出對應之資料訊息，並將這些資料訊息傳 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 壯衣I I —. I —i訂I I I I n線 (請先閎讀背面之注意事項再填寫本頁) 521184 經濟部智慧財產局員工消費合作社印製 4024twt'.doc/005 A7 ____B7 ____ 五、發明説明（f ) 送至要求佇列。控制器與PCI匯流排、要求佇列及資料資源 集都耦接在一起。 此種多延遲讀取交易之裝置接收到這些主控器之要 求#1號後’控制器檢查這些要求訊號之位址。然後，當這 些位址不存在於要求佇列時，則儲存這些位址在要求佇列 中，且控制器會發出延遲交易終止至pci匯流排，同時控制 器向資料資源集要求對應這些位址之資料訊息；當這些位 址已經存在於要求佇列，而對應這些位址之資料訊息卻不 存在於要求佇列時，控制器發出延遲交易終止至PCI匯流 排；當這些位址已經存在於要求佇列，且對應這些位址之 資料訊息也儲存在要求佇列時，回應這些位址所對應之資 料訊息至對應之主控器，並消除在要求佇列中之這些位 址。 上述要求佇列包括位址佇列以及資料佇列，位址佇列 用以儲存這些要求訊號之位址，而資料佇列用以儲存對應 這些位址之資料訊息。上述資料資源集耦接至系統資源記 憶體，而系統資源記憶體儲存有這些資料訊息。 本發明所提供之多延遲讀取交易裝置的操作方法，包 括下列步驟：首先接收該些主控器之複數個要求訊號，再 檢查該些要求訊號之複數個位址。然後，當這些位址不存 在於要求佇列時，則儲存這些位址在要求佇列中，且控制 器發出延遲交易終止至PCI匯流排，同時控制器向資料資源 集要求對應這些位址之資料訊息.；當這些位址已經存在於 要求佇列，而對應這些位址之資料訊息不存在於要求佇列 11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 線 521184 4〇24twf.doc/〇〇5 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（β) 時’控制器發出延遲交易終止至PCI匯流排。 資料資源集接受控制器之要求後，其依據這些位址取 出對應之料訊息，並將這些資料訊息傳送至要求佇列中暫 存。接著，再接收到這些主控器之要求訊號，並檢查這些 .要求訊號之位址，當這些位址已經存在於要求佇列，且對 應這該些位址之資料訊息儲存在要求佇列時，回應這些要 求訊號所對應之資料訊息至對應之主控器，並消除在要求 佇列中對應這些資料訊息之位址。 本發明所提供之一種多延遲讀取交易之裝置及其操 作方法’可同時對多個主控器之讀取要求，進行對應上述 讀取要求之資料準備，同時可隨時保持PCI匯流排於閒置狀 態’讓其他週邊連接裝置可隨時相互通訊，達到充分利用 PCI匯流排及大量縮短要求資料之延遲時間的功能，藉以解 決習知單一延遲交易方式所遇到延遲時間過長的問題。 I爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖繪示的是在電腦架構中使用PCI系統的一種 架構圖； 第2圖繪示的是一讀取操作進行時的系統時序圖； 第3圖繪示的是當多個主控器在同一目標裝置要求資 料，利用習知單一延遲之延遲交易的匯流排耗時圖； 第4圖繪示的是依照本發明一較佳實施例之多延遲交 12 ^紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 · " I---:--"Γ Γ 裝-------訂-----.線 (請先閲讀背面之注意事項再填寫本頁) 10 :中央處理器 12 :主橋接器 16a :圖形介面 16c :網路介面 2〇 :匯流排交易 24 :資料週期 28 :資料傳送週期 521184 4024t.wf.doc/005 A 7 B7 五、發明説明（丨丨） 易的系統時序圖； 第5圖繪示的是當多個主控器在同一目標裝置要求資 料’利用本發明多延遲之延遲交易的匯流排耗時圖；以及 第6圖繪示的是依照本發明一較佳實施例的一種多延 遲讀取交易之裝置的方塊圖。 .圖式之標號說明： 11、260 :系統記憶體 14、250 : PCI 匯流排 16b :延展匯流排橋接器 16d : SCSI 介面 22 :位址週期 26 :等待週期 30、211〜213 :主控器 200 :多延遲讀取交易裝置220 :要求佇列 221 :資料佇列 222 :位址佇列 230 :控制器 240 :資料資源集 實施例 請參考第4圖並配合第1圖，其繪示應用本發明一 較佳實施例之多延遲交易的系統時序圖。在第4圖中，主 控器，如第1圖中之網路介面16c(第一主控器）以及SCSI 介面16d(第二主控器），發出四個不同的讀取週期，用以 存取PCI匯流排14上之目標裝置（主橋接器12)。 在週期T1時，網路介面16c發出要求訊號reqi要 求使用PCI匯流排14 ;而對SCSI介面16d而言，則在週 13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I-----^--Γ裝-------訂-------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521184 經濟部智慧財產局員工消費合作社印製 4024twf.doc/005 八7 __B7___ 五、發明説明（/> ) 期T8時發出訊號REQ2要求使用pci匯流排14。主橋接 器12則分別於週期T2與T9回應同意訊號GNT1與 GNT2，同意網路介面16c與SCSI介面16d使用匯流排 14 〇 網路介面16c在週期T3發出一 FRAME訊號表示資 料交易可以開始進行，並在時脈T3時於AD匯流排送出 位址以及在CBE送出讀取（read)命令與位元組致能（BE)訊 號。在週期T4，網路介面16c送出IRDY訊號，表示網 路介面16c已經備妥。此時，主橋接器12會將此要求記 存住，並開始準備對應此要求之資料訊息，因爲主橋接器 12之TRDY訊號未送出，表示主橋接器12無法即時將資 料備妥傳送給網路介面16c，主橋接器12會回應一延遲 交易終止，亦即在週期T5時，送出一停止訊號STOP， 而網路介面16c便結束送出要求訊號REQ1。 其次，SCSI介面16d在週期T10發出FRAME訊號 表示開始進行資料讀取交易，並在時脈T10於AD匯流排 送出位址以及在CBE送出讀取（read)命令與位元組致能 (BE)訊號。在週期T11送出IRDY訊號表示SCSI介面16d 已經備妥。此時，因爲主橋接器12係爲本發明之一種多 延遲讀取交易之裝置，主橋接器12同樣會將此要求記存 住，並開始準備對應此要求之資料訊息，此時目標裝置（主 橋接器12)之TRDY訊號並未送出，表示主橋接器12無 法及時將資料傳送給起SCSI介面16d，接著主橋接器12 會回應一延遲交易終止，主橋接器12在週期T12時，送 I. ϋ 11111、^ n 111111 ^ 1111II '線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 521184 4 0 2 41 w f. d 〇 c / 0 0 5 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（#) 始進行資料讀取交易，並且於AD匯流排上，送出與上一 次要求相同之位址以及在CBE送出讀取命令。在週期 T30，主橋接器12送出TRDY訊號，便開始進行資料取得 週期（週期T30到T37)。 舉例來說，請同時參照第1圖與第5圖，第5圖繪示 的是當多個主控器在同一目標裝置要求資料，利用本發明 多延遲之延遲交易的匯流排耗時圖。 •首先，當網路介面16c(第一主控器）發出讀取要求以 讀取系統記憶體Π的資料後，主橋接器12(目標裝置）無法 立即由系統記憶體11讀取並備妥資料，此時主橋接器12 會將此要求記存住，並開始準備對應此要求之資料訊息， 同時發出具有重試之目標啓動終止，亦即發出延遲交易終 止，以通知網路介面16c釋放出PCI匯流排14，其中從網 路介面16c發出讀取要求到其釋放出PCI匯流排14，佔據 PCI匯流排共Tlr的時間。此後，主橋接器12開始由系統 記憶體Π讀取資料，約需Td的時間方可備妥資料。 因爲SCSI介面16d(第二主控器)也要存取系統記憶體 11的資料時，所以SCSI介面16d也以主橋接器12爲目標 裝置$發出讀取要求，此時，因爲主橋接器12係爲本發 明之一種多延遲讀取交易之裝置，故主橋接器12同樣會 將此要求記存住，並開始準備對應此要求之資料訊息，主 橋接器12同樣會發出具有重試之目標啓動終止，以使 scsi介面16(1釋放出PCI匯流排14,其中從SCSI介面16d 發出讀取要求到其釋放出PCI匯流排14，佔據PCI匯流排 16 度適财關家( CNS ) A4規格（21GX297公釐1 ~ --：- I--------.I, Γ裝-------訂------線 (請先閱讀背面之注意事項再填寫本頁) 521184 40 2 4twf. doc/O 0 5 A7 B7 五、發明説明（/Ο 共T2rl的時間。此後，主橋接器12開始由系統記億體11 讀取資料，約需Td的時間方可備妥資料。 (請先閲讀背面之注意事項再填寫本頁) 當主橋接器12備妥對應於網路介面i6c所要求之資料 後，但是因爲網路介面16c不會剛好立即來詢問主橋接器 12是否備妥資料’假設必須再等T1 w的時間，網路介面16c 才再發出讀取要求，主橋接器12與網路介面i6c便真正開 始傳送資料，經過T11的資料傳輸時間後，才結束此延遲 交易。對於此次資料讀取交易，共需要T1的時間，其中 Tl^Tlr+Td+Tlw+Tlt 〇 接著，當主橋接器12也備妥對應於SCSI介面16d所 要求之貪料後’问樣地’因爲SCSI介面16d也不會剛好立 即來詢問主橋接器12是否備妥資料，假設必須再等T2w2 的時間，SCSI介面16d才再發出讀取要求，主橋接器12 與SCSI介面16d便真正開始傳送資料，經過T2t的資料 傳輸時間後，才結束此延遲交易。對於此次資料讀取交 易，共需要T2的時間，其中T2=T2rl+Td+T2w2 + T2t。 經濟部智慧財產局員工消費合作社印製 由前述可知，網路介面16c之資料交易的延遲時間爲 TLAT1= Td+Tlw，而SCSI介面16d之資料交易的延遲時間 爲Tlat2=T(1+T2w2。因此，以本發明SCSI介面16d與先前 所提及單一延遲之延遲交易方式兩者所耗費的資料讀取交 易時間相比較，本發明比習知方式可減少大約T2wl+T2i*2 的資料讀取交易時間。所以，由於本發明可同時對多個主 控器之讀取要求，進行資料準備的動作，故可以大大地縮 短主控器要求資料的延遲時間，進而增進整體系統效率。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 521184 4024twf. doc/005 A7 B7 五、發明説明（/ &) 請參照第6圖，其繪示的是依照本發明一較佳實施例 的一種多延遲讀取交易之裝置的方塊圖。 本發明之多延遲讀取交易之裝置200，可設計佈置 (layout)於主橋接器例如晶片組內，其包括要求佇列(request queue)220、控制器（controller)23〇 及資料資源集（data p〇〇l)240，其中要求佇列220係由資料佇列221與位址佇列 222所組成。要求佇列220耦接PCI匯流排250，其內部之位 址佇列222用以儲存主控器211〜213之要求訊號的位址，資 料佇列221用以儲存對應主控器211〜213之要求訊號的位址 之資料訊息。 控制器230也親接至PCI匯流排250，一開始要求f宁列 220中之位址佇列222並未儲存有任何位址，當控制器230接 收到要求訊號時，控制器23〇會送出一停止訊號STOP至PCI 匯流排250中，以釋放(release)出PCI匯流排250供其他裝置 使用，而此時要求訊號之位址會儲存至位址佇列222中，控 制器230也會送出要求訊號之位址給資料資源集24〇，以要 求備妥對應此位址之資料訊息。資料資源集240耦接要求f宁 歹[J220及控制器230, 一般資料資源集240會接至系統記憶 體260，其會依據要求訊號之位址取出系統記憶體26〇內對 應之資料訊息，並將對應之資料訊息傳送至要求丨宁列220之 資料ί宁列221中。 以下敘述本發明之多延遲讀取交易之裝置的操作方 法’當主控器211發出讀取要求以讀取系統記憶體26〇的 資料時，首先控制器230檢查此讀取要求之位址，例如位 18 本紙張尺度適用^_^家標準（（：奶）八4規格（210父297公釐) ' " ---- I-------I裝-------訂------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521184 4024twf.doc/005 B7__ 五、發明説明（，7) 址ADDRO，是否在位址佇列222中，因爲一開始要求佇列 220中之位址佇列222並未儲存有任何位址，故位址ADDRO 會被儲存在位址佇列2D中。接著控制器230會將位址 ADDR0送至資料資源集240中，同時送出停止訊號至PCI 匯流排250中，以釋放出PCI匯流排250給其他裝置使用， 例如：主控器212可透過PCI匯流排250與主控器213相 互通訊。接著資料資源集240會依據此位址訊息ADDR0至 系統記憶體260讀取資料，例如同步動態隨機存取記憶體 (SDRAM)中。， 在上述情況下，假如主控器212也要讀取系統記憶體 260的資料時，同樣地，主控器212會發出一讀取要求，接 著此讀取要求之位址，例如位址ADDR1，同樣會被儲存在 位址佇列222，控制器230會將位址ADDR1送給資料資源 集240以要求資料，同時送出停止訊號至PCI匯流排250 中，以釋放出PCI匯流排250供其他裝置使用。接著資料 資源集240會依據此位址訊息ADDR1至系統記憶體260讀 取資料。 若主控器211之要求訊息再來時，控制器230同樣檢 查此讀取要求之位址ADDR0，是否在位址佇列222中，此 時，發現此位址已經在位址佇列222中，控制器230會繼 續判斷對應位址ADDR0之資料訊息DATA0是否已儲存在 資料佇列221。若資料佇列221中沒有對應位址ADDR0之 資料DATA0時，控制器230同樣地會再送出停止訊號至 PCI匯流排250中，以釋放出PCI匯流排250。若資料資源 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） — — — — — _ I批衣 ϋ I I I訂 I 線 (請先閱讀背面之注意事項再填寫本頁) 521184 4 Ο 2 41 w f. d 〇 c / Ο Ο 5 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明説明（β ) 集240已將對應位址ADDRO之資料DATAO送至資料佇列 221中時，此時控制器230建立資料通路，以將此資料 DATA0送至主控器211中。當主控器211接收完資料 DATA0後’位址ADDR0會從位址佇歹[j 222中消除，以代 表完成資料讀取動作。 若主控器212之要求訊息再來時，其操作方法同上所 述。換句話說，每隔一段時間主控器211與212會送出要 求訊號來查詢其所要求之資料是否準備好，不論主控器211 與212誰先要求，只要資料資源集240 —準備好資料，即 傳送對應位址ADDR0或ADDR1之要求資料DATA0或 DATA1至資料佇列221中，等到主控器211或212之要求 訊號再來時，主控器211或212可立即得到其所要求之資 料訊息。 綜上所述，本發明具有以下優點： (Ό目標裝置在準備資料時，主控器不會持續佔據PCI 匯流排，使得PCI匯流排可經常保持在閒置狀態，讓其他 週邊連接裝置可隨時相互通訊。 (2) 可同時對多個主控器之讀取要求，進行資料準備的 動作’增進整體系統效率。 (3) 可大大地縮短主控器要求資料的延遲時間。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 I I I —裝— ! I訂 I « 線 (請先閲讀背面之注意事項再填寫本頁)、 1T This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 521184 A7 4024twf.doc / 005 ____B7 V. Description of the invention (畛) Pending period 26b. At cycle T5, TRDY is sent again, indicating that the data is ready, and during the data transfer cycle 2 8b sent by both IRDY and TRDY signals, the initiator reads the data from the target device. When the initiator is too late to read the data, the initiator sends an IRDY signal at the end of cycle T6. At this time, because the TRDY signal is still sent, this waiting period 26c is initiated by the initiator. After the initiator is ready, the IRDY signal is sent at cycle T7. At this time, during the data transfer cycle 28c where both IRDY and TRDY signals are sent, the initiator reads data from the target device. This completes the first read operation. Generally, in any given bus cycle, only one master can communicate via the bus. Therefore, each device that wants to trade data must first request and receive the grant of the master control of the bus before conducting a transaction. In the conventional simple system, the main controller will not release the master control of the bus before completing the data transaction. However, in some cases, the host controller may be forced to give up the master control of the bus. For example, when the target device cannot respond to the request of the host controller in real time, the target device may send an appropriate signal to notify the host controller. Give up control of the bus. In the PCI bus protocol specification (such as version 2.1), there is a data transaction method called delayed transaction. The so-called delayed transaction refers to the operating procedure used by the target device (Target) under the definition of the PCI specification to fail to complete the initial data phase. There are two main types of devices that handle delayed transaction operations: I / O controllers and bridges ° This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) --- ---- 1--ί installed ------- order ------ line (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy doc / 005 A7 B7 V. Description of the invention (f) The operation procedure of the delayed transaction includes three phases: 1. The host controller issues a request to access the target device on the PCI bus. After the target device remembers this request, the target device Start a Target Initiated Termination with Retry on the PCI bus, also known as Delay Transaction Termination, to actively end this request; then, 2. The master device should prepare the master control Finally, 3. The host controller actively re-issues the original request to access the target device 'to complete the data transaction. During the entire delayed transaction, the host controller will continue to issue PCI bus query messages. , And occupy the right to use the PCI bus, and continue to send polling operations to the target device. For the access method of the host controller, the earlier method is no delay data transaction For example, please refer to Figure 1 and Figure 2 at the same time. When the host controller (initiator) such as the network interface 16c issues a read request, the data in the system memory 11 must be read. The bridge 12 (target device) cannot immediately read and prepare the data from the system memory 11. At this time, the main bridge 12 continuously keeps the TRDY signal inactive, even if the waiting period 26a of the data period 24a is extended until the master The bridge 12 prepares the data. After the main bridge 12 sends a TRDY signal, the network interface 16c can actually read data. Because the network interface 16c is performing a read operation, the PCI bus 14 is affected by the network interface 16c. The read request is occupied. At this time, if another host controller such as the SCSI interface 16d also reads the data of the system memory 11, or communicates with the graphics interface 16a, it will not be allowed to use PCI. 7 papers Zhang scale is applicable to China National Standard (CNS) A4 specification (210X 297 mm) ------- 1--f equipment -------- IT ------ ^ (Please read the note on the back first Please fill in this page again) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521184 A7 4024twf.d〇c / 00 5 _B7___ 5. Description of the Invention (t) Row 14, which means that any request issued will be considered as Invalid, it is necessary to wait until the network interface 16c completes the read operation and releases the PCI bus 14 before the SCSI interface 16d can perform the read operation through the main bridge 12 through the PCI bus 14. Therefore, this kind of non-delayed data transaction method has not met the requirements of efficiency. It is known that another method is a single delay delayed transaction method. The so-called single delay means that although the target device has the ability to process delayed transactions, it can only process the demand for one delayed transaction, that is, after the target device issues a delayed transaction termination and before the data corresponding to the delayed transaction termination is not actually transmitted. , Other data transaction requirements for this target device, although this target device is still obtained to delay the transaction termination response, but the target device is deemed to have never received these data transaction requirements. For example, please refer to Figure 1 and Figure 3 at the same time. Figure 3 shows a bus time-consuming diagram of delayed transactions using a single delay when multiple masters request data on the same target device. First, when the network interface 16c (the first master controller) issues a read request to read the data of the system memory 11, the main bridge 12 (target device) cannot be read by the system memory 11 and is ready Data, at this time, the main bridge 12 issues a retry target start termination, that is, a delayed transaction termination is issued to notify the network interface 16c to release the PCI bus 14, and a read request is issued from the network interface 16c to release it. The PCI bus 14 occupies a total of T1 r time of the PCI bus. After that, the main bridge 12 starts to read data from the system memory U, and it takes about Td time to prepare the data. Because the SCSI interface 16d (second master controller) also needs to access the data of the system memory 11, the SCSI interface 16d also targets the main bridge π. 8 The ^^^ degree is applicable to the Central Clearance Standard (CNS) A4 Specifications (2 runs 297 male diamonds 1 --------- ------- ^-rt -------- IT ----- ά. (Please read the back Please fill in this page for the matters needing attention) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521184 4024twf.doc / 005 8 7 B7 V. Description of Invention (q) (Please read the notes on the back before filling this page) Take the request. At this time, because the main bridge 12 can only handle a single delay device, the main bridge 12 cannot handle this request at all. At this time, the main bridge 12 also issues a target with a retry to start and terminate, so that the SCSI The interface 16d releases the PCI bus 14 and sends a read request from the SCSI interface 16d until it releases the PCI bus 14 and takes up the total time of the PCI bus T2rl. When the main bridge 12 is ready to correspond to the network interface 16c After the required information, but because the network interface 16c will not immediately ask the main bridge 12 whether the data is ready, it is assumed that the time required for Tlw Only when the network interface 16c issues a read request, the main bridge 12 and the network interface 16c actually start transmitting data, and this delayed transaction ends after the data transmission time of Tit. For this data read transaction, a total of It takes T1 time, where Tl = Tlr + Td + Tlw + Tlt 〇 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, if the SCSI interface 16d re-issues a read request, it will be T2wl after the last read request. Time, as above, the main bridge 12 sends out a target with retry to start and terminate. It will take a total of T2r2 of the PCI bus to start preparing the required data. After the Td time, the main bridge 12 will The data is ready. Similarly, it will wait for T2w2 time before the SCSI interface 16d will issue a read request. After the main bridge 12 and the SCSI interface 16d use T2t time to truly transmit data, this delayed transaction ends. For this data read transaction It takes a total of T2 time, where T2 = T2rl + T2wl + T2r2 + Td + T2w2 + T2t. As can be seen from the foregoing, the latency of the data transaction on the network interface 16c is τΥατι = Td + T〗 w However, the paper size of the SCSI interface I6d is applicable to the Chinese paper standard (CNS) A4 (210X297 mm) 521184 4024twf.d〇c / 005 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ?) The easy delay time is TLAT2 = T2wl + T2r2 + Td + T2w2. In general, since T2wl is greater than the real transmission time Tit and the data transmission time Tit is longer than the data preparation time Td, the delay time TLAT2 of the data transaction on the SCSI interface 16d is greater than 2 Td + T2r2 + T2w2. Therefore, Xi. Knows the single-delay delayed transaction method. While preparing the data required for the network interface 16c, other masters can still communicate with each other through the released PCI bus 14. However, once the SCSI interface 16d is read, When fetching the data from the system memory 11, it takes more time than the previous method without delaying transactions. In view of this, the object of the present invention is to provide a device for multi-delay read transactions and an operation method thereof, in order to improve the problem that the conventional single delay transaction method causes a long delay time. Another object of the present invention is to provide a multi-delay read transaction device and an operation method thereof, which can perform data retrieval operations on the reading requirements of multiple masters at the same time, so as to shorten the required data of individual masters. Delay time. To achieve the above and other objectives, the present invention provides a multi-delay read transaction device connected to a PCI bus, and the PCI bus is connected to at least one master controller to form a PCI bus system. Devices for reading transactions include: request queues, data resource sets, and controllers. The request queue coupled to the PCI bus can store multiple addresses in the request signals of these masters, and store multiple data messages corresponding to these addresses. The data resource set coupled to the request queue can retrieve corresponding data messages according to the addresses of these request signals and transmit these data messages to this paper. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Clothing II —. I —i order IIII n line (please read the notes on the back before filling out this page) 521184 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4024twt'.doc / 005 A7 ____B7 ____ 5. Description of the invention ( f) Send to the request queue. The controller is coupled to the PCI bus, request queue, and data resource set. After such a multi-delay read transaction device receives the request # 1 from these masters, the controller checks the addresses of these request signals. Then, when these addresses do not exist in the request queue, the addresses are stored in the request queue, and the controller will issue a delayed transaction termination to the PCI bus, and the controller requests the data resource set to correspond to these addresses. Data message; when these addresses already exist in the request queue, but the data messages corresponding to these addresses do not exist in the request queue, the controller issues a delayed transaction to terminate to the PCI bus; when these addresses already exist in the Request queue, and the data messages corresponding to these addresses are also stored in the request queue, and the data messages corresponding to these addresses are responded to the corresponding master controller, and these addresses in the request queue are eliminated. The above request queue includes an address queue and a data queue. The address queue is used to store the addresses of these request signals, and the data queue is used to store data messages corresponding to these addresses. The above data resource set is coupled to a system resource memory, and the system resource memory stores these data messages. The operation method of the multi-delay read transaction device provided by the present invention includes the following steps: first receiving a plurality of request signals of the main controllers, and then checking the plurality of addresses of the request signals. Then, when these addresses do not exist in the request queue, the addresses are stored in the request queue, and the controller issues a delayed transaction to terminate to the PCI bus. At the same time, the controller requests the data resource set to correspond to these addresses. Data message .; When these addresses already exist in the request queue, and the data messages corresponding to these addresses do not exist in the request queue 11 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (please first Read the notes on the back and fill in this page)-Binding · 521184 4〇24twf.doc / 〇〇5 A7 B7 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 5. When the description of the invention (β) is delayed The transaction is terminated to the PCI bus. After the data resource set accepts the controller's request, it fetches the corresponding material information according to these addresses, and sends these data messages to the request queue for temporary storage. Then, the request signals of these masters are received and the addresses of these request signals are checked. When these addresses already exist in the request queue, and the data messages corresponding to these addresses are stored in the request queue , Respond to the corresponding data messages of these request signals to the corresponding master controller, and eliminate the addresses corresponding to these data messages in the request queue. The invention provides a multi-delay read transaction device and an operation method thereof. The device can simultaneously read data from multiple master controllers and prepare data corresponding to the above read requests. At the same time, the PCI bus can be kept idle at any time. "State" allows other peripheral connected devices to communicate with each other at any time, so as to make full use of the PCI bus and a lot of functions to reduce the delay time of required data, so as to solve the problem of too long delay time encountered in the conventional single delay transaction method. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 Shows an architecture diagram of using PCI system in computer architecture; Figure 2 shows the system timing diagram when a read operation is performed; Figure 3 shows when multiple masters are on the same target The device requires data and uses the conventional time-delayed diagram of a single-delayed bus transaction. Figure 4 shows a multi-delayed transaction 12 according to a preferred embodiment of the present invention. ^ The paper size applies the Chinese National Standard (CNS) A4. Specifications (210X297 mm) I. " I ---:-" Γ Γ Install ------- order -----. Line (Please read the precautions on the back before filling in this page) 10: Central processing unit 12: Main bridge 16a: Graphic interface 16c: Network interface 20: Bus transaction 24: Data cycle 28: Data transmission cycle 521184 4024t.wf.doc / 005 A 7 B7 V. Description of the invention (丨 丨) Easy system timing diagram; Figure 5 shows when multiple masters are on the same target device Seeking resource materials' use of the present invention is a multi-bus transaction delay of the delay time consuming; and FIG. 6 shows the reading device is a block diagram of the transaction according to one embodiment of a preferred embodiment of the present invention is a multi-delay. .Symbol description of the figures: 11, 260: System memory 14, 250: PCI bus 16b: Extended bus bridge 16d: SCSI interface 22: Address cycle 26: Wait cycle 30, 211 ~ 213: Master controller 200: Multi-delay read transaction device 220: Requirement queue 221: Data queue 222: Address queue 230: Controller 240: Data resource set embodiment Please refer to Figure 4 and cooperate with Figure 1, which shows the application System timing diagram of a multi-delay transaction according to a preferred embodiment of the present invention. In Figure 4, the master controller, such as the network interface 16c (the first master controller) and the SCSI interface 16d (the second master controller) in Figure 1, sends out four different read cycles to Access the target device (master bridge 12) on the PCI bus 14. At cycle T1, the network interface 16c issued a request signal reqi requesting the use of the PCI bus 14; while for the SCSI interface 16d, the Chinese paper standard (CNS) A4 specification (210X297 mm) applies to this paper on week 13. I ----- ^-Γ installed ------- order ------- line (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521184 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4024twf.doc / 005 8 7 __B7___ V. Description of the Invention (/ >) The signal REQ2 is issued at T8 and requires the use of PCI bus 14. The main bridge 12 responds to the consent signals GNT1 and GNT2 at periods T2 and T9, and agrees that the network interface 16c and the SCSI interface 16d use the bus 14. The network interface 16c sends a FRAME signal at period T3 to indicate that data transactions can begin. At clock T3, the address is sent to the AD bus, and the read command and the byte enable (BE) signal are sent to the CBE. At period T4, the network interface 16c sends an IRDY signal, indicating that the network interface 16c is ready. At this time, the main bridge 12 will keep this request in memory and start to prepare the data message corresponding to this request, because the TRDY signal of the main bridge 12 is not sent, it means that the main bridge 12 cannot send the data to the network in time. In the road interface 16c, the main bridge 12 will respond to a delayed transaction termination, that is, in the period T5, it sends a stop signal STOP, and the network interface 16c ends sending the request signal REQ1. Secondly, the SCSI interface 16d sends a FRAME signal at cycle T10 to indicate that data reading transactions have begun, and sends out an address at the AD bus at clock T10 and a read command and a byte enable (BE) at the CBE. Signal. An IRDY signal is sent at period T11 to indicate that the SCSI interface 16d is ready. At this time, because the main bridge 12 is a multi-delay read transaction device of the present invention, the main bridge 12 will also record this request and begin to prepare data messages corresponding to this request. At this time, the target device ( The TRDY signal of the main bridge 12) was not sent, indicating that the main bridge 12 could not send data to the SCSI interface 16d in time, and then the main bridge 12 would respond to a delayed transaction termination. At the period T12, the main bridge 12 sent I. ϋ 11111, ^ n 111111 ^ 1111II 'line (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) 521184 4 0 2 41 w f. d 〇c / 0 0 5 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (#) The data reading transaction is started, and the same address as the previous request is sent on the AD bus. Send a read command at CBE. In cycle T30, the main bridge 12 sends out a TRDY signal, and the data acquisition cycle is started (cycles T30 to T37). For example, please refer to FIG. 1 and FIG. 5 at the same time. FIG. 5 shows a bus time-consuming diagram of the multi-delayed delayed transaction when the multiple masters request data on the same target device. • First, after the network interface 16c (the first master controller) issues a read request to read the data of the system memory Π, the main bridge 12 (target device) cannot be read and prepared by the system memory 11 immediately At this time, the main bridge 12 will keep this request in memory, and will begin to prepare the information message corresponding to this request. At the same time, it will send a target with a retry to start and terminate, that is, it will issue a delayed transaction termination to notify the network interface 16c to release. The PCI bus 14 is output, and the time from the read request from the network interface 16c to the release of the PCI bus 14 occupies a total of Tlr of the PCI bus. After that, the main bridge 12 starts to read data from the system memory Π, and it takes about Td time to prepare the data. Because the SCSI interface 16d (second master controller) also needs to access the data in the system memory 11, the SCSI interface 16d also uses the main bridge 12 as the target device to issue a read request. At this time, because the main bridge 12 This is a multi-delay read transaction device of the present invention, so the master bridge 12 will also keep this request in mind, and will begin to prepare information messages corresponding to this request. The master bridge 12 will also issue a target with retry. Startup termination, so that the scsi interface 16 (1 releases the PCI bus 14, among which a read request is issued from the SCSI interface 16d until it releases the PCI bus 14, occupying the PCI bus 16 degree. CNS A4 specification (21GX297 mm 1 ~-:-I --------. I, Γ installed ------- order ------ line (Please read the precautions on the back before filling in this Page) 521184 40 2 4twf. Doc / O 0 5 A7 B7 V. Description of the invention (/ 〇 Total T2rl time. After that, the main bridge 12 began to read data from the system memory billion 11, it takes about Td time to Prepare the information (Please read the precautions on the back before filling this page) When the main bridge 12 has prepared the information corresponding to the network interface i6c However, because the network interface 16c will not immediately ask the main bridge 12 whether the data is ready. Assuming that T1 w must be waited before the network interface 16c issues a read request again, the main bridge 12 and the network interface i6c The data transmission actually started, and the delayed transaction was ended after the data transmission time of T11. For this data reading transaction, a total of T1 time is required, of which Tl ^ Tlr + Td + Tlw + Tlt 〇 Then, when the main bridge The device 12 is also prepared to correspond to the information required by the SCSI interface 16d. 'Ask the sample' because the SCSI interface 16d will not immediately come to ask the main bridge 12 whether the data is ready. Assuming that you must wait for T2w2, SCSI The interface 16d only issues a read request, and the main bridge 12 and the SCSI interface 16d actually start transmitting data. After the data transmission time of T2t, the delayed transaction is ended. For this data reading transaction, a total of T2 time is required , Where T2 = T2rl + Td + T2w2 + T2t. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. As can be seen from the foregoing, the delay time for data transaction on the network interface 16c is TLAT1 = Td + Tlw, and the SCSI interface 16d The delay time of the data transaction is Tlat2 = T (1 + T2w2. Therefore, comparing the data reading transaction time consumed by the SCSI interface 16d of the present invention with the previously mentioned single-delayed delayed transaction method, the present invention compares The known method can reduce the data reading transaction time of about T2wl + T2i * 2. Therefore, since the present invention can perform the data preparation action on the reading requirements of multiple master controllers at the same time, the master controller requirements can be greatly shortened The delay time of the data, thereby improving the overall system efficiency. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 521184 4024twf. Doc / 005 A7 B7 V. Description of the invention (/ &) Please refer to Figure 6, It shows a block diagram of a multi-delay read transaction device according to a preferred embodiment of the present invention. The multi-delay read transaction device 200 of the present invention can be designed and laid out in a main bridge such as a chipset, which includes a request queue 220, a controller 23, and a data resource set ( data poll) 240, where the required queue 220 is composed of a data queue 221 and an address queue 222. The request queue 220 is coupled to the PCI bus 250, and the internal address queue 222 is used to store the address of the required signal of the master controllers 211 to 213, and the data queue 221 is used to store the corresponding master controllers 211 to 213. Information message requesting the address of the signal. The controller 230 is also connected to the PCI bus 250. At the beginning, the address queue 222 in the bus 220 was not stored with any address. When the controller 230 receives the request signal, the controller 23 will send out Upon stopping the signal STOP to the PCI bus 250 to release the PCI bus 250 for use by other devices, the address of the requested signal at this time will be stored in the address queue 222, and the controller 230 will also send Request the address of the signal to the data resource set 24, in order to prepare the data message corresponding to this address. The data resource set 240 is coupled to the request [J220 and the controller 230, and the general data resource set 240 will be connected to the system memory 260. It will retrieve the corresponding data message in the system memory 26 according to the address of the request signal. The corresponding data message is transmitted to the data of the request Ning Lei 220 and the Ning Lei 221. The operation method of the multi-delay read transaction device of the present invention is described below. When the main controller 211 issues a read request to read the data in the system memory 26, the controller 230 first checks the address of the read request. For example, the paper size of 18 is applicable to ^ _ ^ home standard ((: milk) 8 4 specifications (210 father 297 mm) '" ---- I ------- I equipment ------ -Order ------ line (please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521184 4024twf.doc / 005 B7__ V. Description of Invention (, 7) Address ADRO, Whether it is in the address queue 222, because the address queue 222 in the queue 220 is not required to store any address at first, the address ADDRO will be stored in the address queue 2D. Then the controller 230 The address ADDR0 will be sent to the data resource set 240, and a stop signal will be sent to the PCI bus 250 to release the PCI bus 250 for use by other devices. For example, the main controller 212 can communicate with the host through the PCI bus 250 The controllers 213 communicate with each other. Then the data resource set 240 will read data from the system memory 260 according to the address information ADDR0. For example, in synchronous dynamic random access memory (SDRAM). In the above case, if the main controller 212 also reads the data of the system memory 260, the main controller 212 will also issue a read request Then, the address of the read request, such as the address ADDR1, will also be stored in the address queue 222. The controller 230 will send the address ADDR1 to the data resource set 240 to request data, and send a stop signal to the PCI. In the bus 250, the PCI bus 250 is released for use by other devices. Then the data resource set 240 will read data from the address information ADDR1 to the system memory 260. If the request message from the main controller 211 comes again, The controller 230 also checks whether the address ADDR0 of this read request is in the address queue 222. At this time, it is found that the address is already in the address queue 222, and the controller 230 will continue to judge the corresponding address ADDR0. Whether the data message DATA0 is stored in the data queue 221. If there is no data DATA0 corresponding to the address ADDR0 in the data queue 221, the controller 230 similarly sends a stop signal to the PCI bus 250 to release the PCI bus Row 2 50. If the resource of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) — — — — — _ I batch of clothes III order I line (please read the precautions on the back before filling this page) 521184 4 Ο 2 41 w f. D 〇c / Ο Ο 5 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Invention Description (β) Episode 240 The data DATAO corresponding to the address ADRO has been sent to the data queue 221 During the middle time, the controller 230 establishes a data path to send the data DATA0 to the main controller 211. When the main controller 211 receives the data DATA0, the address ADDR0 will be deleted from the address 伫 歹 [j 222, which represents the completion of the data reading operation. If the request message from the main controller 212 comes again, the operation method is the same as described above. In other words, every once in a while, the main controllers 211 and 212 will send a request signal to inquire whether the required data is ready, no matter who the main controllers 211 and 212 request first, as long as the data resource set 240-ready the data, That is, the request data DATA0 or DATA1 corresponding to the address ADDR0 or ADDR1 is transmitted to the data queue 221, and when the request signal from the main controller 211 or 212 comes again, the main controller 211 or 212 can immediately obtain the requested data message. . In summary, the present invention has the following advantages: (Ό When the target device is preparing data, the main controller will not continue to occupy the PCI bus, so that the PCI bus can always be kept idle, so that other peripheral connecting devices can communicate with each other at any time. Communication. (2) It can read data from multiple masters at the same time and perform data preparation actions to improve the overall system efficiency. (3) It can greatly reduce the delay time of data required by the masters. Although the present invention has been The preferred embodiment is disclosed above, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be regarded as The attached patent application shall be as defined by the scope of the application. III —Installation —! I Order I «Line (Please read the notes on the back before filling this page)