TW520555B - Double data rate synchronous dynamic random access memory and its manufacturing method - Google Patents

Abstract

A kind of double data rate synchronous dynamic random access memory (DDR SDRAM) and the manufacturing method of DDR SDRAM are disclosed in the present invention. At first, a semiconductor substrate is provided. The conventional photolithography technique is used to define memory cell device region; and the trench type capacitor is formed at the memory cell device region. The active device region is defined at the memory cell device region, and shallow trench isolation is formed in between the active device regions. A polysilicon layer is formed on the semiconductor substrate; and by using photolithography and anisotropic etching technique, the vertical active device region polysilicon is formed. A silicon oxide layer, a polysilicon layer and a covering layer are consecutively formed on the semiconductor substrate. By using the photolithography and anisotropic etching technique, the silicon oxide layer, the polysilicon layer and the covering layer on top of the shallow trench isolation in the horizontal direction are removed to form the vertical gate silicon oxide layer, the vertical gate conduction layer and the vertical gate covering layer. On the vertical active device region polysilicon, a contact window opening is formed; and a contact window doped region is formed inside the active device region polysilicon by using ion implantation technique through the contact window opening. Finally, the contact window plug is formed.

Description

520555

Detailed description: Technical field: The present invention relates to a type of synchronous dynamic random access memory, and in particular to a manufacturer of synchronous dynamic random access memory with a double density. Background of the Invention: Dynamic Access Memory (Dynamic R and ◦ m Acess Memory (DR AM) is an important component used to store digital information. Synchr〇n〇us Dynamic RandQm

Access Memory (SDRAM) is a type of DRAM, which is characterized in that data transmission is synchronized with a inch clock signal (clock signai). Another type of DRAM commonly used in the industry is the Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), which differs from SDR AM in that it is a transition in the clock signal The data transmission is performed at a place, that is, it will be transmitted twice in each clock cycle, so its transmission rate is twice that of SDRAM. In terms of existing DRAM technology, both SDRAM and DDR SDRAM use trench cell capacitor structure. Please refer to Figure 1, which is a schematic cross-sectional view of a conventional trench capacitor DRAM. The trench-type capacitor DRAM is formed on a semiconductor substrate 10, which includes a P-type well 12, a capacitor 14, a shallow trench isolation (STI) 16, a buried strap 18, Word line (word 1 ine) 20, contact window 22, etc., wherein the word line

V. Description of the invention (2) The 20-series three-layer salute, the silicon nitride layer has a polycrystalline silicon layer 20a, a tungsten silicide layer 20b, and a half of the DRAM. Figure A The area of fg Z ^ of a conventional element with a trench capacitor is very large, and it is difficult to increase the element density, so that the cost of clothing cannot be reduced. Body | Tπ on /,. Storage retention time (retention time and reliability 2 lty) are the main considerations of DRAM products. How to make use of the existing, two, four, and under the condition that the process steps are minimized, reducing the component density and increasing the component density is the first aspect of the industry's first research and development. Vertical M0S components have been It is used for wireless communication. For example, U.S. Patent No. 6,184,090 approved by Lianhua Electronics Co., Ltd. discloses a method for forming a vertical MOS device (Fabrication Method For a Vertical MOS Transistor). The vertical m0s element formed is formed on a semiconductor substrate 'plate 30, which includes shallow trench isolation 3 2, a first doped layer 3 4, a second doped layer 36, and a third doped layer. Miscellaneous layer 38, gate silicon oxide layer 40, conductive layer 42, and dielectric layer 44. However, the 'vertical MOS device has not been applied to the structure and manufacturing method of DRAM, as shown in Figure 2. SUMMARY OF THE INVENTION The main object of the present invention is to provide a double data density synchronous dynamic random access memory. A secondary object of the present invention is to provide a method for manufacturing a double data density synchronous dynamic random access memory.

-6-5j ^ 55 (3) Another object of the present invention is to provide a double data density and double data rate synchronous dynamic random access memory. Another object of the present invention is to provide a method for manufacturing a double data density and double data rate synchronous dynamic random access memory. The invention discloses a manufacturing method of a double data density synchronous dynamic random access memory and a double data density double data rate synchronous dynamic random access memory. First, a semiconductor substrate is provided, and the memory is defined by using a traditional lithography technology. A cell element region 'forms a trench capacitor in the memory cell element region. Afterwards, active element regions are defined in the memory cell element regions, and shallow trench isolation is formed between the active element regions. Next, a polycrystalline silicon layer is formed on the semiconductor substrate, and then a polycrystalline stone in the vertical active element region is formed by using lithography and anisotropic etching techniques. Next, a silicon oxide layer, a polycrystalline silicon layer, and a cover layer are successively formed on the semiconductor substrate, and the photolithography and anisotropic etching techniques are used to isolate the horizontal direction above the shallow trench isolation. The silicon oxide layer, the polycrystalline stone layer, and the cover layer are removed to form a vertical gate silicon oxide layer, a vertical gate conductive layer, and a vertical gate cover layer. A contact window opening is formed in the vertical active device region complex silicon, and an ion implantation technique is used to pass through the contact window opening to form a contact window doped region in the active device region complex silicon. Finally, a contact window plug is formed. The double data density synchronous dynamic random access memory and the double data density double data rate synchronous dynamic random access memory system disclosed in the present invention are located in an active device area on a semiconductor substrate, which includes a trench capacitor, A vertical active device region complex silicon, a vertical gate silicon oxide layer,

Page 7 520555 V. Description of the invention (4) A vertical gate conductive layer, a vertical gate cover layer, and a contact window plug. Around the active element area is a shallow trench isolation. The trench capacitor is located in the active element region of the semiconductor substrate, and the height of the top surface is the same as the height of the top surface of the semiconductor substrate. The trench capacitor includes a deep trench, a first silicon oxide layer, a first polycrystalline silicon layer, a second silicon oxide layer, a second polycrystalline silicon layer, and a buried layer (b u r e d s s t r a p). The deep trench is located in an active device region in the semiconductor substrate, and the first silicon oxide layer extends upward from a bottom of the deep trench and is closely attached to a side wall of the deep trench. The first polycrystalline silicon system extends upward from the bottom of the deep trench and is located in an area surrounded by the first silicon oxide layer in the deep trench. The second silicon oxide layer extends upward from the top of the first silicon oxide layer and the first polycrystalline silicon, and is closely attached to the side wall of the deep trench. The second polycrystalline silicon system extends upward from the top of the first silicon oxide layer and the first polycrystalline silicon, and a top surface thereof is higher than a top surface of the second silicon oxide layer and is located in the deep trench. Within a region surrounded by the second silicon oxide layer in the trench. The buried zone (b u r e d s t r a p) is located on top of the second oxide stone layer and the second polycrystalline stone layer, and the height of the top surface is the same as the surface height of the semiconductor substrate. Wherein, the vertical active element region polycrystalline silicon system is located on the trench-type electric cell as a word line. The gate silicon oxide layer is coated on the surface of the polycrystalline silicon in the vertical active device region. The gate conductive layer is a polycrystalline silicon layer, and is coated on the surface of the gate silicon oxide layer. The gate cover layer further covers the surface of the gate conductive layer, wherein the gate cover

Page 8 520555 V. Description of the invention (5) The capping layer includes a gate stone layer and a gate nitride layer. The contact window plug is located on the polycrystalline silicon in the active device region, and is composed of polycrystalline silicon. The bottom of the contact window plug is connected to the vertical active device region polycrystalline silicon and extends through the vertical gate silicon oxide layer, the vertical gate conductive layer, and the vertical gate cover layer. Layer-by-layer silicon tungsten dagger / 1/1 oxygen silicon pole pole opening gate window directly touching vertical vertical connection drawing number description 1 0-semiconductor substrate 14-capacitor 1 8-buried tape 2 0 a compound silicon layer 2 0 c Nitride stone layer 3 0-semiconductor substrate 3 4-first doped layer 3 8-third doped layer 4 2-conductive layer 1 0 0-semiconductor substrate 104-first oxide stone layer 1 0 8-second Silicon oxide layer 1 1 2-buried zone 1 2 2-polycrystalline silicon layer

1 2-P-type well 1 6-Shallow trench isolation 2 0-Word line 2 0 Tungsten layer 2 2-Contact window 3 2-Shallow trench isolation 3 6-Second doped layer 4 0-Gate Oxide stone layer 4 4-Dielectric layer 1 0 2-Deep trench 1 0 6-First polycrystalline silicon 1 1 0-Second polycrystalline silicon 1 2 0-Shallow trench trench isolation and fragmentation Various nitrogen-conducting parts, pole-doped gates, and windows move directly to the main vertical connection

520555 V. Description of the invention (6) 1 3 8-Contact window plug The present invention relates to a double data density synchronous dynamic random access memory and a double data density double data rate synchronous dynamic random access memory, especially The invention relates to a manufacturing method of double data density synchronous dynamic random access memory and double data rate synchronous dynamic random access memory. i The present invention combines the conventional trenched capacitor DRAM and vertical MOS device technology to form double data density synchronous dynamic random access memory and double data density double data rate synchronous dynamic random access memory, which not only enables Double the component density while reducing component leakage. ^ First refer to FIG. 3, apply a layer of photoresist (not shown) on a piece of semiconductor substrate 100, define the active device area using traditional lithography technology, and use the conventional anisotropic etching technology to The active device region forms a deep trench 102. Next, a thermal oxidation technique or a chemical vapor deposition (C V D) method is used to form an oxide layer 104 on the substrate. Next, a chemically vapor-deposited method and anisotropic etching technology are used to form a strongly doped first polycrystalline silicon 1 0 6 in a region surrounded by the first silicon oxide layer 1 0 4 in the deep trench 102. . Next, a chemical vapor deposition method is used to form a silicon oxide layer on the first silicon oxide layer 104 and the first polycrystalline silicon 106 in the deep trench 102, and then anisotropic is used. An etching technique is used to remove the horizontal portion of the silicon oxide layer to form a second silicon oxide layer 108, as shown in FIG. Next, referring to FIG. 4, a layer of lightly doped polycrystalline silicon is formed on the first silicon oxide layer 104 and the first polycrystalline silicon silicon 106 in the deep trench 102 by using a chemical vapor deposition method. Silicon layer, and then use the conventional etch-back technology or chemical machine

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1 Polishing; CMp) forming the first step 112) to form a trench mechanical polishing method (Chemical Mechanica 110) and buried capacitor (trench capacitor). In other embodiments of the present invention, it can also be used. Any other, forming the trench capacitor. Any improvements and modifications of the trench capacitor are also the scope of the present invention. ^ Please refer to Figure 5 between the active device areas. Shallow Trench Isolation (STU120) is formed. The method of forming the shallow trench isolation 1 2 0 is to first coat a photoresist on the semiconductor substrate 1000 (not shown in the figure) Then, the traditional lithography technology is used to define the shallow trench isolation area between the active element areas, and the conventional anisotropic silver engraving technology is used to form a shallow trench in the shallow trench isolation area. Next, the chemistry is used. A vapor deposition method is used to form a silicon oxide layer on the semiconductor substrate 1000, and then a chemical mechanical polishing method is used to remove the oxide layer on the surface of the semiconductor substrate 1000 to form a shallow layer. Trench isolation 1 2 0. Next, please refer to FIG. 6, using a conventional chemical vapor deposition method or an epitaxial technique to form a polycrystalline silicon layer 1 2 2 on the semiconductor substrate 100, and then use a conventional lithography. And anisotropic etching techniques are used to form the polycrystalline spar 1 2 4 of the vertical active element region, as shown in FIG. 7. Next, referring to FIG. 8, a chemical vapor deposition method is successively formed on the semiconductor substrate 100 A layer of silicon oxide, a layer of polycrystalline silicon, a layer of silicon oxide, and a layer of silicon nitride, and use lithography and anisotropic etching technology to isolate the horizontal trench above the shallow trench 1 2 0. The oxide stone layer, polycrystalline stone layer, tungsten silicide layer and silicon nitride layer are removed to form a vertical layer.

Page 11 520555 V. Description of the invention (8) Gate silicon oxide layer 1 2 6, vertical gate conductive layer 1 2 8, vertical gate tungsten silicide layer 1 3 0 and vertical gate silicon nitride layer 1 3 2. Next, please refer to FIG. 9, using conventional lithography and etching techniques to form a contact window opening 1 3 4 in the vertical active element region 1 2 4, and using an ion implantation technique to pass through the contact window opening 1 3 4. A contact window doped region 1 3 6 is formed in the polycrystalline silicon 1 2 4 in the active device region. Next, please refer to FIG. 10. First, a conventional chemical vapor deposition method is used to form a polycrystalline silicon layer on the semiconductor substrate 1000, and then a conventional photolithography and etching technique is used to form a contact window plug 1 38. The manufacturing process of the double-data-density synchronous dynamic random access memory of the vertical active device disclosed in the present invention is completed. Next, please continue to refer to FIG. 10 to describe the double data density synchronous dynamic random access memory and the double data density double data rate synchronous dynamic random access memory disclosed by the present invention. The double data density synchronous dynamic random access memory and the double data density double data rate synchronous dynamic random access memory system disclosed in the present invention are located in a vertical active device region on a semiconductor substrate and include a trench capacitor. , A vertical active device region compound silicon, a vertical gate silicon oxide layer, a vertical gate conductive layer, a vertical gate cover layer, and a contact window plug. Around the vertical active element region is a shallow trench isolation. ; Ϊ® wherein the trench capacitor is located in the active element region of the semiconductor substrate, and the height of the top surface thereof is the same as the height of the top surface of the semiconductor substrate. The trench capacitor includes a deep trench, a first silicon oxide layer, a first polycrystalline silicon layer, a second silicon oxide layer, a second polycrystalline silicon layer, and a

Page 12 520555 V. Description of the invention (9) Buried strap. Wherein, the active device region in the deep trench trench substrate, and the bottom of the first oxidation trench extends upwards, and is close to the deep trench, the first polycrystalline silicon system is directed upward from the bottom of the deep trench. The silicon layer in the area surrounded by the first silicon oxide layer in the extended deep trench is extended by the first silicon oxide layer and the first polycrystalline silicon and is closely attached to the side wall of the deep trench. The tops of the first silicon oxide layer and the first polycrystalline silicon are upward and higher than the top surface of the second silicon oxide layer, in a region surrounded by the second silicon oxide layer in the trench. So (b u r i e d s t r a p) is located on top of the second oxide layer, and the height of the top surface is the same as the semiconductivity. The vertical active device region is above the polycrystalline silicon-based container, and is used as a word line. The vertical gate oxygen is between 80 angstroms on the surface of the polycrystalline stone in the vertical active element region. The vertical gate conductive layer is a polycrystalline silicon vertical gate silicon oxide layer, and its thickness is between. The vertical gate cover layer further covers the surface of the layer. The vertical gate cover layer includes a tungsten silicide layer and a vertical gate silicon nitride layer. The thickness of the tungsten silicide layer is between 40 and 40. The thickness of the silicon nitride layer is between 0 angstroms and 700 angstroms, and the thickness of the silicon nitride layer is between 1800 angstroms and 2 500 angstroms. The contact window plug system is located in the vertical active system in the semiconducting silicon. The layer consists of the side walls of the deep trench. The extension is located at the. The top of the second oxidation extends from the top of the second polycrystalline silicon system, and the top surface of the second oxidized polycrystalline silicon system is located in the deep channel buried zone and the surface of the body substrate is higher than the trench. The type of electrochemical silicon layer is coated in a thickness between 5 Angstroms and 300 Å, and is covered by the 600 Angstroms to 120 Angstroms. The vertical gate is conductive and contains a layer of the vertical gate. A description of the compound gate of the vertical gate

Page 13 520555 V. Description of the Invention (Li) The limitation of silicon has also been changed. It is not suitable to the oxygen layer, and in the electrode cover, the connected gates are clearly covered by the Ministry of Justice, and the bottom can also be closed. This is also described by the Mingshi Mingsai, and the human hair is inserted through the detailed window. We will not extend the details and skills to implement this. The description and the actual knowledge are still around, and the layers are well-known and good. The broken battery is more integrated and crystal-guiding for the reorganization and restructuring. It is directly related to the silicon parts of the gate system of the Jingsuo District. It is directly described by Fan Gaiming. So make some, straight, this work is not to hang down the system without # 520555 The diagram is to explain the diagram briefly. Figure 1 is a schematic cross-sectional view of a conventional trench capacitor DRAM. FIG. 2 is a schematic cross-sectional view of a conventional vertical MOS device. FIG. 3 is a schematic cross-sectional view of forming a deep trench and a second silicon oxide layer in the method of the present invention. FIG. 4 is a schematic cross-sectional view of a trench capacitor in the method of the present invention. Figure 5 is a schematic cross-sectional view of forming a shallow trench isolation in the method of the present invention. FIG. 6 is a cross-sectional view of a method for forming a polycrystalline silicon layer in the method of the present invention. FIG. 7 is a schematic cross-sectional view of a method for forming a polycrystalline silicon in a vertical active device region in the method of the present invention. FIG. 8 is a schematic cross-sectional view of forming a vertical gate silicon oxide layer, a vertical gate conductive layer, a vertical gate tungsten silicide layer, and a vertical gate silicon nitride layer in the method of the present invention. FIG. 9 is a schematic cross-sectional view of forming a contact window doped region in the method of the present invention. Figure 10 is a schematic cross-sectional view of the method of the present invention that completes double data density synchronous dynamic random access memory and double data density double data rate synchronous dynamic random access memory.

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Claims (1)

520555 6. Scope of patent application Patent scope: 1. A method for manufacturing double data density synchronous dynamic random access memory, the steps of which include at least: a. Provide a semiconductor substrate, and define the active device using traditional lithography technology Region; b. Forming a trench capacitor in the active element region;-c. Forming a shallow trench isolation between the active element regions; d. Forming a polycrystalline silicon layer on the semiconductor substrate, and then using Lithography and anisotropic etching technology to form a polycrystalline silicon in the vertical active device region; e. Forming a silicon oxide layer, a polycrystalline silicon layer and a cover layer on the semiconductor substrate successively, and using the lithography and non-isotropic layer Isotropic etching removes the silicon oxide layer, the polycrystalline silicon layer, and the cover layer in a horizontal direction above the shallow trench isolation to form a vertical gate oxide layer and a vertical gate conductive layer. And a vertical gate cover layer; f. Forming a contact window opening on said vertical active device region polycrystalline silicon, and using ion implantation technology to pass through said contact window opening Forming a contact window doped region in the vertical active device region polycrystalline silicon; and g. Forming a contact window plug. 2. The manufacturing method of the double data density synchronous dynamic random access memory according to item 1 of the scope of the patent application, wherein the cover layer is composed of a vertical tungsten silicide layer and a vertical silicon nitride layer. Page 16 520555 VI. Patent Application Range 3 · The manufacturing method of the double data density synchronous dynamic random access memory as described in item 1 of the patent application range, wherein the gate covering layer includes a vertical gate tungsten silicide And a vertical gate silicon nitride layer. 4. The manufacturing method of the double-data-density synchronous dynamic random access memory as described in item 1 of the scope of patent application, wherein said trench capacitor is formed. The method comprises: a. Forming a deep trench in the active device region using anisotropic etching technology; b. Forming a silicon oxide layer in the deep trench to form a first silicon oxide layer; c Forming a heavily doped first polycrystalline silicon in a region surrounded by a first silicon oxide layer in the deep trench; d. The first silicon oxide layer and the first silicon oxide in the deep trench A silicon oxide layer is formed on the polycrystalline silicon, and the silicon oxide layer is partially removed in the horizontal direction by using anisotropic etching technology to form a second silicon oxide layer. E. A lightly doped layer is formed by chemical vapor deposition. A heteropolycrystalite layer is etched, and then the lightly doped polycrystalline silicon layer is etched back to form a second polycrystalline silicon and a buriedstrap. 5. The method for manufacturing a double data density synchronous dynamic random access memory according to item 1 of the scope of patent application, wherein the method of forming a contact window plug is firstly using chemical vapor deposition on the semiconductor Shape on substrate Page 17 520555 VI. Scope of patent application Form a layer of polycrystalline silicon, and then use the traditional lithography and etching techniques to form the contact window plug. ** 6. — A method for manufacturing a double data density and double data rate synchronous dynamic random access memory, the steps of which include at least: a. Provide a semiconductor substrate, and define the active-element area using traditional lithography technology; b. forming a trench capacitor in the active element region; c. forming a shallow trench isolation between the active element regions; d. forming a polycrystalline silicon layer on the semiconductor substrate, and then using micro φ. Shadow and anisotropic etching technology to form a polycrystalline silicon in the vertical active element region; e. Forming a layer of stone oxide layer, a polycrystalline silicon layer and a cover layer on the semiconductor substrate successively, and using lithography and non-isotropic The directional etching technology removes the oxidized silicon layer, the polycrystalline silicon layer, and the cover layer in a horizontal direction above the shallow trench isolation to form a vertical, gate silicon oxide layer, and a vertical gate conductive layer. And a vertical gate cover layer; f. Forming a contact window opening on the vertical active element region polycrystalline silicon, and using ion implantation technology to pass through the contact window opening to the vertical active element Region of polysilicon doped region is formed within a contact window; g and a contact plug is formed. 7. The manufacturing method of the double data density and double data rate synchronous dynamic random access memory as described in item 6 of the scope of patent application, wherein said overlay Page 18 520555 VI. Scope of patent application The layer is composed of a layer of vertical stone chemical crane and a layer of vertical nitride stone. 8. The manufacturing method of the double data density and double data rate synchronous dynamic random access memory according to item 6 of the scope of the patent application, wherein the gate cover layer includes a vertical gate stone layer and a layer Vertical gate nitride nitride layer. 9. If applying for a patented synchronous synchronous trench electric a. Using non-ditch; b. On the silicon layer; c. On the doped d. Forming the oxide layer on the above; e. Utilization The method for manufacturing the double-data density double-data fast-state random-access memory according to item 6 of the light-buried band-bearing range, wherein the method of forming a container includes: an isotropic etching technique in the active A deep silicon trench is formed in the deep trench of the element region to form a first oxide silicon layer in a region surrounded by the first silicon oxide layer in the first deep trench. The silicon oxide layer and the first polycrystalline silicon are formed into a silicon oxide layer, and then the silicon layer is partially removed in the horizontal direction by using an anisotropic etching technique to form a second silicon oxide. A vapor doping method is used to form a lightly doped layer. The polycrystalline silicon layer is etched back to form a second polycrystalline silicon and (buried strap). Page 19 520555 VI. Patent application scope_ 10. The manufacturing method of the double data density and double data rate synchronous dynamic random access memory as described in item 6 of the patent application scope, wherein the contact window plug is formed. The method is to first form a polycrystalline silicon layer on the semiconductor substrate by a chemical vapor deposition method, and then use a conventional lithography and etching technique to form a contact window plug. 1 1. A double data density synchronous dynamic random access memory, which is located on a vertical active device region on a semiconductor substrate, and is surrounded by a shallow trench isolation around the vertical active element region, which includes ¥ one trench Capacitors, which are located in the active device region of the semiconductor substrate, the height of the top surface of which is the same as the height of the top surface of the semiconductor substrate; a vertical active device region complex silicon, which is located above the trench capacitor As a word line; a vertical gate silicon oxide layer covering the surface of the polycrystalline stone in the vertical active element region, and a vertical gate conductive layer covering the vertical gate oxide On the surface of the silicon layer; a vertical gate capping layer covering the surface of the conductive layer of the vertical gate; and a contact window plug located on the polycrystalline silicon in the vertical active device region A bottom of the contact window plug is connected to the vertical active device region polycrystalline silicon, and extends through the vertical gate silicon oxide layer, the vertical Page 20 520555 VI. Scope of Patent Application The gate conductive layer and the vertical gate cover layer. 1 2 The double data density synchronous dynamic random access memory according to item 11 of the scope of patent application, wherein the trench capacitor includes: a deep trench, wherein the deep trench is located in the trench An active element region in a semiconductor substrate; a first oxidized stone layer extending upward from the bottom of the deep trench and abutting on a side wall of the deep trench; the first polycrystalline stone formed by The bottom of the deep trench extends upward and is located in an area surrounded by the first silicon oxide layer in the deep trench. A second silicon oxide layer is formed by the first silicon oxide layer and a first compound. The top of the crystalline silicon extends upward and is in close contact with the side wall of the deep trench; the second polycrystalline silicon extends upward from the top of the first silicon oxide layer and the first polycrystalline silicon, and the top surface of the crystalline silicon is Higher than the top surface of the second silicon oxide layer and located in a region surrounded by the second silicon oxide layer in the deep trench; and I »buried strap located on the second oxide Above the top of the Shi Xi layer and the second polycrystalline silicon, The same as the semiconductor substrate surface Fernando. 13. The double data density synchronous dynamic random access memory according to item 11 of the scope of patent application, wherein the contact window plug is composed of polycrystalline silicon. Page 21 520555 VI. Scope of patent application 1 4 · Double data density synchronous dynamic random access memory as described in item 11 of the scope of patent application 'wherein the vertical gate cover layer includes a layer of vertical gate stone The chemical crane layer and a vertical gate nitride nitride layer. 1 5. The double data density synchronous dynamic random access memory according to item 11 of the scope of the patent application, wherein the vertical gate conductive layer is composed of polycrystalline silicon. 16. A kind of double data density and double data rate synchronous dynamic random access memory. It is located in a vertical active device area on a semiconductor substrate, and is surrounded by shallow trenches around the vertical active device area. It includes a trench capacitor, which is located in the active device region in the semiconductor substrate, the top surface of which has the same height as the top surface of the semiconductor substrate; a vertical active device region, polycrystalline silicon, which is located in the trench A vertical gate silicon oxide layer, which is coated on the surface of the complex crystal in the vertical active element region, and a vertical gate conductive layer, which is coated on the vertical On the surface of the gate silicon oxide layer; a vertical gate cover layer covering the surface of the vertical gate conductive layer; and a contact window plug located in the polycrystalline silicon of the vertical active device region The bottom of the contact window plug is connected to the vertical active element area Page 22 520555 6. Scope of patent application Complex crystal silicon, which extends through the vertical gate silicon oxide layer, the vertical gate conductive layer, and the vertical gate cover layer. 17. The double data density and double data rate synchronous dynamic random access memory according to item 16 of the scope of patent application, wherein the trench capacitor includes: a deep trench, wherein the deep trench It is an active element region in the semiconductor substrate. The first oxide layer extends from the bottom of the deep trench and is close to the side wall of the deep trench. 4 ^ First compound Silicon, which extends upward from the bottom of the deep trench and is located in an area surrounded by the first silicon oxide layer in the deep trench; and a second silicon oxide layer, which is formed by the first silicon oxide The top of the layer and the first polycrystalline silicon extend upward and are closely attached to the side wall of the deep trench; the second polycrystalline silicon extends upward from the top of the first silicon oxide layer and the top of the first polycrystalline silicon A top surface thereof is higher than a top surface of the second silicon oxide layer, and is located in a region surrounded by the second silicon oxide layer in the deep trench; and a buried strap, which is located in the On top of the second oxide layer and the second polycrystalline silicon The height of the surface is the same as the height of the surface of the semiconductor substrate. 18. The double data density and double data rate according to item 16 of the scope of patent application, wherein the rate-synchronized dynamic random access memory is in the contact window plug system. Page 23 520555 VI. The scope of patent application is composed of compound crystal; 19. The double data density and double data rate synchronous dynamic random access memory according to item 16 of the scope of patent application, wherein the vertical gate cover layer includes a vertical gate petrified mineralization layer and a layer Vertical gate nitride nitride layer. 20. The double data density and double data rate synchronous dynamic random access memory according to item 16 of the scope of patent application, wherein the vertical gate conductive layer is composed of polycrystalline silicon. · Page 24