TW520549B - Method for etching dielectric layer - Google Patents

Abstract

The present invention provides an etching method of dielectric layer, in which the problems of edge loss and pattern deformation generated when etching the dielectric layer to form openings in the conventional process can be reduced by using two-step etching method and the control of etching selection rate. The invented method contains the following steps. At first, a semiconductor substrate is provided, in which a dielectric layer is formed on the substrate and a patterned mask layer is provided on the dielectric layer. Then, by using the mask layer as the etching mask, the first etching step is conducted onto the dielectric layer. By using the mask layer as the etching mask, the second etching step is performed onto the dielectric layer. The first etching step of etching dielectric layer has a higher etching selectivity relative to the mask layer than the second etching step. Additionally, in a better executed-example, a step of stripping anti-reflection layer can be included before the execution of the first etching step mentioned above, and the anti-reflection layer is located between the mask layer and the dielectric layer.

Description

520549 Printed by A7 B7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the invention () Field of the invention: The present invention relates to a semiconductor process, and in particular, to a dielectric layer etching process method to eliminate edge loss during etching. Or pattern deformation (st ri at ion) problem, providing good control of etch shape and etch selectivity. BACKGROUND OF THE INVENTION: Since the birth of the first integrated circuit components, the flat conductor industry has developed for nearly forty years, and Semiconductor manufacturing technology has also continued to progress to minimize the size of components on the wafer; with advances in process technologies such as deposition, lithography, etching, and heat treatment, the degree of integration of components and circuits on integrated wafers has also increased. In terms of current process technology, a single chip can already hold tens of millions, even hundreds of millions of components. Advances in process technology have also reduced the size of components on integrated circuits to sub-micron (sub- micron) to achieve the goal of higher integration. In the manufacture of semiconductor components, dielectric materials are extremely important materials in applications, and can be used as gate insulation layers, insulation layers between wiring layers, and dielectric layers between capacitor plates. In different applications, a dielectric layer etching process may be required to define the required holes or patterns. Without limiting the spirit and scope of the present invention, the following is the process of etching contact holes or connection holes, which is most frequently applied in the dielectric layer etching process. This paper is based on the Chinese National Standard (CNS) A4 specification (210 X 297). (Mm) 丨 丨% | __ 丨 丨 _ | ^^ Packing, 丨 _ 丨 丨 丨 —— 丨 Order · --- (Please read the notes on the back before filling this page) 520549 A7 V. Description of the invention () Examples to introduce the background of the present invention. On the integrated circuit chip, please do Φ (please read the precautions on the back before filling out this page). The various components are connected by conductive interconnects. Designed circuit structure. Generally speaking, the chip will use several layers of conductors, conductors, and structures, including horizontal and vertical connections to form a circuit, and each layer of conductor; check & connection layer They are separated by a dielectric layer. The so-called one-layer connection structure or pile contact structure can mainly include a layer of dielectric lightning layer, and a defined horizontal connection line and downward extension connection. The vertical connection, also known as the plug, Rong θ ^ or 疋 connection plug and contact plug. In the purpose of metallized wiring or contact formation technology, the "electrical layer" is usually formed first, and the opening is defined in order to provide the space required to fill the conductor material and form an electrical connection. ; Then the conductor material is filled in the opening, that is, the contact hole (contact h0le) 5t connection hole (via h〇ie), to form a vertical connection, and the horizontal connection can be obtained by Another layer of body, with a pattern of fixed H 杳 flower; #.. T In the process of embedded or dual embedded (duai damascene), the horizontal connection can also be filled in and formed in the dielectric layer that has defined the lateral connection channels. At the time of entry, you can make a & taxi, p + Tian 丨 』renren into a horizontal and vertical connection. Referring to the first figure, the semiconductor substrate 10 may have a defined completed element structure, such as the transistor gate structure 1 shown in the figure,

丞 丞 1 Q Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and has a dielectric layer 14 covering it and other component structures to form an insulating layer that isolates the subsequent conductor layer from the underlying components and substrate. The intermediate layer 14 may include an anti-reflection layer 16 to improve the accuracy of the pattern 2 and 2 during the photolithography process, and a photoresist layer 18 is formed on the anti-reflection layer 16. The fine paper size is suitable for the Chinese country Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 520549 A7 B7 V. Description of the invention () The application of the filmmaking process can make the pattern to be etched, such as the contact required Areas of holes, etc., are defined on them. Referring to the second figure, the photoresist layer 18 is used as a mask, and the contact hole 20 is defined within the dielectric layer 14 by etching through the anti-reflection layer 16 and etching the dielectric layer 14, but in the conventional In the manufacturing process, due to the difficulty in controlling the etching process and the control of the etching selectivity, the material of the photoresist layer 18 defining the pattern is often lost during etching, resulting in a change in the defined pattern, which in turn causes the lower dielectric layer 14 The problem of edge loss and pattern deformation (st riat ion), such as the area marked 22 in the second figure, causes the problem that the pattern definition is deformed, the opening of the contact hole is enlarged, and the accuracy of the defined area is reduced. The zigzag shape of the side wall at the opening of the dielectric layer affects the effect of the filling of the conductive material in subsequent processes, which results in the effect of the electrical connection between the components and the long-term stability of the product. For the decline. However, in the traditional dielectric layer etching process, there is no effective solution to the above problems. Currently, the more commonly used process methods are mostly in the early stage of dielectric layer etching, and the etching selectivity is low. However, the process with a higher etching rate; and at the end of the dielectric layer etching, a process with a better etching selectivity is switched to provide an etching selectivity relative to other materials under the dielectric layer 14 to avoid material loss. However, the traditional single-step etching or the improved method of the two-stage etching described above cannot solve the problems of edge loss and pattern deformation of the openings of the dielectric layer 14; and in the above, the etching selectivity is poor. For the process with better etching selectivity, it is easy to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) due to the lower etching rate and excessive polymer accumulation in the later process.丨 --- ^ ------- install -------- order --------- (Please read the precautions on the back before filling out this page) 520549 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the consumer cooperative A7 B7 V. Description of the invention () product, as shown in the second figure, the tilt angle of the opening 20 increases, and the size of the opening in contact with the source drain region of the substrate 10 below decreases, The top view of the partial area on the wafer is as shown in the third figure. The opening 24 has distortion in the definition of shape and pattern due to poor etching selectivity and controllability, which causes the current semiconductor process to control the etching of the dielectric layer. One in terms of performance and process yield Big challenge. Object and Summary of the Invention The object of the present invention is to provide a method for etching a dielectric layer. Another object of the present invention is to provide a method for etching a dielectric layer, which can reduce the problem of photoresist layer loss by using a two-step etching method and control of the etching selectivity. Another object of the present invention is to provide a method for engraving a dielectric layer, so as to eliminate the problems of edge loss and pattern distortion of the etching opening of the dielectric layer in the conventional dielectric layer etching process. The method for etching a dielectric layer in the present invention may mainly include the following steps: First, a semiconductor substrate is provided. The substrate has a dielectric layer and a mask layer having a defined pattern on the dielectric layer. Then, the mask layer is provided. In order to etch the mask, a first etching step is performed on the dielectric layer; then, using the mask layer as an etching mask, a second etching step is performed on the dielectric layer, and the first etching step is relative to the mask layer when the dielectric layer is etched The etching selectivity is higher than that of the second etching step. In addition, in the preferred embodiment, it may be included in carrying out the above-mentioned first paper size to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) • · ϋ nn ϋ βϋ ϋ · ϋ ti ΜΜ ·· II aw I aw I (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 520549 A7 B7 V. Description of the invention () Remove the anti-reflection before touching the step In the step of Bottom Anti-reflection Coating, the anti-reflection layer is located between the mask layer and the dielectric layer, which is an organic compound with properties close to the photoresist layer. In a preferred example of the present invention, the above-mentioned first etching step is an etching step rich in a polymer substance, and the above-mentioned second etching step is an etching step which is less likely to generate a polymer substance. A photoresist layer can be applied to the above mask layer. Brief description of the diagram: The first diagram shows a schematic cross-sectional view of a photoresist layer with a dielectric layer and a defined pattern on a substrate in a conventional process. The first figure shows a schematic cross-sectional view of the problem of the loss of the opening edge and the deformation of the pattern after the dielectric layer is etched in the traditional process. The second figure shows the distortion of the opening shape and pattern definition of the local area on the wafer in the traditional process. Top view schematic. The fourth figure shows a schematic cross-sectional view of a dielectric layer and a defined mask layer on a substrate in the present invention. The fifth figure shows a schematic cross-sectional view of the base material after the first #etching step in the present invention. The sixth figure shows the cross-sectional diagram of the base material with the dielectric layer opening etched after the second etching step in the present invention. The seventh figure shows a partial cross-sectional schematic diagram of an inductively coupled high-density plasma reactor used in the preferred example of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) »^ 1 ϋ n ϋ 0 ln 1 nn an · ϋ J, I ϋ nn 3 i (Please read the notes on the back before filling out this page) 520549 A7 B7 V. Description of the invention () Detailed description of the invention: (Please read the notes on the back first Please fill in this page again.) The present invention provides a method for etching a dielectric layer. By controlling the etching process, adjusting the etching selectivity, and coordinating the reaction conditions, the two-stage etching can be performed to reduce the etching medium. In the electrical layer, the problem of loss of the mask layer or photoresist layer used to define the pattern, thereby avoiding the problem of loss of the edge of the opening of the dielectric layer and the deformation of the pattern in the traditional process, and can greatly improve the control of the etching process It can provide good dielectric layer etch shapes, such as good contact hole etch shapes, etc., to improve the yield of semiconductor processes and the operating efficiency and reliability of products. As mentioned in the background of the invention, in the fabrication of semiconductor devices, the dielectric material is a very important material in application. It can be used as the gate insulating layer, the insulating layer between the connection layers, and the dielectric between the upper and lower plates of the capacitor. Different applications such as layers; among different applications, the process of dielectric layer etching will be required to define the required holes or patterns. Without limiting the spirit and scope of the present invention, the following uses the contact hole engraving process of the dielectric layer last name process as an example to introduce the preferred embodiment of the present invention in application. Details. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in the fourth figure, a semiconductor substrate 30 is provided first, which may have a defined element structure, such as the transistor gate structure 32 shown in the figure; substrate 30 and has a dielectric layer 34 covering it and other element structures to form a subsequent conductor layer between the underlying element and the substrate 30. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297). (Mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 520549 A7 __ B7 V. Description of the invention () Insulating insulation layer, dielectric layer 3 4-Generally, silicon oxide-based materials can be used, such as silicon dioxide Or a borophospho silicate glass (BPS G) layer that can provide better surface flatness; a mask layer 38 to be applied during etching is formed over the dielectric layer 34, and In the application of the photolithography process, the pattern of the area to be etched, such as the area to form a contact hole, etc., can be defined on it. In the current application of the semiconductor process, the mask layer 38 uses a photoresist layer. In order to facilitate the introduction of the present invention, the fourth to sixth figures show two different cross-sections of contact holes that need to be formed above the etched gate structure 32 and above the source and electrode regions of the substrate 30 at the same time. For details of the manufacturing process, the mask layer 38 in the fourth figure is the definition of the contact hole pattern above the gate and source drain regions. In a preferred embodiment, the dielectric layer 34 may include an anti-reflection layer 36, or a bottom anti-reflection coating (B ARC), sandwiched between the dielectric layer 34 and the cover layer. 38 to improve the accuracy of the pattern definition on the photoresist layer during the lithography process; in general, the antireflection layer 36 can use organic compounds with photoresistive properties. For the application in this example, its thickness is about It is between 600 and 900 Angstroms. If the above-mentioned preferred embodiment using the anti-reflection layer 36 is used, after the pattern definition of the mask layer 38 is completed, the anti-reflection layer (B ARC opening) may be removed before the dielectric layer 34 is etched. And taking the anti-reflection layer 36 similar to the photoresist layer as an example, the step of removing the anti-reflection layer can be plasma etching, using fluorocarbon gas' oxygen, and carrier gas as the main paper Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) I, 1 II M ------ · 1111111 ^ «— — — — — — I— (Please read the notes on the back before filling (This page) 520549 A7-____B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention () Gas to be involved in the reaction. In a preferred embodiment, in the plasma etching for removing the anti-reflection layer, a flow rate between about 15 to 30 sccm (standardcubic centimeter per minute) can be used. The flow rate is about 80 to Argon gas between 120 sccm is used as the carrier gas and oxygen gas with a flow rate of about 3 to 8 sccm. In the best embodiment, the optimal value of the c2F6 flow rate is about 20 sccm and the optimal value of the argon flow rate is about 100 scccrn, and the optimum value of the oxygen flow rate is about 5 sccm. In terms of the operating conditions of the reaction chamber, the total energy of the plasma source used is between about 600 and 1200 watts, preferably about 900 watts, and the bias energy is between 400 and 600 watts. The preferred value is about 500 watts, the pressure in the reaction chamber is about 5 to 15 millitorr (mTorr), and the preferred value is about 10 millitorr. In a preferred embodiment, in the current stage of semiconductor manufacturing, the above-mentioned etching step to remove the anti-reflection layer and the subsequent dielectric layer etching step can be performed using inductively coupled high-density plasma (inductively coupled high-density plasma) etching reaction machine to perform, this type of machine can provide good selectivity and process flexibility at the same time, and in other processing steps after etching. In addition to the above-mentioned machines, there are also other high-density machines, including machines such as remote plasma source (RPS) and electron-cyclotron resonance (ECR); and The definition of high-density plasma can be a condition where the ion density of the plasma-filled space reaches at least 10E1 lcnT3 or more. An example of the above-mentioned inductive coupling, high-density plasma etching reaction machine (please read the precautions on the back before filling this page). -------- Order ---- # · This paper size applies to China National Standard (CNS) A4 Specification (210 X 297 mm) 520549 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7___ __ --- 5. Description of the invention () May be applied by the applicant of this invention, American Applied Materials Company ( Applied

Materials, Inc. of Santa Clara, California, USA) manufactured an IPS (Inductively-Coup led Parallel-Plate Semiconducting Chamber Dielectric Etch System) reaction machine. The approximate reaction chamber structure and matching equipment are as shown in Figure 7 As shown in a partial cross-sectional schematic diagram, the wafer to be processed 80 is carried by a cathode stage 82, and the cathode stage 82 is supplied with radio frequency (RF) energy provided by a first radio frequency energy source; a silicon ring 8 surrounding the stage 82 6 The heating control can be performed by the annularly arranged heating lamps 88, while the grounded silicon wall 90 surrounds the plasma processing area, and the silicon top cover 92 covers the plasma processing area. The silicon ring 8 with heating control 6 and part of the silicon top cover 9 2 can be used to remove the fluorine generated by fluorocarbon plasma or fluorinated plasma; the process gas is supplied from one or more lower gas supply ends 94 through the mass flow controller 96 area Block to supply. In addition, the upper gas supply end can form a small gas shower head in the center of the Shixi top cover 92, and a vacuum pump system (not shown) is connected to the pump channel 98 below the reaction chamber to maintain The system controller 100 of the reaction chamber at the set pressure controls the operation of the etching reaction machine and the cooperating equipment. In the previous architecture, the 'Shixi top cover 92' will be grounded, but the resistance and thickness of the semiconductor will be adjusted and selected so that the approximately axial RF magnetic energy can pass through the 'Shixi top cover 92' through the 'axial RF magnetic The system is generated by the internal induction unit 106 and the external induction unit 108 driven by the radio frequency energy supply no and U2, respectively. In addition, 'the above design can also be replaced by a single RF energy supply with optional power splitter; and •. Ββ§ emt n —a— _ · 1 em— amm§ J >, · I · 1 I n fl— an n I (Please read the notes on the back before filling this page) 10

520549 A7 B7 V. Description of the invention (Other coil structures can be used, such as a transformer coupled plasma (TCP) reactor with a flat, spiral induction coil on the top i 92. System controller 1 0 0 Controllable mass flow controller 9 6, heating lamp 8 8, 9 4. Cold water supply to cooling channel 96. Throttle valve for vacuum pump, and energy supply source 8 4, 1 1 0, 1 1 2 ' The function can control the chemical composition of the last name to meet the conditions in the following embodiments. The parameters of the reaction can be stored in the controller 100 using conventional magnetic, optical, or semiconductor memory devices, and The controller 100 reads it out from the storage medium inserted therein, and generally the equipment supplier provides the required parameters with magnetic disks or CDROMs and other optical media to be read out by the controller 100. Inductive plasma reactor The main advantage of the stage is that it can deliver different energy to the induction coils 106, 108, and the capacitive stage 82; when the capacitance performance controls the plasma surface area at the wafer 80, and therefore determines the DC bias in the Z area of the table Pressure The energy can generate a plasma source area that is far away from the wafer 80. The plasma source energy can be increased to increase the etch rate and control the type and number of excitation 2 ^ subclusters. The bias energy can be changed to make the net *加速 Accelerate with high energy or low energy in the surface area, and then hit the wafer 80 with the preset energy. Li Ri (Please read the precautions on the back before filling this page) Installation ----- I- -Order ·! 1 The printing machine of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs should be similar to the one described in the anti-etching statement. Compared with other methods of electricity I, this law can also be issued. This method is based on the system. The effect of step-by-step resistance to remove the finished machine should be used for the purpose of anti-etching.

This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) —IJ 520549 A7 V. Description of the invention (After printing by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the cover layer 3 8 is used as the cover layer. The mask is etched, and the first etching step is performed on the dielectric layer 34. In order to maintain good etching selectivity, the accuracy and integrity of the mask layer 38, such as the photoresist layer in this example, and the defined pattern, are maintained. In the present invention, a process condition with a higher etching selectivity is applied in the first etching step, that is, the first etching step provides a first-name selectivity relative to the mask layer 38 when the dielectric layer 34 is etched; In the preferred embodiment, the first etching step is an etching step that is rich in polymer materials. In this example, the first first step is the step of engraving the dielectric layer and the last name of the mask layer. The rate ratio can be controlled between about 6-20. In a preferred embodiment, the combination of a fluorocarbon gas, a fluorocarbon gas, an oxygen-containing gas, and a carrier gas can be used as the first-name step. Reactive gas. In the preferred embodiment, the anti-rat gas is mainly C4F8 '.之 The door is about 12 to 20 sccm ^ between the heart, the best value is about 16 sccm; the hydrocarbon gas can be mainly ch2F2, the recooling temperature is from a /, the amount is about 17 to 2 ^ 7 SCCm, the best value Approximately 22 sccm; oxygen-containing gas can be mainly used carbon monoxide 'flow rate of about 25 to 65 sccm, the best value is about 4 5 seem; in this example, argon can be used as the carrier gas, and its flow rate is about π to 35 0 sccm. The best value is about 2 7 0 sccm. The first etching step also uses a plasma reaction chamber to cry, in which the total energy of the plasma source is about 650 watts to 1 150 watts, with ^ The best value is about 920 watts; the bias energy is about 1000 watts to 1800 watts, and the best value is about 1400 watts; the pressure in the reaction chamber is about 10 to 20 gram > The best value is about 15 mTorr. And using the above-mentioned induction type, high-density X-ray plasma etching reactor 12 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ) (Please read the notes on the back before filling this page)-I-- Order ---- # 520549 A7 B7 V. Description of the invention () Taiwan, which is the US applied materials company (Applied Materials, Inc. Of (please read the Notes on the back to fill out this page)

1 卩 3 (111 (111 (: 1 ^ 61) ^-manufactured by Santa Clara, California, U.S.A.)

Coupled Parallel-Plate Semiconducting Chamber Dielectric Etch System ,;) In the best example of a reaction machine, the energy of the inner ring plasma source during the first etching step is about 100 watts to ι6. Between watts, a more preferred example may be 130 watts; while the energy of an outer ring (focusing) source is between about 600 watts and 1,000 watts, and a more preferred example may be 780 watts. As mentioned in the introduction to the machine in the ninth figure, the inner plasma source energy is generated by the inner induction unit 106 driven by the RF energy supply 110, and the outer plasma source energy is generated by the RF energy source. The external induction unit 108 driven by the supplier 丨 丨 2 is generated. The depth ratio of the entire dielectric layer 38 occupied by the first engraving step can be adjusted according to different process requirements, for example, the first etching step can be etched about 1/2 to 3/4 of the thickness of the dielectric layer; and For the application of etching the opening of the gate and source drain contact holes in this example simultaneously, the first etching step can be stopped until the gate structure 32 is stopped, as shown in the fifth figure, and the source drain The opening 42 in the electrode region is etched to a depth of about 2/3; in terms of thickness, the thickness of the dielectric layer 34 in this example is between about 7000 and 10,000 Angstroms. The depth is between 5,000 and 70,000 Angstroms. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Figure 5. With the high #etch selectivity provided by the first etching step rich in polymer substances, a good dielectric layer 34 etching effect can be formed. And the good effect of maintaining the shape of the cover layer 38; as shown in the photoresist layer, there is only a small loss in thickness, and the shape change of the opening part also applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 520549 A7 B7 5. The description of the invention () is slight, so the accuracy of the definition of the contact hole pattern of the dielectric layer 3 4 can be maintained. Then, using the same mask layer 38 as the etching mask, the dielectric layer 34 is subjected to a second etching step. Compared with the first etching step, the second etching step uses a process condition with a lower etching selectivity to provide sufficient The etch rate and depth of the etch will produce more vertical sidewalls, and prevent the problem of the contact hole opening width being too small or the etch stop. Therefore, the etching selectivity of the first etching step with respect to the mask layer is higher than that of the second etching step. In a preferred embodiment, the second etching step is an etching step that is less likely to generate a polymer substance. In this example, the etch rate ratio of the dielectric layer to the etching mask layer in the second etching step can be controlled to be between about 2-3.5. In a preferred embodiment, the second etching step may use a combination of a fluorocarbon gas and a carrier gas as a reaction gas. In the preferred example, the fluorocarbon gas can be mainly C4F8 and C2F6, wherein the flow rate of C4F8 is between 12 and 20 sccm, the best value is about 16 sccm, and the flow rate of C2F6 is between 4 and 8 sccm, the best value is about 6 sccm; The carrier gas can also be argon. Its flow rate is about 75 to 120 sccm, and the optimal value is about 9 5 seem. The second etching step is also performed using a plasma reaction chamber, in which the total energy of the plasma source is about 1200 watts. To 1 900 watts, the optimal value is about 1600 watts; the bias energy is about 1000 to 1 800 watts, the optimal value is about 1400 watts; the reaction chamber pressure is about 3 to 7 millitorr, The optimal value is about 5 mTorr. 、 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) • 0 tmt n I n memme n sal J, Zhaoam IIIII mm I (Please read the precautions on the back before filling this page) 520549 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Using the above-mentioned inductive coupling and high-density plasma etching reaction tip σ is also the IPS reactor manufactured by American Applied Materials Σ, the energy of the inner plasma source during the first etching step is about 250 watts to 500 watts, and the best example is 3500 watts. ; And the amount of 爿 b of the external J | electric water source is about 10,000 watts to 5,000 watts, and a better example may be 1250 watts. See the "Figure" through the second step of engraving in the present invention, can provide a good etch rate and the verticality of the sidewall, so that the contact hole 42 on the substrate 30 source drain region culvert to the base smoothly. 3Q surface. Although the selection rate of the second engraving step is higher than that of the plate, Bo Ping is relatively low. After the first etching step, the photoresist layer as the mask layer 38 still has sufficient thickness and good Shape, so under the second money engraving step, although there will be more thickness loss and the expansion of the upper opening of the aperture, but it can still maintain a good dielectric layer ^ pattern transfer effect, And it can effectively eliminate the serious damage problem in the traditional process, and through the control of the condition of the box in the present invention + β β 1%, it can still provide the dielectric layer 34 when etched relative to the gate structure 32 below. And the engraving selectivity of the material of the substrate 30, providing a contact hole buckle with a complete shape as shown in the figure, and the present invention has been described above with a preferred embodiment, and is only used to help understand the implementation of the present invention. It is used to define the spirit of the present invention. After realizing the spirit of the present invention, the artist can make minor modifications and equivalent changes without departing from the spirit of the present invention. The scope of patent protection depends on the scope of the attached patent application and its equivalent fields. . 15 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)

Equipment -------- Order --- I

Claims (1)

520549 A8 B8 C8 D8 6. Scope of Patent Application 1. A method for etching a dielectric layer includes at least the following steps: A semiconductor substrate is provided, the substrate has a dielectric layer, and a mask layer with a defined pattern. On the dielectric layer; using the mask layer as an etching mask, performing a first etching step on the dielectric layer; and using the mask layer as a surname to engrav the mask, performing a second money engraving on the dielectric layer Step, the first etching step has a higher etching selectivity with respect to the mask layer than the second etching step when the dielectric layer is etched. 2. If the method for etching a dielectric layer according to item 1 of the patent application scope, further includes a step of removing an anti-reflection layer before the first etching step, the anti-reflection layer is located between the mask layer and the dielectric layer. Between layers. 3. The method for etching a dielectric layer according to item 2 of the patent application, wherein the anti-reflection layer includes at least an organic compound having photoresist properties. Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 4. For the method of etching the dielectric layer in the third item of the patent application, the above steps of removing the anti-reflective layer The reaction gas includes at least a fluorocarbon gas, oxygen, and a carrier gas. 5. The method for etching a dielectric layer as described in the first item of the patent application, wherein the above-mentioned first etching step is an etching step rich in a polymer substance, and the above-mentioned second etching step is a method that is less likely to generate a polymer substance. Etching step. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 520549 A8 B8 C8 D8 6. Application for patent scope 6. For the method of etching the dielectric layer in the first scope of the patent application, where the first etching described above The etching rate ratio between the step of etching the dielectric layer and the etching of the mask layer is between about 3-5. 7. The method for etching a dielectric layer according to item 1 of the scope of the patent application, wherein the second etching step described above etches the dielectric layer and etches the etching layer at a rate between about 2 and 3.5. 8. The method for etching a dielectric layer according to item 1 of the application, wherein the first etching step includes at least the use of a fluorocarbon gas, a fluorocarbon gas, an oxygen-containing gas, and a carrier gas. 9. The method for etching a dielectric layer according to item 8 of the application, wherein the fluorocarbon gas contains at least C4F8. 10. The method for etching a dielectric layer according to item 8 of the patent application, wherein the flow rate of the fluorocarbon gas is about 12 to 20 seem. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 11. For the method of etching the dielectric layer in the scope of patent application item 8, the above-mentioned hydrocarbon gas contains at least CH2F2 . 12. The method for etching a dielectric layer according to item 8 of the application, wherein the flow rate of the fluorocarbon gas is about '17 to 27 sccm. Wood paper scale is applicable to China National Standards (CNS) A4 (210X297 mm) 520549 A8 B8 C8 D8 6. Scope of patent application Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 3. If the etch of the scope of patent application item 8 A method of a dielectric layer, wherein the above-mentioned oxygen-containing gas contains at least an oxide barrier. 1 4. The method for etching a dielectric layer according to item 8 of the scope of patent application, wherein the flow rate of the oxygen-containing gas is about 50 to 90 s c c m. 15. The method for etching a dielectric layer according to item 8 of the scope of patent application, wherein the above-mentioned carrier gas includes at least argon. τ 16. The method for etching a dielectric layer according to item 15 of the patent application, wherein the above-mentioned 1 gas flow rate is about 200 to 350 sccm. 17. The method for etching a dielectric layer according to item 8 of the patent application, wherein the first etching step is performed by a plasma reaction chamber, and the total energy of the plasma source is about 650 watts to 1 15 0 Watt. 18. The method for etching a dielectric layer according to item 8 of the patent application, wherein the first etching step is performed by a plasma reaction chamber, and the bias energy is between about 1000 watts and 1800 watts. 19. The method for etching a dielectric layer according to item 8 of the scope of patent application, wherein the pressure of the reaction chamber in the first etching step is about 10 to 20 mTorr. (Please read the precautions on the back before filling out this page) 18 This paper size applies to Chinese National Standards (CNS) A4 specifications (210 X 297 mm) 520549 A8 B8 C8 D8 々, patent application scope (please read the notes on the back first (Please fill in this page again for details) 2 0. The method for etching a dielectric layer according to item 1 of the scope of patent application, wherein the above-mentioned second etching step includes at least the use of a fluorocarbon gas and a carrier gas. 2 1. The method for etching a dielectric layer according to item 20 of the scope of patent application, wherein the above fluorocarbon gas includes at least C4F8 and C2F6. 22. The method for etching a dielectric layer according to item 21 of the patent application, wherein the C 4 F 8 flow rate described above is between about 12 and 20 s c c m. 23. The method for etching a dielectric layer according to the scope of claim 21, wherein the C 2 F 6 flow rate is about 4 to 8 s c c m. 24. The method for etching a dielectric layer according to claim 20, wherein the carrier gas mentioned above contains at least argon. 25. The method for engraving a dielectric layer according to item 24 of the patent application scope, wherein the above-mentioned argon flow rate is between about 75 and 120 sccm. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 26. For example, the method for etching a dielectric layer in the scope of patent application No. 20, wherein the above-mentioned second etching step is performed by a plasma reaction chamber, wherein the total energy of the plasma source is about Between 1 100 watts and 1 900 watts. 27. For the method of etching dielectric layer in the scope of application for patent No. 20, in which the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 520549 A8 B8 C8 D8 々 Patent scope (please read the back first (Please note this page and fill in this page again.) The above-mentioned second etching step is performed by a plasma reaction chamber, wherein the bias energy is about 1000 watts to 1800 watts. 2 8. The method for etching a dielectric layer according to item 20 of the application, wherein the pressure of the reaction chamber in the second etching step is about 3 to 7 mTorr. 29. The method for etching a dielectric layer according to item 1 of the patent application, wherein the mask layer includes at least a photoresist layer. 30. The method of etching a dielectric layer according to item 1 of the scope of patent application is used to define a contact hole in the dielectric layer. 31. A method for etching a dielectric layer, including at least the following steps: providing a semiconductor substrate having a dielectric layer on the substrate and a photoresist layer having a defined pattern on the dielectric layer; The photoresist layer is an etching mask, and a first etching step is performed on the dielectric layer. The first etching step includes at least a fluorocarbon gas, a fluorocarbon gas, an oxygen-containing gas, and a carrier gas; and the intellectual property of the Ministry of Economic Affairs The bureau ’s consumer cooperative prints the photoresist layer as an etching mask and performs a second etching step on the dielectric layer. The second etching step includes at least the use of a fluorocarbon gas and a carrier gas. The first etching step etches the substrate. The etching selectivity of the photoresist layer relative to the photoresist layer is higher than that of the second etching step, and the first etching step is an etching step rich in polymer materials, and the second etching step is less likely to generate high Molecular substances This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 520549 A8 B8 C8 D8 々, the etching steps in the scope of patent application. (Please read the precautions on the back before filling out this page) 3 2. If the method for etching the dielectric layer in the 31st scope of the patent application, further includes a step of removing the anti-reflective layer before the first etching step, The anti-reflection layer is located between the photoresist layer and the dielectric layer. 33. The method for etching a dielectric layer according to item 32 of the application, wherein the anti-reflection layer includes at least an organic compound having photoresist properties. 34. The method for etching a dielectric layer according to item 33 of the application, wherein in the above step of removing the anti-reflection layer, the reaction gas includes at least a fluorocarbon gas, oxygen, and a carrier gas. 35. The method for etching a dielectric layer according to item 31 of the application, wherein the first etching step described above etches the dielectric layer and etches the photoresist layer at a rate between about 6-20. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 3 6. The method for etching a dielectric layer as described in the 31st scope of the patent application, wherein the second etching step described above etches the dielectric layer and etches the photoresist layer at an etching rate About 1.5-4. 3 7. The method of etching a dielectric layer according to item 31 of the scope of patent application, wherein the above fluorocarbon gas contains at least C4F8. This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 520549 A8 B8 C8 D8 々 、 Scope of patent application (please read the precautions on the back before filling this page) 3 8. If the scope of patent application is 3 7 In the method of etching a dielectric layer, the flow rate of the fluorocarbon gas is about 12 to 20 seem. 3 9. The method for etching a dielectric layer according to item 31 of the scope of patent application, wherein the above-mentioned hydrocarbon gas contains at least CH2F2. 40. The method for etching a dielectric layer according to item 39 of the scope of patent application, wherein the flow rate of the fluorocarbon gas is about 17 to 27 sccm. 41. The method for etching a dielectric layer according to item 31 of the scope of patent application, wherein said oxygen-containing gas contains at least carbon monoxide. 42. The method for etching a dielectric layer according to item 41 of the application, wherein the flow rate of the oxygen-containing gas is about 50 to 90 seem. 43. The method for etching a dielectric layer according to item 31 of the scope of patent application, wherein the above-mentioned carrier gas includes at least argon. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 44. For example, the method for etching a dielectric layer according to item 43 of the patent application, wherein the above-mentioned argon flow is between 200 and 350 sccm. 45. The method for etching a dielectric layer according to item 31 of the patent application, wherein the first etching step is performed by a plasma reaction chamber, and the total energy of the plasma source is about 650 watts to 1 150 Watt. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 520549 A8 B8 C8 D8 6. Application for patent scope Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 46. If applying for the etch dielectric of item 31 of the patent scope Layer method, wherein the above-mentioned first etching step is performed in a plasma reaction chamber%, wherein the bias energy is between about 1000 watts and 1800 watts. 47. The method for etching a dielectric layer according to item 31 of the application, wherein the pressure of the reaction chamber in the first etching step is about 10 to 20 mTorr. 48. The method for etching a dielectric layer according to item 31 of the patent application, wherein the carbon gas includes at least C4F8 and C2F6. 49. The method for etching a dielectric layer according to item 48 of the patent application, wherein the C4F8 flow rate is about 12 to 20 seem. 50. The method for etching a dielectric layer according to item 48 of the application, wherein the C 2 F 6 flow rate described above is between about 4 and 8 s c c m. 51. The method for etching a dielectric layer according to the scope of application for item 31, wherein the above carrier gas includes at least a cap gas. 52. The method for etching a dielectric layer according to item 51 of the application, wherein the above-mentioned argon flow rate is between about 75 and 120 sccm. (Please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 520549 A8 B8 C8 D8 VII. Patent application scope 5 3. If you apply for patent scope item 31 The method for etching a dielectric layer, wherein the above-mentioned second etching step is performed by a plasma reaction chamber, wherein the total energy of the plasma source is about 1 100 watts to 1900 watts. 54. The method for etching a dielectric layer according to item 31 of the patent application, wherein the second etching step is performed by a plasma reaction chamber, and the bias energy is between about 1000 watts and 1800 watts. 5 5. The method for etching a dielectric layer according to item 31 of the patent application scope, wherein the pressure of the reaction chamber in the second etching step is about 3 to 7 mTorr. 5 6. The method of etching a dielectric layer according to item 31 of the scope of patent application is used to define a contact hole in the dielectric layer. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)