經濟部智慧財產局員工消費合作社印製 519731 A7 _B7_ 五、發明說明（1 ) 發明領域 本發明係關於一種半導體製程，特別是關於一種可將 南頻互補式金屬氧化物半導體與南效能雙載子電晶體製作 在同一晶片上的雙載子互補式金屬氧化物半導體之製造方 法。 發明背景 雙載子互補式金屬氧化物半導體（BiCMOS)元件是將雙載 子電晶體（Bipolar Transistor)與互補式金屬氧化物半導體 (CMOS)元件製作，同一晶片上而成。由於兩種元件的製程不 同，且元件特性與製程有很大的關係，故欲將兩者製作在同 一晶片上且同時具備非常優良的元件特性（例如截止頻率大於 25GHz)或低雜訊（low noise)特性是相當困難的工作。 目前高頻的CMOS元件是業界亟欲發展的製程技術，因為 隨著線寬不斷縮小，使得CMOS的截止頻率可以不斷的提升， 同時如何減少寄生效應（parasitic effect)引發的閉鎖現象（latch-up) 與 減少源 極與沒 極的接 合深度 （junction depth) 更是 未來發 展的方向，因為這些都可以有效提升CMOS元件高頻的特性。 若能順利研發成功，且將之應用在BiCMOS之製程内，對於該 元件的特性將有極大的助益。 圖1(a)至圖1(e)為習知之雙載子互補式金屬氧化物半導 體之製造方法示意圖。首先在底材U假設為一 P型底材）内之 預定區域生成作為元件間隔離用之隔絕層2 ;接著一高濃度摻 雜之η +區4亦在底材1内被形成’該區作用係在於將集極區 (collector region)導出；而後生成一Ν井（圖未示出）以及一 Ρ井 7。一絕緣層6緊接著被沈積在底材1之全表面上；之後再沈積 -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---ί---I-------裝--- (請先閱讀背面之注意事寫本頁) . · 丨線- 519731 A7Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519731 A7 _B7_ V. Description of the Invention (1) Field of the Invention The present invention relates to a semiconductor process, and in particular, to a method capable of combining a south-frequency complementary metal oxide semiconductor with a south-efficiency double carrier. A method for manufacturing a double-carrier complementary metal oxide semiconductor in which transistors are fabricated on the same wafer. BACKGROUND OF THE INVENTION BiCMOS complementary metal-oxide-semiconductor (BiCMOS) devices are made from a bipolar transistor and a complementary metal-oxide-semiconductor (CMOS) device on the same wafer. Since the two components have different manufacturing processes, and the characteristics of the components have a great relationship with the manufacturing process, it is desirable to fabricate the two components on the same chip and have very good component characteristics (for example, cut-off frequency greater than 25GHz) or low noise noise) characteristic is quite difficult work. At present, high-frequency CMOS devices are a process technology that the industry is eager to develop, because as the line width continues to shrink, the cut-off frequency of CMOS can be continuously improved, and how to reduce latch-up caused by parasitic effects. ) And reducing the junction depth of the source and non-electrode (junction depth) is the future development direction, because these can effectively improve the high-frequency characteristics of CMOS devices. If it can be successfully developed and applied in the BiCMOS process, it will greatly help the characteristics of the device. Fig. 1 (a) to Fig. 1 (e) are schematic diagrams of a conventional method for manufacturing a double-carrier complementary metal oxide semiconductor. Firstly, an insulating layer 2 is generated as a separation between elements in a predetermined area in the substrate U (assuming a P-type substrate); then a high-concentration doped η + region 4 is also formed in the substrate 1 'the region The function is to export the collector region; then, an N well (not shown) and a P well 7 are generated. An insulating layer 6 is then deposited on the entire surface of the substrate 1; then it is deposited -4-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --- ί --- I ------- Install --- (Please read the notes on the back to write this page). 丨 Line-519731 A7
一弟一複晶層8於絕緣層6之上，如圖i (a)所示 接下來如圖1W所示’利用光阻作為罩膜（圖未于出） 預定區域内製作-NPN型雙載子電晶體之集極區3以及基極區 (base region) 5 。 口口 接考，利用-微影製程在基極5上方之預定區域内製作— 開口’該開口穿透第-複晶層8以及絕緣層6，作用在於暴霖 出-邵份基極；而後沈積一第二複晶層9在第—複晶層8之全 表面上與前一步驟所製作的開口内，並且摻雜N型不純物至第 一複晶層9内。 其後，將MOS閘極（gate)和雙載子電晶體射極（emitter^々 圖形經過微影及蝕刻製程，轉移至第一複晶層8與N型的第二 複晶層9上，結果如圖1(c)所示，如此即完成了閘極與射極的 製作。 接著生成間隙壁（spacer) 10與絕緣層1 1，如圖1(d)所示； 而後PM0S内構成源極（source)與汲極（dram)之p +區域與卜區 域（圖未示出）以及NM0S内構成源極與汲極之區域12與卜 區域13相繼被生成。此外，一作為基極嫁接（graft以^丨之时 £域14與作為集極導边區之n +區域15也被生成。 然後，在適當的操作條件下進行一熱處理製程以生成射 極（emitter)32，如圖1(e)所示；自行對準矽化物製程（SaHcide) 接著被進行以在整個底材表面沈積一金屬矽化物層（Slhcide film)33 ; —内層絕緣層1 6則在自行對準矽化物製程後被沈積 至元件上。 再來在内層絕緣層1 6之預定區域製作接觸窗開口，該等 接觸窗開口係穿透内層絕緣層；之後用具傳導性之物質填滿 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---^-------.-------- (請先閱讀背面之注意事寫本頁) 訂·· --線_ 經濟部智慧財產局員工消費合作社印製 519731 經濟部智慧財產局員工消費合作社印製 A7 _B7_五、發明說明（3 ) 該等接觸W，故一源極電極2 6、一沒極電極2 7、一基極電極 2 8、一射極電極2 9以及一集極電極3 0就都完成了。至此，整 個BiCMOS元件即，告製作完成。 經由上述製程所製出之BiCMOS元件，在進行Salicide製程 時，無論是使用鈦或鈷作為金屬矽化物之主要成分，由於皆 會消耗大量的矽原子（見表一），故會有接合過深的問題；且因 接合過深，就會順帶導致摻質的擴散，影響電場分佈，並因 此而影響到整個元件的效能。 此外，一般習知的BiCMOS元件之基極寬度較寬也較深； 但若要使元件效能提升，淺接合的形成是很重要的，而此點 也必須靠製程技術的改善來達成。 發明之簡要說明 本發明之主要目的係提供一可同時製作高頻金屬氧化 物半導體與高效能之雙載子電晶體之雙載子互補式金屬氧 化物半導體之製造方法。 本發明之另一目的係在提供一可提升截止頻率且具備 低雜訊（noise)與減少寄生效應（Parasitic Effect)等特性之元 件的雙載子互補式金屬氧化物半導體之製造方法。 本發明之又一目的在於提供一雙載子互補式金屬氧化 物半導體之製造方法，其可一併應用異質介面雙載子電晶 體（Heterojunction Bipolar Transistor ; HBT)製程技術。 為達上述目的，本發明揭示一種雙載子互補式金屬氧 化物半導體之製造方法，其步，驟如下： 進行雙載子互補式金屬氧化物半導體之前段製程； -6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事 ^寫本頁) 裝 · •線. 經濟部智慧財產局員工消費合作社印製 519731 A7 _B7_ 五、發明說明（4 ) 選擇性沈積一第二磊晶層於基極、源極和汲極之上； 沈積一薄氧化層作為墊氧化層，進行射窗間隙壁的製作 及姓刻； 進行雙載子互補式金屬氧化物半導體之後段製程。 其中該前段製程包括： 在一具第一導電性之基材上製作雙埋層； 沈積一具第二導電性之第一磊晶層，製作一具第一導電 性之井區、一具第二導電性之井區、集極、隔絕層及閘氧 化層； 沈積一複晶層，製作閘極與基極，並進行互補式金屬氧 化物半導體之製程； 沈積氧化層與氮化矽層，定義射窗、集極與源極並進行 I虫刻。 而該後段製程則包括： 沈積射極複晶，製作射極； 進行自行對準矽化物製程及後段金屬化製程。 利用本發明之方法，在雙埋層製作完成、P井製作之 前預先沈積一 N型之磊晶層，可有效防止元件因寄生雙載 子效應所產生的閉鎖現象，故即使是高積集度的元件，其 元件特性仍不至於改變。此外，由於多了一層選擇性沈積 的磊晶層，故CMOS之閘極、汲極與源極皆被墊高。在進 行Salicide製程時，以鈦或鈷為主要成分之金·屬矽化物，原 本皆會消耗大量的碎原子導致接合（junction)過深；但在本 發明中由於磊晶層墊高的效應，將Μ〇S源極與汲極的接合 -7 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---^--------------- (請先閱讀背面之注意事寫本頁) .- -_線_ 519731 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 才疋升到矽晶片的表面，使該金屬矽化物層與M〇s的接合不 至於太深，確保了接觸金屬與元件間的淺接合（shail〇wA polycrystalline silicon layer 8 is on the insulating layer 6, as shown in Figure i (a), and then shown in Figure 1W. 'Using a photoresist as a cover film (not shown in the figure) A -NPN type double is fabricated in a predetermined area. The collector region 3 and the base region 5 of the carrier transistor. Take the test, make it in a predetermined area above the base 5 using the -lithography process-the opening 'the opening penetrates the -multi-crystalline layer 8 and the insulating layer 6, and the role is to storm out the-Shaofen base; then A second polycrystalline layer 9 is deposited on the entire surface of the first-multicrystalline layer 8 and in the opening made in the previous step, and an N-type impurity is doped into the first polycrystalline layer 9. Thereafter, the MOS gate and the bipolar transistor emitter (emitter ^ 々 pattern) are transferred to the first polycrystalline layer 8 and the N-type second polycrystalline layer 9 through a lithography and etching process. The result is shown in Fig. 1 (c), so the gate and emitter are completed. Next, a spacer 10 and an insulating layer 11 are generated, as shown in Fig. 1 (d); and then a source is formed in PM0S. The p + region and the b region (not shown) of the source and the drain and the region 12 and the b region 13 constituting the source and the drain in the NMOS are successively generated. In addition, one is used as a base graft (Graft ^ 丨 when the domain 14 and n + region 15 as the collector leading edge region are also generated. Then, a proper heat treatment process is performed to generate an emitter 32, as shown in Figure 1 (e); the self-aligned silicide process (SaHcide) is then performed to deposit a metal silicide layer (Slhcide film) 33 on the entire substrate surface;-the inner insulating layer 16 is in the self-aligned silicide process It is then deposited on the element. Then, contact window openings are made in a predetermined area of the inner insulating layer 16 and the contact windows are opened. Mouth penetrates the inner insulation layer; after filling the paper with conductive substances, the size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) --- ^ -------.--- ----- (Please read the note on the back first and write this page) Order ·· --line _ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519731 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ Description of the invention (3) These contacts W, so one source electrode 26, one electrode electrode 27, one base electrode 28, one emitter electrode 29, and one collector electrode 30 are all completed. At this point, the entire BiCMOS device has been completed. When the BiCMOS device manufactured through the above process is used in the Salicide process, whether titanium or cobalt is used as the main component of the metal silicide, a large amount of silicon atoms are consumed ( (See Table 1), there will be the problem of too deep junctions; and because of too deep junctions, incidentally, dopant diffusion will occur, which will affect the electric field distribution, and thus affect the performance of the entire device. In addition, the commonly known BiCMOS The base width of the device is wider and deeper; but if you want to make the device The improvement of efficiency and the formation of shallow junctions are very important, and this must also be achieved by the improvement of process technology. Brief description of the invention The main purpose of the present invention is to provide a high-frequency metal oxide semiconductor and high-performance A method for manufacturing a double-carrier complementary metal oxide semiconductor of a double-carrier transistor. Another object of the present invention is to provide an improved cut-off frequency, low noise, and reduced parasitic effect. A method for manufacturing a bicarrier complementary metal oxide semiconductor of a characteristic device. Yet another object of the present invention is to provide a method for manufacturing a dual-carrier complementary metal oxide semiconductor, which can be used in conjunction with a hetero-interface bipolar transistor (HBT) process technology. In order to achieve the above object, the present invention discloses a method for manufacturing a double-carrier complementary metal oxide semiconductor, the steps of which are as follows: the preceding process of the double-carrier complementary metal oxide semiconductor is performed; -6-This paper size is applicable to China National Standard (CNS) A4 Specification (210 X 297 mm) (Please read the notes on the back ^ write this page first) Installation · • Line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519731 A7 _B7_ V. Description of the invention ( 4) Selectively depositing a second epitaxial layer on the base, source and drain; depositing a thin oxide layer as a pad oxide layer for making and engraving the window gap; performing a two-carrier complementary type Metal oxide semiconductor back-end process. The front-end process includes: making a double buried layer on a substrate with a first conductivity; depositing a first epitaxial layer with a second conductivity; making a well region with a first conductivity; Two conductive well areas, collectors, insulation layers and gate oxide layers; depositing a polycrystalline layer, making gates and bases, and performing complementary metal oxide semiconductor processes; depositing oxide layers and silicon nitride layers, Define the shot window, collector and source and perform I worming. The latter-stage process includes: depositing an emitter complex, making an emitter; performing a self-aligned silicide process and a later-stage metallization process. By using the method of the present invention, an N-type epitaxial layer is deposited in advance before the completion of the double-buried layer and the production of the P well, which can effectively prevent the latch-up phenomenon caused by the parasitic double-carrier effect, so even the high accumulation degree Components, its component characteristics remain unchanged. In addition, the gate, drain, and source of the CMOS are all raised because of an additional epitaxial layer that is selectively deposited. During the Salicide process, gold and metal silicides containing titanium or cobalt as the main component will originally consume a large amount of broken atoms and cause the junction to be too deep. However, in the present invention, due to the effect of the epitaxial layer cushioning, Connection of MOS source and drain-7-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --- ^ ------------- -(Please read the note on the back first to write this page) .- -_ 线 _ 519731 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of Invention () Only rose to the surface of the silicon wafer, so that The metal silicide layer is not bonded to Mos too deeply, ensuring a shallow bond between the contact metal and the component (shail〇w
JunCtlon)，此優勢即可避免電場分佈不均、離子擴散等問 碭，亚且兼可讓汲極、源極與閘極之電阻值顯著下降，維 持較佳之元件特性。 星__式之簡單說明 本發明將依照後附圖式來說明，其中： 圖Ua)〜1(e)為習知之雙載子互補式金屬氧化物半導體之 製造方法示意圖；及 圖2(a)〜2(h)為本發明之BlCM〇s製程示意圖。 13 底材 2 隔絕層 集才亟區 4 η +區 基極區 ， . 0 絕緣層 P井 0 弟一複晶層 0 10 吊一硬晶層 間隙壁 絕緣層 12 η +區域 η -區域 14 基極嫁:接 集極導通區 * 16 内層絕緣層 源極雷；te ζ / 汲極電極 基極電極 2 9 射極電極 集極電極 3 2 射極 金屬矽化物層 3 8 ρ Μ 0 s源極 p Μ 0 S汲極 一 8 ‘紙張尺度適用中國®^i^(CNS)A4規格⑽ 519731 A7 B7 五、發明說明（ 41 底材 4 2 ρ井 43 集極 44 羞晶層 45 閘極 4 6 基極區 47 間隙壁 4 8 Ν Μ〇S源極 4 9 N Μ〇S汲極 51 四氧乙基矽層 5 2 氮化矽層 53 系晶層 5 4 墊氧化層 5 5 氮化矽層 5 6 氧化層 5 7 光罩 5 8 間隙壁 5 9 射極 IL----------裝—— (請先閱讀背面之注意事寫本頁) 較佳實施例說明 本發明之BiCMOS製程在前段部分，亦即自底材啟始至 製作隔絕層為止，皆與習知之BlCM〇s製程類似，故在此不 再多加描述。 圖2 ( a)為本發明製程利用區域氧化法（L〇c〇s)製造隔 絕層後之元件剖面圖。自圖2 ( a)可看出雙埋層、N型磊晶 層4 4、P井4 2、集極區4 3、隔絕層（場氧化層）以及閘氧化 層皆已製作完成，該磊桌層的厚度約為〇 . 5至丨5 μ m。 接著’在整個元件表面沈積一複晶層，並且用的 能量將濃度為5 X 1 〇 1 4之B F 2摻雜入該複晶層内；之後在複 晶層表面上除了預定作為CMOS閘極區域之外的部分覆上 光阻’未被覆光阻的區域則以5〇keV的能量將濃度為 2 X 1 0 1 6之绅（A s )摻雜之，如此即完成了閘極4 5的定義。 一 9 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） 訂 線 經濟部智慧財產局員工消費合作社印製 然後再利用同樣的方式以1〇keX^々能量將濃度為5χ1〇ΐ5之 侧捧雜入該複晶層上的基極預定區，而完成基極區4 6的定 義。此時之結構如圖2 ( b )所示。 接下來進行NMOS與P Μ 0 S元件的製程。首先製作 Ν Μ〇S的源極4 8與汲極4 9，並且採用輕微掺雜汲極（Llght Doped Dram)技術，以避免元件積集度提升後產生短通道熱 电子效應，故間隙壁4 7也在此步騾中被形成。之後使用相 同的方式製作P Μ〇S的源極3 8與汲極3 9 ;至此，CMOS元 件的離形已然形成。如圖2 ( c )所示。 然後在整個元件全表面上沈積一層厚度約為9 〇 〇至 1100埃之石夕酸四乙酉旨層51(Tetra_Ethyl_〇rth〇_s山cate ; TEOS)，接著再沈積一層厚度約為丨丨〇 〇至丨3 〇 〇埃之氮化 矽層52 ，然後利用微影定義出元件之射窗（emitter wmdow)、汲極和源極的位置並進行蝕刻，結果如圖2(d) 所示。至此為止，本發明之雙載子互補式金屬氧化物半導體 《雨段製程已全邵完成’·㈣注意的是，前段製程並不單被 侷限在如前所述的方法，而可在不背離其精神的情況下作相 對應的變化。 在已足義出的CMOS源極和汲極與本徵基極（ base)的位置以選擇性沈積的方式沈積—層羞晶碎53，在此 也可選擇使用HBT製程中慣用的SlGe，其中鍺含量約在〇 至3 0 %的範圍；此外 孩磊晶層5 3也可被選擇性沈積在 C Μ Ο S的閘極上’以增加閘極的穸戶：·、 」ι 7見度，之後在同樣位置沈 積一墊氧化層（padoxHeb#。其結果將如圖2(e)所示。 10 519731 A7 —----—-— —__B7 _ 五、發明說明（8 ) —一 接著在元件全表面上沈積一層厚度約8 〇 〇埃的氮化矽 層55與一層厚度约25〇〇埃的氧化層56，然後利用光罩5? 將元件CMOS的位置加以遮蔽，對雙載子電晶體的部分進 行蝕刻舲主層氧化層蝕刻冗畢之後，射窗位置會有—間 隙壁5 8的形成，如圖2 ( f)所示。 下逑4步驟為本發明之B 1 C Μ〇S後段製程部分。在除 去光罩後m台製作射極；首先沈積一層複晶至元件表面 上，亚摻雜砷至該複晶層内；之後利用微影定義出射極 區，在其他未足，義區域進行蝕刻，則射極5 9製作完成。如 圖2 ( g )所示。 經濟部智慧財產局員工消費合作社印製 接著就進入後段金屬化製程的部分，在此只簡單加以 敛述。首先沈積一層未摻雜之厚度約丨5 〇 〇埃的T e〇s，而 後沈積一層厚度約1〇〇〇〇埃的硼磷矽玻璃（B p s G )，並進行 趨入（dnve-m) ’接著再沈積一層厚度約2 3 〇 〇埃之旋塗式玻 璃（S〇G )。然後進行回蝕使其平坦化。之後定義出元件上 各極的接韻窗，在包括接觸窗部分的元件全表面上沈積一 阻障層（bamer layer)，亦即利用金屬矽化物製程沈積一 T i / T 1 N層至元件上足後，再進行電極的沈積。至此整個元 件即告製作完成，如圖2(h)所示。至此為止，本發明之雙 載子互補式金屬氧化物半導體之後段製程已全部完成；但需 主思的是’後段製程亦不單被侷限在如前所述的方法，而可 在不背離其精神的情況下作相對應的變化。 經由本發明之製程所製作出的元件，較之習知的 BiCOMS元件，其優點為： ~ 11 -JunCtlon). This advantage can avoid problems such as uneven electric field distribution and ion diffusion, and can also significantly reduce the resistance values of the drain, source, and gate, and maintain better device characteristics. Brief description of the star__ formula The present invention will be described in accordance with the following drawings, in which: Figures Ua) to 1 (e) are schematic diagrams of a conventional manufacturing method of a double-carrier complementary metal oxide semiconductor; and Figure 2 (a ) ~ 2 (h) are schematic diagrams of the BlCMos process of the present invention. 13 Substrate 2 Insulation layer set in the urgent region 4 η + region base region,. 0 Insulation layer P well 0 Di-multi crystal layer 0 10 Hang a hard-crystal layer spacer insulation layer 12 η + region η-region 14 base Pole grafting: collector-conductor conduction region * 16 inner layer source mine; te ζ / drain electrode base electrode 2 9 emitter electrode collector electrode 3 2 emitter metal silicide layer 3 8 ρ Μ 0 s source p Μ 0 S drain electrode 8 'Paper size applies to China® ^ i ^ (CNS) A4 specification 519731 A7 B7 V. Description of the invention (41 substrate 4 2 ρ well 43 collector 44 crystalline layer 45 gate 4 6 Base region 47 Spacer 4 8 N MOS source 4 9 N MOS drain 51 Tetraoxyethyl silicon layer 5 2 Silicon nitride layer 53 Crystalline layer 5 4 Pad oxide layer 5 5 Silicon nitride layer 5 6 Oxide layer 5 7 Photomask 5 8 Partition wall 5 9 Emitter IL ---------- install-(Please read the note on the back first to write this page) The preferred embodiment explains the invention The BiCMOS process in the previous part, that is, from the beginning of the substrate to the production of the insulating layer, is similar to the conventional BlCM0s process, so it will not be described here. Figure 2 (a) The cross-sectional view of the element after the isolation layer is manufactured by the area oxidation method (Locos). From Figure 2 (a), we can see the double buried layer, N-type epitaxial layer 4 4, P well 4 2, and the collector region. 4 3. The isolation layer (field oxide layer) and the gate oxide layer have been completed, and the thickness of the epitaxial layer is about 0.5 to 5 μm. Then, a polycrystalline layer is deposited on the entire surface of the element and used BF 2 with a concentration of 5 X 1 0 1 4 is doped into the polycrystalline layer; after that, a portion of the surface of the polycrystalline layer other than that intended to be a CMOS gate region is covered with a photoresist. The area is doped with a concentration of 2 X 1 0 1 6 (A s) with an energy of 50 keV. This completes the definition of the gate electrode 4 5. 9 This paper size applies the Chinese National Standard (CNS ) A4 specification (21〇X 297 public love) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and then using the same method to mix the side with a concentration of 5 × 10〇5 into the compound with 10keX ^ 々 energy. The base region on the layer is predetermined, and the definition of the base region 46 is completed. The structure at this time is shown in Fig. 2 (b). Next, NMOS and P are performed. 0 S device manufacturing process. First, source 4 8 and drain 4 9 of N MOS are produced, and a lightly doped drain (Llght Doped Dram) technology is used to avoid short channel hot electrons after the component accumulation is improved. Effect, the partition wall 47 is also formed in this step. Thereafter, the source 38 and drain 39 of the P MOS were made in the same way; so far, the CMOS element has been formed. As shown in Figure 2 (c). Then deposit a layer of Tetra_Ethyl_〇rth〇_s mountain cate; TEOS with a thickness of about 900 to 1100 angstroms on the entire surface of the entire component, and then deposit another layer with a thickness of about 丨 丨〇〇 ～ 丨 300 SiO2silicon layer 52, and then use the lithography to define the position of the emitter window, drain and source of the device and etch, the result is shown in Figure 2 (d) . So far, the dual-carrier complementary metal oxide semiconductor of the present invention "The rain section process has been completed" · Note that the previous stage process is not limited to the method described above, but can be done without departing from it. Make corresponding changes in mental situations. Selectively deposited on the CMOS source and drain and the intrinsic base (layers)-layer shattered crystals 53. Here, you can also choose to use SlGe commonly used in HBT process, where The content of germanium is in the range of 0 to 30%; in addition, the epitaxial layer 5 3 can also be selectively deposited on the gate of the CMOS ′ to increase the gate user ’s visibility: After that, a pad oxide layer (padoxHeb #) is deposited at the same position. The result will be shown in Figure 2 (e). 10 519731 A7 —----—-— —__ B7 _ V. Description of the invention (8) — one after the other A silicon nitride layer 55 with a thickness of about 800 angstroms and an oxide layer 56 with a thickness of about 2500 angstroms are deposited on the entire surface of the device, and then the position of the CMOS of the device is shielded by using a photomask 5? The part of the crystal is etched. After the main layer oxide layer is etched redundantly, the position of the shot window will be formed with a partition wall 58, as shown in Figure 2 (f). The next four steps are B 1 C Μ of the present invention. Part of the post-S process. After the photomask is removed, m units are used to make the emitter; firstly, a layer of polycrystal is deposited on the surface of the element, and sub-doped arsenic is Then, the emitter region is defined by lithography, and the remaining regions are etched, and the emitter 5 is completed. As shown in Figure 2 (g). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Then enter the part of the later metallization process, which will only be briefly summarized here. First, a layer of undoped T e0s with a thickness of about 5,000 Angstroms is deposited, and then a layer of about 1000 Angstroms is deposited. Borophosphosilicate glass (B ps G), and dnve-m ', and then deposit a layer of spin-on glass (SOG) with a thickness of about 2300 angstroms, and then etch back to flatten it. . Then define the rhyme windows of the poles on the element, deposit a barrier layer (bamer layer) on the entire surface of the element including the contact window portion, that is, use a metal silicide process to deposit a T i / T 1 N layer to After the element is fully loaded, the electrode is deposited. At this point, the entire element is completed, as shown in FIG. 2 (h). So far, the subsequent process of the ambivalent complementary metal oxide semiconductor of the present invention has been completed; But it ’s important to think about it, It is limited to the method described above, and can be changed correspondingly without departing from its spirit. Compared with the conventional BiCOMS element, the element produced by the process of the present invention has the advantages: ~ 11-
519731 A7 B7 五、發明說明（ 2 4 經濟部智慧財產局員工消費合作社印製 本發明在雙埋層製作完成、P井製作之前預先沈積 型之磊晶層’其可有效防止元件因雙載子效應所產生 的閉鎖現象’故即使是南積集度的元件，其元件特性 仍不至於改變。 習知之雙載子電晶體製程係利用離子植入法來製作基 極，此方式使基極寬度不容易受到控制；未來的趨勢 則會利用Η B T法來製作雙載子元件，亦即使用s i G e 來製作基極。本發明將使用於雙載子電晶體製程之 Η B T法應用至BKMOS製程，並一併應用在c M〇s部分 的製造上；故本發明不但可準確控制基極寬度與深 度’甚至可製作深度只達5 0 0至1 0 0 0埃的基極，又兼 可達到製作一高頻C Μ 0 S的目的。 本發明以選擇性矽磊晶或S i G e沈積的方式，將c Μ 〇 s 的源極與沒極墊高。墊高的汲極與源極不但可以藉該 沈積層降低其電阻值，並且在後續的金屬矽化物製程 中’也可有效防止接合過深，確保兩介面之間的淺接 合。 本發明射窗部分的間隙壁與一般閘極間隙壁較不同， 其厚度需要被精確的控制以確保射極的完整；但是在 BlCMOS的製程中常會碰到許多牽涉到HF清潔的步 驟’為不使該等步騾影響到元件的完整，故在本發明 中並不單採用τ e〇S層製作射窗之間隙壁，更進一步 增加一氮化矽層，始可有效避免元件受到HF的侵蝕= 影響到間隙壁的厚度。 一 12 - ------τ I 卜--------- (請先閱讀背面之注意事寫本頁) .- ，線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 519731 A7519731 A7 B7 V. Description of the invention (2 4 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The invention has a pre-deposited epitaxial layer before the completion of the double buried layer and the production of the P well. The latch-up phenomenon caused by the effect 'so even the components of the South accumulation degree, the characteristics of the components will not change. The conventional bipolar transistor manufacturing process uses the ion implantation method to make the base, this method makes the base width It is not easy to be controlled; the future trend will use 制作 BT method to make the bipolar element, that is, use si Ge to make the base. The present invention applies the Η BT method used in the process of bipolar transistor to BKMOS The manufacturing process is also applied to the manufacture of the c M0s part; therefore, the present invention can not only accurately control the width and depth of the base electrode, but also the base electrode with a depth of only 500 to 100 Angstroms. The purpose of making a high-frequency C M 0 S can be achieved. The present invention uses a selective silicon epitaxial or Si Ge deposition method to pad the source and non-electrode of c M 0s. The source can not only reduce the Resistance, and in the subsequent metal silicide process, it can also effectively prevent the joint from being too deep and ensure a shallow joint between the two interfaces. The gap wall of the shooting window part of the invention is different from the general gate gap wall, and its thickness needs to be It is precisely controlled to ensure the integrity of the emitter; however, in the process of BlCMOS, many steps involving HF cleaning are often encountered. In order to prevent these steps from affecting the integrity of the component, τ is not used in the present invention. The e〇S layer is used to create the gap wall of the shot window, and a silicon nitride layer is further added to effectively prevent the element from being eroded by HF = affecting the thickness of the gap wall. 12------- τ I BU- -------- (Please read the note on the back first and write this page) .-, The paper size of the thread is applicable to China National Standard (CNS) A4 (210 X 297 public love) 519731 A7