TW519599B - Component-activity data flow equation on compiler for low power instruction sets - Google Patents

Abstract

The invention relates to a component-activity data flow equation on compiler for low power instruction sets and the system primarily comprises three subsystems of the construct control flow graph, the equation analysis for primary data as component and the instruction codes optimization. Locate the block of certain component in source codes without activity for long while during the activity state of each component when processor is executing, and using the data compiler inserts sleep function of component before the block to speed up the sleep state of component, achieving power saving effect. The invention can be both applied to component environment of hardware; if a hardware component is idle for a while, it will automatically shut off power. Targeting at different instruction arrangement of compiling, the invention collects power on and off states of component during execution and assesses different command arrangement so as to ascertain which can save more power in terms of component activity. The invention can be applied to portable electronic appliance, chip of portable communication equipment and embedded system.

Description

519599 V. Description of the invention (1) Field of the invention The present invention relates to a component-based data flow equation analysis (component based data f 1 ⑽ eqUati ana 1 ysis). In particular, it is about a method that analyzes the components of the compiler (commpiler) as the main data stream equation analysis method by combining the Baishi's red and eighth, sucking the instruction set (100w ρ 〇 er instruction set) in the compiler. Background of the Invention The general-style re-enactment of the benefit band took many days to bring on the disguise of the disguise, and to solve the hard themes of the problem is to solve the problem of consumption. The best source of digestive questions and re-questioning can often be spent doing. The production of non-consumption is also related to the problem of electrical transformation and the problem of over-problem questions. Questions about the integration of good production and the system are devoted to consumption. The writing is due to the softness of consumption, and the source inlay. For the special year and the soft needle national year ,. For the United States, which has a beautiful appearance, Ea Yang and Dianliang are similar to U.S. Patent Nos. 5,79,8,7 4 in that they analyze the dependencies between program instructions and adjust the order of instructions ( instruction sequence) 'to save power consumed by the instruction bus. The application of the top domain is the reduction of the distance of h a m m i n g (m i n i m i z i n g h a m in i n g distance) 〇 US Patent No. 5,8 8 〇, 9 811 document, discloses a kind of

519599

V. Description of the invention (2) Competent method. Among them, the technology of the number of times can achieve the effect of reducing power consumption and transmitting data to the multiplier (mu 1 t 1 p U) in a low-level digital signal processor. The US patent says 5,9 2 0,7 1 The literature of 6 discloses a method for compiling the p segment using a data flow analysis method to analyze the predicate code in the program (predicate = code), and grasp the regional (i0cai) predicate and global (gl〇bai) preacher. Education of the relationship. In another US patent No. 5, 9 2 0, 7 1 6 related to predicate code analysis, the data flow analysis method is used to analyze the entire procedure in the program. The predicate code of each block in the flowchart generates a set of basic sets, and then generates a set of live sets (1 iveset) for each predicate in the basic set. 'This system & Provides information between the registers when a register (a 1 10 cate register) is configured.

In addition, 'Related Papers' is more relevant to D avid I. August # A ^ " Proceedings of the 30th International Symposium on Microarchitecture, December 1997, pages · 92-103 n, nA Framework for Balancing Control Flow and Predication ", this document proposes a software framework (framework), using this framework to effectively collect data flow and control flow (c ο ntr ο 1 f 1 ow), and use this information to assist the compiler to optimize the software化 动。 The action. Another article by Erik Ruf in Micros oft Research, March

Page 5 519599 V. Explanation of the invention (3), 〇 PtimiZlng SpaI * Se Representatlons matrix) == J This document ^ Ten pairs of sparse matrices (sparse formula for this silk, not / 仃 nine, through the material The flow equation is used to collect the process, and the use of this sparse I material is shown in HI51. Using this method, Asia uses this information to re-express less conversions. ^ When the sparse data is taken, it can achieve the most targeted software generation process Improving the original code space in the process of inversion makes the software use less optimization processing, which can reduce the active energy of the components in the processor to achieve the desired performance during programming.

" Generally speaking, every element in the processor of an electronic system

There are two states in the "executlon cycle": one is the active state UctlVe State, and the other is the resting state (the rest state is active during the sad day, the components are in the charging state), which can be requested at any time according to the instructions In order to perform the given task, or are busy executing instructions. In the dormant state, the 'elements do nothing at all' is in an idle (idU) state. Zheng Temple is waiting to execute the instructions without consuming any power or consuming a small amount of power. However To return from the hibernation state to the active state requires an additional power supply, called peak voltage. Generally, the components are in the hibernation state before executing certain software. Once the components enter the active state due to execution requirements, In this state, the device will not be forced to enter the sleep state after a period of inactivity, which is called timeout. The length of the time-out period is different for different components.

519599 V. Description of the invention (4) However, from a low power perspective, during the period of time exhaustion, a lot of unnecessary energy is wasted because the components consume power to make them active, but in fact there is no Action occurs. In order to solve the problem of energy waste of the components in the processor, the present invention proposes an effective solution. The component-based data flow equation analysis program is used to improve the original code in the process of programming and reduce the components in the processor. Reduce power consumption during events. SUMMARY OF THE INVENTION The main operating principle of the component flow analysis system of the present invention is to use components as the main stream equation analysis program 'combined with a low-energy instruction set in the compiler to find the active status of each component when the processor is executed in the future. The section where a component in the code has not been operated for a long time, and using this information, the compiler can insert the component sleep function before this section, and promote the component to enter the sleep state early to solve the problem of energy waste. One of its main purposes is to provide a component flow analysis system that integrates a low-energy instruction set in the compiler. This component flow analysis system mainly includes three subsystems, that is, the construction control flow chart (conn s t r u c t f 10w g r a p h), the component-based data flow equation analysis, and the optimal instruction code. 519599 V. Description of the invention (5) Sun and Moon < Another purpose is to provide a method for designing the component flow analysis system. ^ ^ 〇x ^? Construct control flow chart "module will use the original instruction Ma Yi 2 * autumn sequence to branch (loop), loop (1 oop) and other control flow in the graph to increase y α% to show The program instructions are cut into several basic blocks = the sequence of processes between different basic blocks is indicated by arrows. Its input is the original private code 'and the control flowchart is rotated out as the original code. The Component-Based Data Flow Equation Analysis module also includes two sub-modules. One sub-module is used to calculate the component generation set (common set), and the other sub-module is used to calculate the component entry set (common set), and the component extinction set (common set km) ) And component out set. The Baguang 1 command code is the best: dagger; the 则 group obtains the activity of the parent component from the "component-based data flow equation analysis" module, and can be dormant for several instruction cycles: ' … Under the condition of continuous power saving, in this instruction interval = order area 'and satisfying

Put the component to sleep to save energy. Therefore, the original process outputted by the component sleep function and the control flow chart is the components of the above-mentioned subsystem "building model", "computing component entry set, component two-system flow chart, and shanghe". Leaving the set, and turning out to change the set and the pieces left the set. Post-optimization style

519599 V. Description of the invention (6) According to this, the present invention can be adapted to the environment of hardware components at the same time. If a hardware component is not used for a while, it will automatically turn off the power. Instruction scheduling method 'The present invention can collect the status of power on and off of components in the program execution status' to judge different instruction scheduling methods, which is more power-saving in terms of component activities. The above and other objects and advantages of the present invention are described in detail below in conjunction with the following drawings, detailed description of the embodiments, and the scope of patent applications. Detailed description of the invention FIG. 1 is a block diagram of a component flow analysis framework of the present invention. As shown in Figure 1, 'The component flow analysis framework is divided into a "construction control flow chart" module 101, a "component-based data flow equation analysis" module 丨 02, and a "script optimization module" 1 〇3. The "Construction Control Flowchart" module 1 〇1 constructs a directed graph. This directed graph will control the process information (n ow — 〇ίο 〇ntr 〇1 inf〇rmati〇η). The women's platform instructs Shima to collect the block. The "component-based data flow equation analysis" module 10 includes two submodules 102a and 102b. Submodule 1 0 2a is used to calculate the component generation set of each block in the control flowchart, and submodule 1 0 2b is used to calculate the control flowchart

liillis 111

Page 9 ---- 、 Explanation of invention (7) The component destroys the collection and the component leaves the collection. According to the present invention, according to the present invention, the "direct control of the original eight-digit code ^ six" ^ structure control flowchart "module constructs the directed graphic newsletter with the graphic report,, main 1 ', ,, and heart. Circles and other control process data blocks: Two t show *, and cut the program instructions into several basic l0 ^ _ native process sequence to establish a link (1 ink), as represented by the river head ' Process. And "Yuan Zheyan +-Instruction Use Wang Li Cry '/ Poor 2 Stream Equation Analysis" module 102 analyzes each equation and accurately calculates ::::' s state, #analyzes components with repeated data streams. : Program 2 whose status is active in the clock cycle of the day ^^^^ 2 ^ ;; s: ;; c ^; + 〇 ^ ^^^ > a ^ ^ < ^-^ vinstruction cvni ^ \ ,, ^ is the instruction area for sleep 卩 彳 #), add one before the interval of state of sadness: sleep under the condition of: electricity, this instruction sleeps the function, let the component sleep to save energy. , Xiayang, ,, Tian. Er Ming detailed process of each module. Figure 2a illustrates the flow of the construction control flow chart of the "process chart" module 101. "Construction: /; IL module 1 0 1 is the original program

V. Invention description (8) code, and the output is the control flowchart of the original process. Referring to FIG. 2a, the control flow is step 2 0 2 2 4: < The construction process is sequentially divided into the following four steps 201: determining the original codebook block (basic h 2 statement) as the base 10ck Title (ieader). Step 2 0 · For each bow, the basic block is self-assembled into a basic block, with the first but not including the following :: chanting 'includes all the following descriptions, * The description after the first bow 1. Step 203: According to the original program, indicate the flow. Establish a bond to connect different basic blocks. Step 204: Divide the $ in the basic block, that is, only one narrative in each block is divided into one block, and one is included. According to the present invention, ^ of step 2 〇]

A narrative is a quotation. The rules of (b) 'and 疋 are: (a) the (conditional goto) or non-parallel second of the program == conditional jump a ^ kk ^ ^ p \ (unconditional goto) That is an i-quote, (c) yu g〇1: 0; the narrative after the conditional goto 卽 oxygen ☆ soil ', i-extends one hundred quotes. The way to establish a link in step 20 3 can be an arrow to indicate the process.

$ 11 pages 519599 5. Description of the invention (9) Figure 2b is an aAlpha machine code (the original source code of machine cod 'is used as the "establishment control flow chart" module "= 保 岳 丨! 2c is the original program of Figure 2b After the code passes through the process steps of Fig. 2a, the resulting B & 5 diagram is generated. In Fig. 2c, according to the decision rule of step 201, the block step 2 BBH6 and the strict block & According to the SB XL basic block, it contains blocks & to block B] 〇. Ghost 11 to & block ^, block B16 to block I, and block 3 B3. According to step 20 3, the entire Figure 2c is the control flow chart: ▲ Step m 'The four basic blocks are divided into two broad blocks and only one narrative is included. Call it £ _3Q, and the mother and b2 assume that the original program can be divided into μ solid regions. Blocks, respectively]

Bk, there are n elements to be analyzed, which are Cl, c, c,. C. According to the present invention, the element 逄 4 2 3, cn is calculated. The root code, Hu Ba 1 & Raw 2's module 1 02a's input is the comparison table of the original dagger two, ... "The set of components that create the control flow and the number of all & blocks per zone. Fig. 3a illustrates the necessary sequence of the module 102 "" soil:] :::, as shown in Fig. 3a. Refer to the following three steps: 301 ~ 303: Step 301: For each block, add one for each element to be analyzed.

Page 12 519599

V. Description of the invention (10) Two-dimensional array parameters C yc 1 e C 〇unt, and the initial values of all elements of CycleCount are set to 0, that is, CycleCount [Bi] [Cj] = 0, where 1 — I ^ k, j ^ n. CycleCount [Bi] [Cj] is used to indicate the number of sequences required by block B to use component C. Step 302: In each block, construct a component comp_gen set that belongs to the block. And set the initial value of this set to an empty set. Step 303: According to the execution order of the instructions, do the following actions on the instructions in each block bi: Look up the relationship between the instruction and the component use from the comparison table between the instruction and the component use, assuming that the instruction uses the C component & j fixed time sequence, C weapon CC 2 time sequence .... c dead piece cc ^ solid time 1 sequence adds components with time sequence number other than 0 to the block's generation 隹, and the CycleCounttBiHC! ^ value Plus cc city, co

The value of CycleCount [Bi] [(: 2] plus CC2, ... ,, Γ The value of CycleCountCBJCCJ plus CCn. Now an example is as follows: Suppose a source code, in ten

There are six instructions I to I ^ in B to 1Q, as shown in Fig. 3b. In the ~ system, there are four types of elements CrCr analyzed by Cr. The CrCr is an arithmetic logic unit (ALU) slave ^ multi-pier, divider, Zhiji 丨 triplex ^ shell material confluence

Page 13 519599

5. Description of the invention (π) row (data bus). Fig. 3c shows a list of instructions and components used in Fig. 3b. For example, it is known from FIG. 3M that the block B executes the instruction I 1, and from FIG. 3 ′, it is known that the instruction I uses the arithmetic logic unit of the component C and executes the instruction! F c timings are required. Therefore, the value of Cy c 1 e Coun t [B 2] [C!] Is increased by 3 and the block b μ produces a set containing element C !. After processing the calculation step 3 of this component generation set, the component generation set of each block and the sequence number CycleCount [Bi] [Ci] required by the component C to use the component C are obtained, as shown in the figure next. Figure 4a illustrates the detailed flow of module 10 2b calculating the components entering the collection, the components destroying the collection, and the components leaving the collection. The rotation of module 10 2b is the original program control flowchart output by the above-mentioned "establishing control flow chart" module 101, and each area rotated by "calculation element generation set" module 1 02a. The elements of a block generate a set, and each block uses the timing number required by each element, and the output is the entering set, eliminating set, and leaving set of the elements of all blocks. Assume that the original program uses k blocks 'and uses marriage components' to input a set comp-gen [Bi] for the components of each block Bi and each block B uses the timing number Cyc 1 eCount [ B i] [C] ·], the output is that every element of block B enters the set comp-i n [B ”, the element destroys the set comp ki 1 1 [BJ and the element leave the set comP-〇ut, where K Dk and 1 $ η.

Page 14 519599 V. Description of the invention (12) Referring to Figure 4a, this detailed flow is divided into the following three steps 401 ~ 403 in order: Step 4 0 1 · In the parent-block I, construct the block belonging to the block h. The element enters the set comp — intBi], the element> Xiao Xiao set comp — ki 1 1 [^], and the element leaves the set comp — out [B,]; the element enters the set comp + infBi] and the element eliminates the set c0mp —ki 1 The initial value of 1 [Bi] is set to the empty set, and the initial value of components leaving the set comp__ou t [Bi] is set to the components of the block to generate the set comp —gen [Bj]. Step 4 0 2 · Do the following for each block & 4 0 2 a: For each element Cj to be analyzed, compare the CycleCountfBjfQ] value of all predecessors, and take the maximum value. Assume that the maximum value is CCmax. If CCmax is not 0, the value of CCmax is decreased by 1. If the value after the decrease is 0, component Cj is added to the component elimination set comp_ki 1 1 α] of the block. If the value of (CCmax-1) is greater than the value, then set the value of C yc 丨 e C 〇unt [Bi] [Cj] to (CCmax-1) 〇 4 0 2 b ·· Enter the components of this block The set c 0 mp _ in [Bi] is set as all elements of the previous block of the block leave the union of the set comp — outiBd, that is,

Page 15 519599 V. Description of the invention (13) comp-intBi]: Ucomp_ut [P], where P is the previous block of 1. 4 0 2 c ·· Separate the elements of the Yanxuan block from the set c0mp —〇ut [B]] The history of the block is that the element enters the set comp_in [Bi] and the element destroys the set comp_k i 1 1 [Bi ] After the difference (difference), and then compose the set comp —gen [BJ as a joint set, that is, comp —outA] = comp —gentB!] U (comp_i n [B1]-comp_k i 1 1 [B} ]). Step 40 3: Repeat step 40 2 until the elements of all blocks leave the set and no longer change. Using the above-mentioned Figures 3C to Bi4 contains six element cores ~ (: 4, material bus. The control flow is set to "calculate elements to generate a set. Combination, component elimination (blt) combination does not include this

The description is as follows: Figure 4b illustrates an input source code. Use the instruction and component comparison table shown. There are four types of instructions L to Iβ in 4 blocks, and there are four kinds of logic logic units, multipliers, dividers, and the original code of Figure 4b. The original program control flow chart rotated by the subsystem "Building Map" 101. Figure & d pieces generation set "module 丨 〇 2a components of each block output Figure 4e is the initial component entry set and component departure set obtained in step 401, where each set consists of ^ a Represents the four elements of C], (: 2, Q, Q, 0 means this set of elements, 1 means this set contains this element. For example, wood

Page 16 519599, Description of the invention (14) " ----- comp-out [B2]: l00〇 means comp-0ut [B2] This j solid component leaves the set "module 1 0 2b The output element enters the 7 ^^^^ elimination set [Bi], the element elimination set c0mp — ki 1 1 [β ·], and 0 c0mP — in comp — out [Bi] are shown in FIG. 4f. Leaving the set of components does not include component C2, component C3, and component c. After combining the operations of ί 0 2, "the computing element enters the set of 4, yuan, and 2 steps. The output element of 102b and the set of Huai Xiao minus and * Ding sent the set as dormant to respond to instructions; The state, but often, the status of the component due to the implementation of the component. Judgment value) The component does not consume any status at all in each component implementation. It takes a lot of places. After the 1J will do it, the status of the line cycle is charging. Either as an action power source or as a threshold for the b-threshold value, it must be in the hibernation state, as described before, in each state. In the command demand, while in the hibernation state is waiting to be executed. For a long period of time, determine whether the yuan is recorded as L_st. When the active state is executed, the component instruction is executed without returning to the active body. After the component is in the active state, there is no moving part for a period of time. The executive system is in idle state. It consumes a small amount of external power. Once in this state, it is forced to enter sleep (critical hibernate = clear for different component hardware designs). Corresponding to the column) the right 1 element provides on / off (〇n / 〇ff) hardware design, that is, this element can only be issued or the order set, cut off its power supply, so that the yuan 519599 Description of the invention (15) The item changes from a power-consuming state to a non-power-consuming state. In this case, the value of Lc〇nst can be determined according to the following cost model (c 〇s ^ ^ 〇de 1)

* ACT (v); P (V) + SLEEP (v) according to this λ formula. The minimum value of ten different Lc0nst, where p (v) is the large peak package I of the piece, SLEEP (v) is the voltage that puts the element into sleep state, and ACT (V) is the value that keeps the element in the active state Voltage. (b) If the component only provides low power consumption or instruction set, reduce its electrical status to low power consumption status. The following cost model determines: The physical design, that is, this component can be provided according to the instruction source. The component is consumed under this condition, and the Leonst value can be determined by

P (v) + SLEEP (v) const [ACT (v)-LPOff (v) Execution: Is the element maintained in a low-consumption execution cycle? Σσ a ^ ^ Sleep time is longer than the L element Continuously enter the sleep function value before this continuous time zone. 'Next, Fig. 5a illustrates the detailed flow of m of the present invention. "Instruction code optimization, optimization" module Dan kli machine% map "output group i gate I original I control flow chart

Page 18

519599 V. Description of the invention (16) and the module "Calculate component entry collection, component elimination collection, and component departure collection" 1 0 2 b The component departure collection output, and "instruction code optimization" module 1 0 3 The output is improved optimized code. Suppose there are n elements to be analyzed, which are C !, C2, C3, ..., C n, and the full set (a 1 1 s e t) contains all the elements. Suppose the program can be divided into k blocks B i, and the component departure set of each block is comp_out [BJ, where 1 $ i ^ k. Referring to FIG. 5a, this detailed flow is sequentially divided into the following four steps 50 1 to 5 0 4: Step 5 0 1: In each block B !, construct an active set and a dormant set belonging to the block B 妁, The active set refers to the set of active elements in the block, and the dormant set refers to the set of dormant elements in the block. Therefore, the active set is the leaving set of the block, and the dormant set is the result of the difference between the full set and the active set. . It can be expressed in an array as action [Bi] and rest [Bi], where 1 $ i ^ k. Step 502: For each basic block, the dormant sets of all the blocks are intersected one by one, and the result is stored in another array. The sets in the array are intersected one by one, and then Store in another array, repeat this action until all in the array

Page 19 519599 V. Description of the invention (17)

The collections are all empty collections. The result of the first pairwise intersection is stored in R2, the result of the second pairwise intersection is stored in and so on. Assume that a total of 1 intersections have been done, that is, all the sets of R1 + 1 are empty sets. Step 503: For all the sets in & that are not empty sets, assuming that the set is the jth set in &, perform the following actions on all elements in the set: if 1 is greater than the Lec) nst of the element, Then it records the information that the component can insert the hibernation function before the jth block, and also records the information of the interval (j, j + i) for future viewing. Before recording the information, check whether the component and the interval are included in the recorded interval. If the above situation is true, skip the recording action. Step 504: According to the record, insert the sleep function instruction of the component in the code. An example is as follows: Suppose that the component Lec) nst value in Figure 5b represents the component “computing component entering collection, component destroying collection and component leaving collection” 1 0 2 b. The status of the component to be analyzed at each instruction, such as This is shown in Figure 5c. After processing by the "command code optimization" module 103, the heart value of each block is obtained, as shown in Figure 5d. It is learned from Figure 5d that the element (arithmetic logic unit) is dormant for 5 consecutive execution cycles after B5, and this time is greater than the LeQnst of the arithmetic logic unit (2: 4).

Page 20 519599 V. Description of the invention (18) It is stated that a sleep function for putting an arithmetic logic unit into sleep can be inserted before & such as the SLEEP instruction. In the same king, you can also insert a sleep function that allows C3 (divider) to enter the sleep state, such as the SLEEP instruction, and you can insert a sleep function that lets Q (multiply into the sleep state, such as the SLEEp instruction) before the mind.叩 J When withdrawing from the comprehensive system, when the system and state are settled, this information piece can be reasonably made and written in a timely manner. The present invention does not enable the execution of the activities described in the order arrangement to combine low-cost methods. Find the process, compile The battery can be used at the same time when it is in the portable electronic memory battery. However, the present invention can instruct the system to set a certain device in the code to be in this sleep state, sub product, brain, or when in use. It is suitable for hardware to automatically turn off the invention, and judge power saving. Use the component to insert the long-term section of the compiler processor to save the embedded system's portable communication system, and the component is closed to the power supply to collect the component Different refers to the tribute 'providing no integration of component energy during the trip, will not affect the situation', such as the arrangement of the logistics side for different power orders The effect of the dormant work D is not the same as in the chip. It is the same as the opening and the way, the program analysis process flow analysis of the active section of the piece, the use of energy, to promote the use of modern digital personal assistance. The performance of the present invention. The difference in the translation of the body components means that the program is closed in the program or in the component. The above description is only for comparison of the present invention. This cannot be used to limit the scope of the present invention. , | Equal changes and modifications made within the scope of benefits, all V: The present invention applies to the invention patent 1

P.21 519599 V. The scope of invention description (19). ❿

Page 22 519599 Brief Description of Drawings Figure 1 is a block diagram of the component flow analysis framework of the present invention. Figure 2a illustrates the detailed flow of the "control flow chart" module of the present invention. Figure 2b is an original code written in the A 1 pha machine code language, which is used as the input to the "Building Control Flowchart" module 101. Fig. 2c is a control flowchart generated by the original code of Fig. 2b after the process steps of Fig. 2a. ❶ Figure 3a illustrates the detailed process of generating a set of computing elements for module 102a. Fig. 3b illustrates an original code as an input to the module 102a of the "computing element generating set" of the present invention. Fig. 3c shows a comparison table of instructions and components used in Fig. 3b as an input to the module 102a of "computing component generation set" of the present invention. Fig. 3d shows the assembly of components generated after the steps of Fig. 3b and Fig. 3c after the steps of Fig. 3a. ❿ Figure 4a illustrates the detailed flow of module 10 2b computing elements entering the collection, destroying the collection, and leaving the collection.

Page 23 519599 Brief description of the diagrams Figure 4b illustrates an original code ′ as the input of the different elements of the present invention into the assembly, the destruction of the assembly, and the departure of the module 10 2b of the assembly. Fig. 4c is an original program control flowchart outputted by the original program code of Fig. 4b through the "establishment control flowchart" module. Figure 4d is the component generating set of each block output by the module 1 0 2a computing component generating set of Figure 4b. Figure 4e shows the initial component entry set, component elimination set, and component departure set obtained by step 102 of the calculation of the component entry set, the component elimination set, and the element leaving set by the module 102b. FIG. 4 is the component entry collection, component elimination collection, and component departure collection obtained after the module 102b of the present invention calculates component entry collection, component elimination collection, and component departure collection 402. Figure 5a illustrates the detailed flow of the "instruction code optimization" module of the present invention. FIG. 5b illustrates the L⑽st value of a component as the input of the “instruction code optimization @ 化” module of the present invention. Fig. 5c is the output of the original code of Fig. 4b through the module "computing component entering set, component destroying set and component leaving set" 1 0 2b of the present invention.

Page 24 519599 The diagram briefly illustrates the state of a component at each instruction. Figure 5d is the output obtained by the "instruction code optimization" module of the present invention. Description of drawing number 1 0 1 Construction control flowchart module 1 0 2 Element-based data flow equation analysis module 10 2a Module for generating sets from calculation elements 1 0 2b Module 10 for entering into sets, destroying sets and leaving sets 3 Instruction code optimization module 2 0 1 ~ 2 0 4 Steps of constructing the control flowchart of the present invention 3 0 1 ~ 3 0 3 Steps of the calculation module generating assembly module of the present invention by step 4 0 1 ~ 4 0 3 Flow steps of the computing element entering the collection, destroying the collection and leaving the collection module of the present invention 5 0 1 ~ 5 0 4 Flow steps of the optimization code of the present invention

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Claims (1)

519599 6. Scope of patent application 1. A component flow analysis structure in a compiler that combines a low-energy instruction set: Contains: A control flowchart module is constructed, and a directed graph is constructed. The instruction code is cut into a plurality of basic blocks, and the control flow information is added to the set of blocks of the input original instruction code according to the flow order, and the flow order between different basic blocks is represented by the establishment of a chain; A component-based lean flow equation analysis board group 'analyzes the state of the component in each instruction using the processor according to the directed graph, and uses a data flow analysis method to calculate the component whose status is active in each time sequence; and An instruction code optimization module obtains the activity status of each component from the component's main data flow equation analysis module, and finds out the instruction interval where the component is in a dormant state under several consecutive instruction cycles. A sleep function is added before the interval to let the component sleep to save energy. 2. The component flow analysis structure described in item 1 of the scope of patent application, wherein the component is the main data flow equation analysis module and further includes the following submodules: a first module for calculating in the directed graph The components of each block generate a set, and the number of timings required for each block to use the components; and a second module, which is used to calculate the components of each block in the directed graph into the set, and the components are eliminated Collections and symbols leave collections. 3. The component flow analysis structure described in item 1 of the scope of patent application, where Page 26 519599 6. Scope of patent application Provide different sleep function for different component hardware design. 4. The component flow analysis structure described in item 3 of the scope of patent application, wherein if the component provides an on / off hardware design, the component cuts off the power supply of the component according to the instruction or instruction set 5 to make the component The tragic transition from power consumption to non-power consumption. 5. The component flow analysis structure described in item 3 of the scope of patent application, wherein if the component only provides a low power consumption hardware design, then the component is issued in accordance with the instruction or instruction set, reducing the supply of power to the component From power consumption state 丨 _ to low power consumption state. 6. —A method for analyzing the component flow of the compiler in combination with a low-energy-consumption instruction set, including the following steps: (a) constructing a control flowchart which cuts the input original instruction code into a plurality of basic blocks, According to the flow order, the control flow information is added to the set of blocks of the input original instruction code, and the flow order is established by establishing links between different basic blocks; (b) Analyze each according to the control flow chart The instruction uses the state of the component in the processor and uses a data flow analysis method to calculate the active component in each time sequence; and (c) obtains the active status of each component from the component's main data flow equation analysis module. , Find out the component under several consecutive instruction cycles, the state Page 27 519599 VI. Scope of patent application The instructions are all dormant instruction intervals, and the original instruction code is optimized to make the component sleep and save energy. 7. The component flow analysis method described in item 6 of the scope of the patent application, wherein the construction of the control flow chart of step (a) further includes the following four steps in order: (a 1) determine those statements in the original code as The headings of the basic block; (a2) For each heading, a basic block is formed, with the heading as the beginning of the basic block, including all the following descriptions, but not including the description after the next heading; a 3) According to the original program, a link is established to connect different basic blocks to represent the process; and (a 4) each of the basic blocks in the basic block is divided into one block. 8. The component flow analysis method described in item 6 of the scope of patent application, wherein step (b) further includes the following two steps in order: (b 1) Calculate the component generation of each block in the control flowchart Set, and the number of timings required for each block to use the component; and (b 2) Calculate the component entry collection, component elimination collection, and component departure collection for each block in the control flowchart. ® 9. The component flow analysis method described in item 6 of the scope of patent application, wherein the construction of the control flow chart of step (c) includes the following four steps in order: Page 28 519599 VI. Patent Application Scope (cl) In each block & construct the active set and dormant set belonging to the block B, the active set refers to the set of active elements in the block, and the dormant set is Refers to the set of dormant elements in the block, the active set is the leaving set of the block, and the dormant set is the result of the difference between the full set and the active set; (c 2) For each basic block, sequentially intersect the dormant sets of all the blocks, and store the results in another array, and then intersect the sets in the array in order. To another array, repeat this action until all sets in the array are empty sets. The result of the first pairwise intersection is stored in R2, the result of the second pairwise intersection is stored in R3, and so on. Assume that a total of 1 intersection has been made, that is, all sets in RH1 are empty sets; (c 3 ) For all the sets in & that are not empty sets, assuming that the set is the jth set in R, do the following actions for all elements in the set: If 1 is greater than the L_st of the element, record that this element can be used in The information of the sleep function is inserted before the jth block, and the information of the interval (j, j + 1) is also recorded as Use for back view. Before recording the information, check whether the component and the interval are included in the recorded interval. If the above situation is true, skip the recording action; and (c4) insert the sleep function of the component in the code according to the record. instruction. 10. The component flow analysis method described in item 6 of the scope of patent application, which Page 519599 6. This step (b 1) in the scope of patent application includes the following three steps in sequence: (b 1 1) For each block for each element to be analyzed, add a two-dimensional array The parameter C yc 1 e C ount, and the initial values of all elements of Cyc 1 e C ount are set to 0, that is, CycleCountfBinCj] = 0, where 1 S i $ k, 1 S j S n, CycleC〇 unt [Bi] [Cj] is used to represent block B, using the sequence number required by component q; (b 1 2) In each block, construct the component Comp_gen set that belongs to the block, and set this The initial value of the set is set to the empty set; and (b 1 3) According to the execution order of the instructions, do the following actions for the instructions in each block &: Look up the order and The relationship between the components. Assuming that this instruction uses q components, cq timings, C2 components, CC2 timings, ..., Cn components, CCn timings, then the components with timing numbers other than 0 are added to the block's generation set, and Cy c 1 eCoun t [Bi] [C!] plus CC !, C yc 1 e C ount [Bi] [C2] white C C2, ..., C yc 1 e C Ount [] [Cn] C Cn o Π. The component flow analysis method described in item 6 of the patent application scope, wherein Step (b 2) includes the following three steps in sequence: (b 2 1) In each block, construct the component that belongs to the block into the set comp_infB ", and the component destroys the set comp — kill [Bj] Page 30 519599 VI. Scope of patent application and components leave the set comp-out [B!], The components enter the set comp—] and the component destroys the set comp — ki Π [Bi] The initial value is set to the empty set 'the component leaves the set c 0 mp __ 0 ut [The initial value of bj is set to the component generation set comp ^ gen [] of the block; (b22) Do the following for each block & (b2 2a) For each element to be analyzed q, compare the CycleCountanCj] values of all predecessors of & and take the maximum value, assuming this maximum value is CCmax, if cCmax is not 0, then decrease the value of CCmax by 1, If the value is 0, component C is added to the component elimination set comp —killfB!] In the block. 'If (CCmax-1) is greater than C yc 1 e C 〇u η η [] [C ”·] , Then set the value of CycleCountl ^ nCj] to (CCmax ~~ l), (b22b) Set the components of the block into the set c0mp_in [Bi] Set the components of the previous block of the block to leave the set c〇mp — 〇ut [Bi] Union, that is, comp-i η [] two u comp_〇ut [P], where P is the previous block of B1, (b2 2c) will The component of the block leaves the set c0mp_〇ut [I] is set as the difference between the block component entering set and the component elimination set c〇mp_kl u [h], and then the set c 〇mp — ge η is generated with the component. [] As a joint collection, also — Page 31 519599 6. The scope of patent application is comp —〇ut [Bi] = comp—gen [Bi] U (comp—infBi]-comp —killfBi]); and (b2 3) repeat step (b2 2), No changes are made until the elements of all blocks leave the collection. ^ 12: According to the component flow analysis method described in item 7 of the scope of patent application, there are three rules for determining the heading of step (a 1): (a 11) The first description of the program is a heading; U12 ) Any narrative that is a goal of conditional got or unconditional goto is a quotation; and "(al3) any goto or conditional goto The following description is a quote. 1 3 · The component flow analysis method described in item 1 of the scope of patent application, which provides corresponding sleep functions for different component hardware designs, and uses a threshold LCQnst to Determine whether to turn the component into a dormant state. 1 4 · The component flow analysis method described in item 13 of the scope of patent application, wherein if the component provides an on / off hardware design, the component is issued according to an instruction or instruction set , Cut off the supply of its power, so that the component changes from a power-consuming state to a non-power-consuming state, and the value of LCDnst is determined according to the following cost model: P (v) + SLEEP (v) ^ Lconst * ACT (v);