經濟部智慧財產局員工消費合作社印製 517275 A7 B7 五、發明説明（彳) 【發明領域】. 本發明係關於半導體積體電路，.特別是關於使用於內 藏電容器或電感器、電阻等的被動元件的半導體積體電路 的較佳裝置。 【發明背景】 【習知技藝之說明】 近年來半導體裝置中的積集化技術的進展很醒目，迄 今類比的個別零件，安裝於晶片外的電容器或電感器、電 阻等的被動元件也能內藏於晶片內。據此，將朝各種用途 的被動元件內藏於一個晶片的LSI常被開發。藉由利用這 種LSI可減少類比的零件數目，對電子機器的小型北也能 貢獻。 但是，即使說可內藏電容器或電感器、電阻等於晶片 ’惟這些被動元件若與MOS或雙載子（Bipolar)等的元件（以 下記爲MOS元件等）比較的話，具有非常大的面積，在晶片 內佔有許多空間。因此，與晶片內可大致無間隙而配置的 MOS元件等不同，每一個面積若內藏幾個大的被動元件的 話’無論如何在MOS元件等的邏輯電路與被動元件之間或 被動元件間產生間隙，此變成死空間（Dead space)產生浪費 〇 圖1係被動元件的例子，槪略地顯示內藏電容器的習知 半導體積體電路的晶片佈局之俯視圖。在圖1中，101爲1C 晶片’在其周邊部配置複數個資料（Data)輸入輸出用的銲墊 本紙張尺度適用中國國家標準（CNS ) A4規格（210^C297公釐） ---*-----衣---ΙΙΊ1--訂------- (請先閲讀背面之注意事項再填寫本頁) 517275 A7 _ B7 __ 五、發明説明（2 ) (Pad) 102。這些銲墊102係藉由銲接線（Bonding wire) 103與未 圖示的導線架（Lead frame)或印刷電路基板電性連接。 而且，在銲墊102的內側即1C晶片101的中心部存在配 置有類比電路或邏輯電路等的核心（Core)部104。配置於此 核心部104的電路包含積集化M0S電晶體或雙載子電晶體等 的非常小的元件的積集部105與附隨於此積集部105的電容 器 106。 如圖1所示除了 1C晶片101、積集部105外若也內藏電容 器106的話，在積集部105與電容器106之間等會產生不存在 任何元件或配線的死空間1 07。因此，產生到達在1C晶片 1 〇 1內無法利用的浪費空間之處，有無法有效地活用1C晶 片101所限制的空間的問題。 本發明係爲了解決這種問題所進行的，其目的爲減少 存在於1C晶片的核心區域的浪費的死空間，以可更提高半 .導體積體電路的積集度。 【發明槪要】 本發明的半導體積體電路，係具有排列有複數個銲墊 的銲墊區域與配置有電路的核心區域，其特徵爲： 在該複數個銲墊的排列上所產生的該銲墊區域的空的 空間配置被動元件。 此處，配置於該銲墊區域的空的空間之被動元件係例 如電谷益、電感或電阻的任一'個，或迫些兀件的組合。 而且，本發明的其他樣態，配置於該銲墊區域的空的 本紙張尺度適用中國國家標準（CNS ) A4規格（2%X297公釐） ϋϋ mm Bn— ·111 ml n^i _1 (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 517275 A7 B7 V. Description of the Invention (彳) [Field of the Invention] The present invention relates to semiconductor integrated circuits, and particularly to the use of built-in capacitors or inductors, resistors, etc. Preferred device of semiconductor integrated circuit of passive element. [Background of the Invention] [Explanation of the know-how] In recent years, the progress of accumulation technology in semiconductor devices has been remarkable. Individual components that have been analogized so far can also be installed in passive components such as capacitors, inductors, and resistors outside the chip. Hidden in the wafer. As a result, LSIs in which passive components for various applications are built on one chip are often developed. The use of this LSI can reduce the number of analog parts and contribute to the small size of electronic equipment. However, even if it is said that capacitors, inductors, and resistors can be built into the chip, these passive devices have a very large area when compared with devices such as MOS or bipolar (hereinafter referred to as MOS devices). Takes up a lot of space inside the wafer. Therefore, unlike MOS devices and the like that can be arranged almost without gaps in the chip, if there are several large passive devices embedded in each area, 'there will be no matter between logic circuits such as MOS devices and passive devices or between passive devices. The gap becomes a dead space. Figure 1 is an example of a passive device, which is a plan view showing a chip layout of a conventional semiconductor integrated circuit with a capacitor in it. In Figure 1, 101 is a 1C chip. A plurality of pads for data input and output are arranged on the periphery of the chip. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 ^ C297 mm) --- * ----- 衣 --- ΙΙΊ1--Order ------- (Please read the notes on the back before filling out this page) 517275 A7 _ B7 __ 5. Description of the invention (2) (Pad) 102. These pads 102 are electrically connected to a lead frame or a printed circuit board (not shown) through a bonding wire 103. Further, a core portion 104 having an analog circuit, a logic circuit, or the like is disposed inside the pad 102, that is, the center portion of the 1C wafer 101. The circuit disposed in the core portion 104 includes an accumulation portion 105 that integrates very small elements such as a MOS transistor or a bipolar transistor, and a capacitor 106 attached to the accumulation portion 105. As shown in FIG. 1, if the capacitor 106 is built in in addition to the 1C chip 101 and the accumulation section 105, a dead space 107 is generated between the accumulation section 105 and the capacitor 106 without any components or wiring. Therefore, there is a problem that a wasteful space that cannot be used in the 1C wafer 101 is reached, and there is a problem that the space limited by the 1C wafer 101 cannot be effectively used. The present invention is carried out in order to solve such a problem, and the purpose thereof is to reduce the wasted dead space existing in the core area of the 1C chip, so as to further increase the integration degree of the semiconducting volume circuit. [Summary of the invention] The semiconductor integrated circuit of the present invention has a pad region in which a plurality of pads are arranged and a core region in which the circuit is arranged, and is characterized by the following: The empty space in the pad area is configured with passive components. Here, the passive components arranged in the empty space of the pad area are, for example, any one of electric valley, inductor or resistor, or a combination of these elements. Moreover, in other aspects of the present invention, the empty paper size of the paper pad arranged in the pad area is applicable to the Chinese National Standard (CNS) A4 specification (2% X297 mm) ϋϋ mm Bn— · 111 ml n ^ i _1 (Please (Read the notes on the back before filling out this page)
、1T f 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 517275 A7 B7 五、發明説明（3 ) 空間之被動元件係在搭載於該半導'體積體電路的種種尺寸 的被動元件之中，在該空的空間的範圍儘可能大的尺寸之 被動元件。 如果依照如上述而構成的本發明，可有效地利用在將 複數個銲墊排列於半導體晶片上時所產生的空的空間，藉 由將本來配置於半導體晶片的核心區域的電容器、電感器 、電阻等的被動元件的幾個配置於此空的空間，可減少應 配置於核心區域的被動元件的數目。而且，可減少存在於 核心區域的浪費的死空間，可格外地提高半導體晶片的積 集度。 · 而且，在搭載於半導體晶片的種種尺寸的被動元件之 中，藉由將在該空的空間的範圍儘可能大的尺寸之被動元 件配置於空的空間，也能儘可能地縮小應配置於核心區域 的被動元件的尺寸。 據此’可谷易進f了混合存在由MOS或雙載子等的元件 所構成的積集部與被動元件的核心區域的電路佈局，可減 少因配置被動元件所產生的死空間。 【圖式之簡單說明】 圖1係槪略地顯示內藏電容器的習知半導體積體電路的 晶片佈局之俯視圖。 圖2係槪略地顯示利用內藏電容器的本實施形態的半_ 體積體電路的晶片佈局的一例之俯視圖。 圖3係顯示配置於空的空間的電容器的例子之圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（2」&Χ_297公釐1 — ~ ---.~~^----•衣-- (請先閲讀背面之注意事項再填寫本頁) 訂 f 517275 A7 B7 五、發明説明 圖4係槪略地顯示利用內藏電容器的本實施形態的半導 體積體電路的晶片佈局的其他例之俯視圖。 (請先閱讀背面之注意事項再填寫本頁) 圖5係槪略地顯示利用內藏電容器的本實施形態的半導. 體1貝體電路的晶片佈局的再其他例之俯視圖。 【符號說明】 1 、 20 、 101: 1C 晶片 2:資料輸入輸出用的銲墊 2 a、2 b:銲墊 經濟部智慧財產局員工消費合作社印製 3、103:銲接線 4:核心部 5:電容器 6、0a、0b:角落部 7:電源線 8a、8b:空的區域 102:銲墊 104:核心部 105:積集部 106:電容器 107:死空間 【較佳實施例之詳細說明】 以下根據圖示說明本發明的一實施形態。. 的 圖2係被動元件的例子，槪略地顯示利用內藏電容器 本紙張尺度適用中國國家標準（CNS ) A4規格（p^X297公釐） 517275 A7 B7 _ 五、發明説明（5 ) 本實施形態的.半導體積體電路的晶片佈局的一例之俯視圖 〇 (請先閱讀背面之注意事項再填寫本頁) 在圖2中1爲1C晶片，在其周邊部配置複數個資料輸入 輸出用的銲墊2。這些銲墊2係藉由銲接線3與未圖示的導線 架或印刷電路基板電性連接。 而且，在銲墊2的內側即1C晶片1的中心部存在配置有 類比電路或邏輯電路等的核心部4。配置於此核心部4的電 路至少包含積集化MOS電晶體或雙載子電晶體等的元件的 積集部（未圖示）。依照電路的內容也包含附隨於積集部的電 容器的一部分（未圖示）。而且，在核心部4的周邊電源線7係 繞核心部4一圈而配置。 如圖2所示在矩形的1C晶片1的周邊部若沿著各邊排列 複數個銲墊2的話，在1C晶片1的四角的角落部6產生空的 空間。本實施形態係利用此角落部6的空的空間，以配置本 來配置於核心部4內的電容器5的全部或一部分。 經濟部智慧財產局員工消費合作社印製 即使用的電容器5的總數少，若可將其全部配置於角落 部6的話，則將全部的電容器5配置於角落部6。據此，在核 心部4完全不配置電容器5就能完成，可僅以可高積集化的 MOS或雙載子等的元件構成核心部4。據此，可完全消除因 在核心部4配置電容器5所產生的死空間，可格外地提高1C 晶片1的積集度。 而且，當無法將電容器的全部配置於角落部6時，將其 一部分的電容器5配置於角落部6。此時，在核心部4的電路 所使用的電容器依照其用途爲由電容大的到小的各種。在 本紙張尺度適用中國國家標準（CNS ) A4規格（21&X297公釐一 517275 A7 B7 五、發明説明（e ) 這些種種尺寸.的電容器之中，最好儘可能將在角落部6的空 的空間的範圍大的電容器5配置於角落部6。 據此，不僅可減少配置於核心部4內的電容器（未圖示） 的數目，其尺寸也可當作儘可能小的。據此，可容易進行 混合存在由MOS元件等所構成的積集部與電容器的電路佈 局，可減少因配置電容器所產生的死空間，可格外地提高 1C晶片1的積集度。 本發明對於配置於角落部6的電容器5的用途並未特別 限定，惟例如可舉出如圖3(a)所示，將高頻電壓降低到接地 電位的電源的旁路電容器（By-pass condenser)、如圖3(b)所 示的振盪電路的電容器，或阻止直流成分僅用以使高頻訊 號往返的親合電容器（Coupling condenser)等。而且，將與電 感器（Inductor)—起構成的共振電路或濾波器（Filter)的電容 器、電感器或與半導體元件一起構成的阻抗（Impedance)變 換電路的電容器等配置於角落部6也可以。 將電源的旁路電容器當作角落部6的電容器5配置時， 將靠近角落部6的銲墊2a、2b當作電源用銲墊、接地用銲墊 使用較佳。據此，可縮短電源的旁路電容器5、電源供給用 的銲墊2a、2b以及電源線7間的配線長，在抑制雜訊的產生 上較佳。 當然將耦合電容器、振盪電路、共振電路、濾波器或 阻抗變換電路的電容器等當作角落部6的電容器5配置時， 藉由將與其有關的銲墊配置於靠近角落部6的銲墊2a、2b等 ，並且將相關的MOS元件等配置於核心部4內的儘可能靠 本紙張尺度適用中國國家標準（CNS ) A4規格（21gX297公釐） tmtmmmMW mmmttt «·ϋν- Μϋϋ n·—·- n mmammttm mi (請先閲讀背面之注意事項再填寫本頁) 訂 f 經濟部智慧財產局員工消費合作社印製 517275 Α7 Β7 五、發明説明（7 ) 近角落部6的位置，可縮短連接間隙的配線長。 (請先閱讀背面之注意事項再填寫本頁) 此外，圖2的例子雖然係顯示在四角的角落部6的全部 配置電容器5的樣子，惟未必需要配置於所有的角落部6， 至少配置於一個位置也可以。 而且，圖2的例子複數個銲墊2爲了整然地排列，僅在 空的空間產生1C晶片1的角落部6，惟當銲墊2不被整然地 排列，當角落部6以外有像不存在一部分銲墊2的場所時， 也能在該空的空間配置電容器5。 圖4係槪略地顯示利用本實施形態的半導體積體電路的 晶片佈局的其他例之俯視圖。此外在此圖4，圖2所示的銲 接線3以及電源線7係省略圖示。 圖4所示的半導體積體電路係在1C晶片10的周邊部雙 重地配置有資料輸入輸出用的銲墊2。而且，在配置於內側 的銲墊2的更內側即1C晶片10的中心部，存在配置有類比 電路或邏輯電路等的核心部4。 經濟部智慧財產局員工消費合作社印製 如圖4所示在矩形的1C晶片10的周邊部若沿著各邊雙 重排列複數個銲墊2的話，在1C晶片10的四角各產生兩個 空間空的角落部6a、6b。本實施形態係在此角落部6a、6b 的空的空間的每一個，配置本來配置於核心部4內的電容器 5的全部或一部分。 此外，此圖4雖然在.1C晶片1的周邊部雙重配置銲墊2 ，惟三重以上配置的情形也一樣地將電容器5配置於角落部 的空的空間的每一個。即若η重配置銲墊2的話，因在四角 的角落部產生各個η個空的空間，故在這些空的空間配置 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇^297公釐） 517275 Μ _ Β7 _ 五、發明説明（g ) 電容器5。 . (請先閱讀背面之注意事項再填寫本頁) 圖5係槪略地顯示利用本實施形態的半導體積體電路的 晶片佈局的再其他例之俯視圖。此外，在此圖5圖2所示的 銲接線3以及電源線7係省略圖示.。 圖5所示的半導體積體電路係在1C晶片20的中央部縱 一列地配置有資料輸入輸出用的銲墊2。而且，在銲墊2的 兩側存在配置有類比電路或邏輯電路等的核心部4。如此當 配置銲墊2時，在銲墊2的列的兩端部產生空間空的區域8a 、8b。本實施形態係在此空的區域8a、8b配置電容器5。 如以上幾個例子的例子所說明的，在本實施形態中有 效地利用將複數個銲墊排列於半導體晶片上時所產生的空 的空間，藉由將本來配置於半導體晶片的核心部的電容器 的幾個配置於此空的空間，可減少存在於核心部的浪費的 死空間，可格外地提高半導體晶片的積集度。 此外，以上圖2〜圖5所示的.實施形態係說明在1C晶片 的銲墊區域所產生的空的空間配置電容器的例子，惟同樣 的空的空間也能配置電感器、電阻等的其他被動元件。 經濟部智慧財產局員工消費合作社印製 本發明對於配置於空的空間的電感器或電阻等的用途 並未特別限定。電感器的用途例可舉出阻止高頻成分，與 僅用以使直流訊號往返的抗流圈電感器（Choke inductor)、 電容器一起構成的共振電路或濾波器的電感器、電容器或 與半導體元件一起構成的阻抗變換電路的電感器等。 而且，使電容器與電感器的雙方配置於銲墊區域的空 的空間也可以。例如也能將由電容器與電感器所構成的共 本紙張尺度適用中國國家標準（CNS ) A4規格（21¾¾ 297公釐） 517275 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（g ) 振電路或濾波器，或者構成阻抗變換電路的電容器與電感 器等配置於空的空間。藉由將LC共振電路或振盪電路配置 於1C晶片周圍的銲墊區域的空的空間，可儘可能地分離與 配置於核心部的類比電路等的距離，也有可減少對類比電 路的雜訊的混入之優點。 而且，配置於空的空間的電阻的用途例可舉出用以給 予電晶體或二極體等的半導體元件偏壓（Bias)的偏壓電阻、 衰減器（Attenuator)或終端器，.用以使高頻功率消耗的電阻 等。對於配置當作後者的用途的電阻於銲墊區域的空的空 間的情形，也有核心部內的半導體元件不易受到因伴隨著 功率消耗的發熱的影響之優點。 除此之外，以上所說明的實施形態任一個都只不過是 關於實施本發明的具體化的一例而已，並非據此限定地解 釋本發明的技術範圍。即本發明不脫離其精神或其主要的 特徵，可以各種形來實施。 【產業上的可利用性】 本發明係減少存在於1C晶片的核心區域的浪費的死空 間’對更提高半導體積體電路的積集度有用。 本紙張尺度適用中國國家標準（CNS ) A4規格（21衫297公釐） am·· ϋ·—^ ϋϋ mtmMmmMt a—·—— ammmMmmmmmmw ^ϋϋ m···- flu·— Bn···— uttm mi —ai^i - y νχΜΗΐ μμμμμι T 口 (請先閲讀背面之注意事項再填寫本頁)1T f Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 517275 A7 B7 Among the passive components of the size, the passive components of the size as large as possible in the empty space. According to the present invention configured as described above, an empty space generated when a plurality of pads are arranged on a semiconductor wafer can be effectively used, and a capacitor, an inductor, Disposing several passive components such as resistors in this empty space can reduce the number of passive components that should be placed in the core area. In addition, the wasteful dead space existing in the core area can be reduced, and the degree of integration of the semiconductor wafer can be significantly increased. · Among passive components of various sizes mounted on semiconductor wafers, by arranging passive components of a size as large as possible in the empty space in the empty space, it is possible to reduce the size of the passive components as much as possible. The size of the passive components in the core area. According to this, Kogujin has mixed the circuit layout of the core area of the accumulation part composed of MOS, bipolar, and other components, and the passive component, which can reduce the dead space caused by the passive component. [Brief Description of the Drawings] FIG. 1 is a plan view schematically showing a chip layout of a conventional semiconductor integrated circuit with a built-in capacitor. FIG. 2 is a plan view schematically showing an example of a chip layout of the semi-volume body circuit of the present embodiment using a built-in capacitor. FIG. 3 is a diagram showing an example of a capacitor arranged in an empty space. This paper size is applicable to Chinese National Standard (CNS) A4 specification (2 "& X_297 mm 1 — ~ ---. ~~ ^ ---- • Clothing-(Please read the precautions on the back before filling this page ) Order f 517275 A7 B7 V. Description of the invention Fig. 4 is a plan view schematically showing another example of the chip layout of the semiconductor integrated circuit of this embodiment using a built-in capacitor. (Please read the precautions on the back before filling in this (Page) FIG. 5 is a plan view schematically showing still another example of a chip layout of a body 1 circuit using a built-in capacitor according to this embodiment. [Description of Symbols] 1, 20, 101: 1C Chip 2: Pads for data input and output 2 a, 2 b: pads printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3, 103: welding wire 4: core 5: capacitor 6, 0a, 0b: corner 7: power cord 8a, 8b: empty area 102: pad 104: core 105: accumulation portion 106: capacitor 107: dead space [detailed description of the preferred embodiment] The following describes an embodiment of the present invention based on the illustration. Figure 2 is an example of a passive component, which shows the use of a built-in capacitor paper. Applicable to China National Standard (CNS) A4 specification (p ^ X297mm) 517275 A7 B7 _ V. Description of the invention (5) Top view of an example of a semiconductor integrated circuit chip layout in this embodiment. (Please read the back first Please note this page and fill in this page again.) In Fig. 2, 1 is a 1C chip, and a plurality of pads 2 for data input and output are arranged on the periphery. These pads 2 are connected by a wire 3 and a lead frame (not shown). Or the printed circuit board is electrically connected. In addition, a core portion 4 in which an analog circuit or a logic circuit is arranged is provided inside the pad 2, that is, in the center portion of the 1C wafer 1. The circuit arranged in this core portion 4 includes at least accumulation. An accumulation section (not shown) of a device such as a MOS transistor or a bipolar transistor. A part of a capacitor (not shown) accompanying the accumulation section is also included in accordance with the content of the circuit. The core section 4 The peripheral power cord 7 is arranged around the core portion 4. As shown in FIG. 2, if a plurality of pads 2 are arranged along the sides of the rectangular 1C chip 1, the corners of the four corners of the 1C chip 1 An empty space is created by the section 6. This embodiment is The empty space in the corner 6 is used to arrange all or part of the capacitors 5 originally arranged in the core 4. The total number of capacitors 5 printed and used by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is small. If all the capacitors are arranged in the corner portion 6, all the capacitors 5 are arranged in the corner portion 6. Accordingly, it can be completed without disposing the capacitor 5 in the core portion 4, and only a MOS or a biconductor capable of high accumulation can be used. Such components constitute the core portion 4. Accordingly, the dead space caused by disposing the capacitor 5 in the core portion 4 can be completely eliminated, and the degree of accumulation of the 1C chip 1 can be particularly increased. When it is not possible to dispose all the capacitors in the corner portion 6, a part of the capacitors 5 is disposed in the corner portion 6. At this time, the capacitors used in the circuit of the core section 4 are various from large to small depending on the application. In this paper scale, the Chinese National Standard (CNS) A4 specification (21 & X297 mm-1 517275 A7 B7) V. Description of the invention (e) Among the capacitors of these various sizes, it is best to keep the space in the corner 6 as much as possible. The capacitor 5 having a wide range of space is disposed in the corner portion 6. This not only reduces the number of capacitors (not shown) disposed in the core portion 4, but also reduces the size as much as possible. Accordingly, It is easy to mix the circuit layout of the accumulation section composed of the MOS element and the capacitor, which can reduce the dead space caused by the capacitor arrangement, and can increase the accumulation degree of the 1C chip 1. The invention is suitable for placement in the corner. The use of the capacitor 5 of the section 6 is not particularly limited, but examples thereof include a bypass capacitor (By-pass capacitor) for a power source that reduces a high-frequency voltage to a ground potential as shown in FIG. The capacitor of the oscillation circuit shown in (b), or a coupling capacitor that prevents direct-current components from only passing high-frequency signals back and forth. In addition, it will be a resonant circuit or filter formed with the inductor. A capacitor such as a filter, an inductor, or a capacitor of an impedance conversion circuit formed with a semiconductor element may be disposed in the corner portion 6. When a bypass capacitor of a power supply is disposed as the capacitor 5 in the corner portion 6, It is better to use the pads 2a and 2b near the corners 6 as power supply pads and grounding pads. Accordingly, the bypass capacitor 5 for the power supply, the pads 2a and 2b for the power supply, and the power cord can be shortened. The length of the wiring between 7 is better for suppressing the generation of noise. Of course, when a capacitor such as a coupling capacitor, an oscillation circuit, a resonance circuit, a filter, or an impedance conversion circuit is used as the capacitor 5 in the corner 6, the The related pads are arranged on the pads 2a, 2b, etc. near the corner portion 6, and the related MOS elements and the like are arranged in the core portion 4. As far as possible, this paper size applies the Chinese National Standard (CNS) A4 specification (21gX297). Mm) tmtmmmMWMWmtmttt «· ϋν- Μϋϋ n · — ·-n mmammttm mi (Please read the precautions on the back before filling this page) Order f Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 517 275 Α7 Β7 V. Description of the invention (7) The position near the corner 6 can shorten the wiring length of the connection gap. (Please read the precautions on the back before filling this page) In addition, the example in Figure 2 is shown in the four corners It is not necessary to arrange the capacitors 5 in all the corners 6, but at least one position may be arranged. In addition, in the example of FIG. 2, the plurality of pads 2 are arranged only in the empty space. The corner portion 6 of the 1C wafer 1 is generated in the space. However, when the pads 2 are not arranged neatly, and when there is a place other than the corner portion 6 where there is no part of the pads 2, the capacitor 5 can also be arranged in the empty space. Fig. 4 is a plan view schematically showing another example of a wafer layout using the semiconductor integrated circuit of this embodiment. Note that the welding wires 3 and the power supply wires 7 shown in FIG. 4 and FIG. 2 are not shown. The semiconductor integrated circuit shown in FIG. 4 is provided with pads 2 for data input and output in a double arrangement on the peripheral portion of the 1C wafer 10. Further, a core portion 4 in which an analog circuit, a logic circuit, or the like is arranged is located further on the inner side of the pad 2 arranged on the inner side, that is, in the center of the 1C wafer 10. As shown in FIG. 4, printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. If a plurality of pads 2 are arranged on the periphery of the rectangular 1C chip 10 along the sides, two space spaces will be generated at each corner of the 1C chip 10. Corners 6a, 6b. In this embodiment, all or part of the capacitor 5 originally arranged in the core portion 4 is arranged in each of the empty spaces of the corner portions 6a, 6b. In addition, in FIG. 4, although the pads 2 are double-arranged on the peripheral portion of the .1C wafer 1, the capacitor 5 is similarly placed in each of the empty spaces in the corners in the case of a triple or more arrangement. That is, if η re-arranges the pads 2, each η empty space is generated in the corners of the four corners. Therefore, the paper size is arranged in this empty space. The Chinese National Standard (CNS) A4 specification (21〇 ^ 297 mm) is applied. ) 517275 Μ Β7 _ V. Description of the invention (g) Capacitor 5. (Please read the precautions on the back before filling out this page.) Figure 5 is a plan view schematically showing still another example of a wafer layout using the semiconductor integrated circuit of this embodiment. It should be noted that the welding wires 3 and the power wires 7 shown in FIG. 5 and FIG. 2 are not shown here. In the semiconductor integrated circuit shown in FIG. 5, pads 2 for data input and output are arranged in a row in the center of the 1C wafer 20. Further, on both sides of the pad 2, there are core portions 4 in which analog circuits, logic circuits, and the like are arranged. When the pads 2 are arranged in this manner, space-free regions 8a and 8b are generated at both ends of the row of the pads 2. In this embodiment, the capacitors 5 are arranged in the empty areas 8a and 8b. As explained in the examples above, in this embodiment, the empty space generated when a plurality of pads are arranged on the semiconductor wafer is effectively used, and the capacitor originally arranged in the core portion of the semiconductor wafer is used. A few of these are arranged in this empty space, which can reduce the wasted dead space existing in the core portion, and can particularly increase the accumulation degree of the semiconductor wafer. In addition, the embodiment shown in FIGS. 2 to 5 above describes an example in which a capacitor is disposed in an empty space generated in a pad area of a 1C chip. However, inductors, resistors, etc. can also be disposed in the same empty space. Passive components. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The present invention is not particularly limited to the use of inductors or resistors arranged in empty spaces. Examples of the use of the inductor include an inductor, a capacitor, or a semiconductor element of a resonance circuit or a filter that is composed of a choke inductor and a capacitor that only block a high-frequency component and reciprocates a DC signal. Inductors and other components of impedance conversion circuits that are constructed together. Alternatively, both the capacitor and the inductor may be disposed in an empty space in the pad region. For example, the common paper size composed of capacitors and inductors can also be applied to the Chinese National Standard (CNS) A4 specification (21¾ to 297 mm) 517275 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (g) An oscillator circuit or a filter, or a capacitor and an inductor constituting the impedance conversion circuit are arranged in an empty space. By arranging the LC resonance circuit or the oscillation circuit in the empty space of the pad area around the 1C chip, the distance from the analog circuit arranged at the core can be separated as much as possible, and there is a possibility of reducing the noise of the analog circuit. Advantages of mixing in. Examples of uses of the resistors arranged in the empty space include a bias resistor, an attenuator, or a terminator for biasing a semiconductor element such as a transistor or a diode (Bias). Resistors that consume high frequency power. In the case where the resistor used for the latter purpose is disposed in the empty space of the pad region, there is also an advantage that the semiconductor element in the core portion is not easily affected by heat generation due to power consumption. In addition, any of the embodiments described above is merely an example of a concrete implementation of the present invention, and it is not intended to limit the technical scope of the present invention. That is, the present invention can be implemented in various forms without departing from the spirit or main characteristics thereof. [Industrial Applicability] The present invention is useful for further increasing the degree of integration of a semiconductor integrated circuit by reducing wasteful dead space existing in the core area of a 1C wafer. This paper size applies the Chinese National Standard (CNS) A4 specification (21 mm 297 mm) am ·· ϋ · — ^ ϋϋ mtmMmmMt a— · —— ammmMmmmmmmw ^ ϋϋ m ···-flu · — Bn ··· — uttm mi —ai ^ i-y νχΜΗΐ μμμμμι T mouth (Please read the precautions on the back before filling in this page)