516213 五、發明説明（1 ) 發明背景 發明領域 本發明係有關一種含有半導體基板及至少兩個電感的積 體電路。特別是，本發明係有關一種變壓器。 此外，本發明係有關一種用於製造含有半導體基板及至 少兩個電感之積體電路的方法。 相關技術說明 電感（線圏）係諸如振盪器、放大器、及混頻器之類多工 電路型式中所需要的元件。該電感係屬於其於晶片上之積 體電路會連同剩餘的電路零件產生問題的元件型式。目前 這指的是在很多例子裡仍然使用電感當作分離式元件，由 於它們會在其他情形下具有如同依合倂方式形成於晶片上 之線圈一般的缺點。在非常高的頻率也就是說其頻率落在 比1千兆赫高很多之範圍內下，由於那時會變得很難經由 各分離式線圈之引線進行信號傳輸的綠故，在任何例子裡 都必須使用合倂式電感。 例如將已知的線圈型式用在標準的CMOS製程中。於這 種製程中，使用的是具有非常低之阻抗的基板，而得到對 應的低線圈品質係數。若代替地使用高阻抗基板，則其損 耗會減少而其線圈品質係數會增加。不過，高阻抗基板可 能會在由電晶體性質構成的整體系列上具有不利的效應。 若使用的是高阻抗基板，則在任何例子裡都不再能夠使用 標準的CMOS製程，且因此必需使用不同的製程控制。不 過，這不是吾人想要的結果。 516213 五、發明説明（2 ) 用於改良其線圈品質係數的另一種可能的方法，係藉由 適用的飩刻方法以去除落在該線圈正下方的基板材料。然 後在該線圈平面與該基板之間塗覆金屬層。藉由引進各狹 縫，吾人能夠防止渦流，同時達成相對於基板的屏蔽作用 。不過，這種解決方法的缺點是少了 一個能夠取得以便用 於線圈纏繞的金屬平面。此外，只能夠在其中使線圈品質 係數達成些微的改良。 歐洲專利申請案第ΕΡ-Α-0 725 407號文件說明了 一種合 倂於微電子電路內的三維線圈，其中線圈軸係落在相對於 該晶圓表面的水平方向上。該線圈含有一或更多圈，各圈 係藉由下邊金屬化平面的互連結構以及上邊金屬化平面的 互連結構且同時經由用來連接它們的通孔接點。一般而言 ，「通孔」係被理解爲指的是兩個金屬平面之間的連接件 。於已知的解決方法中，該電感係藉著由具有更高導磁率 之材料構成之核心達成的，將該核心引進該互連結構與各 通孔接點之間而構成了這種已知解決方法的基礎特性，在 歐洲專利申請案第ΕΡ-Α-0 725 407號文件所揭示線圈幾何 的例子裡，只有很少部分的磁場會穿透到該基板之內，結 果是與這種現象有關的耗損會減小且必然地改良了該線圈 的品質係數。儘管有這種優點，截至目前爲止都未使用這 種線圈幾何。這是肇因於例如目前無法取得一種半導體相 容材料的事實。此外，在極高頻率下所有高導磁率材料都 會呈現出磁化逆轉性耗損，而這種耗損則會轉而限制該線 圈品質係數。此外，通常在使用金屬化層的例子其通孔阻 -4- 516213 五、發明説明（3 ) 抗會太高。 一種用於線圈品質或變壓器的基本規範指的是品質係數 Q。在大多數例子裡，這會定出整個電路的類比性質。對 依微電子方式合倂的變壓器而言，這種參數基本上係藉由 兩種耗損機構定義在常差的數値上。取決於該元件的操作 頻率，在核心上不是出現金屬軌跡的歐姆耗損或是由該磁 場在基板內引致的渦流。雖則於新製程中從鋁變化到銅的 金屬化作用會產生較小導體耗損的預期，然而依相反的運 作，使用具有可觀導電性的基板材料以便形成次微米電晶 體，這類電晶體會在更高頻的電路內明確地引致嚴重的渦 流耗損。這更像是指出即使對未來的製程而言也會得到具 有更差的變壓器品質係數。 爲了解決該問題，過去已提出用於切換到高阻抗基板上 的計劃。不過，這已偏離了標準製程’因此另一方面是和 較高的成本或是可觀的費用有關，或者另一方面會引致諸 如用於CMOS製程的閂鎖之類的額外問題。能夠藉由引進 含狹縫的金屬平面當作該基板正上方的屏蔽結構而在其品 質係數上達成只屬裝飾性的改良。不過，這意味著此金屬 層不再能夠用於形成變壓器。 此外，美國專利第6,008,1 02號文件說明了一種用於製 造三維線圈的方法，其中係將第一光阻層塗覆於基板上， 且於其內形成溝渠並塡充以金屬。隨後澱積第二光阻層’ 且於其內形成第一溝渠和第二溝渠並轉而塡充以金屬。隨 後塗覆第三光阻層，且於該第三光阻層內形成另一溝渠並 516213 五、發明説明（4 ) 轉而塡充以金屬。隨後將這三層光阻層去除掉，因此露出 該線圈。 美國專利第5,8 84,990號文件說明了一種用於製造二維 單件式合倂線圈的方法，其中形成了第一介電層。一種金 屬線圈係藉由將金屬引進該第第一介電層的各溝渠之內並 將該金屬結構再分割成單獨的第一金屬片段而形成的。將 第二介電層塗覆於各第一金屬片段上並將金屬塡充到該二 介電層的溝渠內，其中該金屬係透過該第二介電層內的各 通孔而與各第一金屬片段形成接觸。 歐洲專利申請案第〇 512 718 A1號文件說明了另一種含 有單件式合倂磁性元件的多層結構。 發明之扼要說明 本發明係以避免產生習知設計之缺點的目的爲基礎而提 出的。特別是，本發明的目的是提供一種具有最高可能之 品質係數而屬一般型式的元件。 根據本發明，這種目的係藉由各電感的軸基本上係沿著 平行於半導體基板上至少某一結構平面的方向延伸之事實 的優點而達成的。 此外，有利的是該積體電路的建造方式是使各電感之一 落在另一電感之內。 這使吾人能夠例如在該積體電路之內施行變壓作業。 較佳的是，各互連結構及/或各互連片段同時各通孔接 點會與該線圈的截面結合。這種截面係藉由各互連結構之 間的垂直間隔而定出的。這類長度係歸因於各導線的體電 -6- 516213 五、發明説明（5 ) 阻（bulk re si stance)而能夠在其極限之內自由選擇。必然地 ’在各對應金屬化平面上較長的導線片段下，能夠得到對 應的較大截面積。 藉由實例，用來形成線圈上某一圈或各圈的各互連結構 及/或各互連片段係配置有相互之間大槪隔了 4微米的間 隔。 在各單獨通孔元件之間所提供的各互連結構及/或各互 連片段及/或各通孔元件及/或金屬化平面上之各組成零件 ’都是有利地由銅特別是由依電解方式澱積出之銅形成的 。在使用銅時，各組成零件具有的只是很低的電阻。若使 用銅當作互連材料，形成爲由兩個或更多個通孔元件構成 之堆疊上各通孔接點的電阻也能夠維持是很低的。例如在 〇· 1 8微米技術的例子裡，這種電阻可能是3歐姆。藉由具 有η-通孔的堆疊，吾人能夠藉由並聯連接將此電阻減小爲 1/η倍。若使用具有銅的標準金屬化作業製造出該線圈， 吾人也能夠例如在施行這種方法期間以低阻抗的銅塡充位 於各金屬平面之間的垂直連接片段（各通孔元件）。 依特別有利的方式，使用的是藉由電解方法而澱積的銅 。這種銅的製造方法本質上是已知的。這種方法係說明於 例如由亞歷山大•布朗（Alexander Ε. Brown)等人發表於 1 999 年 4 月之 Semiconductor International 期刊第 5 8 頁起 標題爲「銅電鍍法（Copper Electroplating)」的論文中，在 此將這該文件所揭示的內容列爲本發明的參考文獻。 -7- 516213 五、發明説明（6 ) 各電感係依權宜方式設計成配置於晶片上及/或晶片內 的積體電路，各線圈軸係定向在相對於該基板表面的水平 方向上。這使吾人能夠減少各漏泄場穿透到該基板之內， 而引致更高的線圈品質係數。 較佳的是是將該線圈的起點和終點配置成互爲相鄰，結 果是該線圈軸會形成一種至少大槪接近的線段，特別是一 種圓形線段。這種形式的線圈軸會減少漏泄耗損，而引致 進一步改良了其線圈品質係數。特別是當該線圈軸形成大 槪呈圓形的線段時，這種幾何會允許吾人依適當方式使該 線圈受到橫向屏蔽，如同以下將隨著說明的進行參照根據 本發明的線圈系統作更詳盡的解釋。 各通孔堆疊可有利地定向在大槪垂直於該線圈軸的方向 上。 於另一精煉形式中，吾人能夠提供至少一種屏蔽平面以 便依垂直方式屏蔽該線圈。 權宜的是使微電子電路配備有交互作用式的線圈。這使 吾人能夠產生一種微電子電路，其中能夠合倂具有極高品 質係數的各線圈或各線圈系統，以致吾人也能夠在例如其 頻率落在1千兆赫以上之範圍內的極高頻率下使用這種微 電子電路。有關根據本發明之微電子電路之作業的優點、 作用、效應、及方法，同樣地係參照上述有關用來解釋根 據本發明之線圈以及根據本發明之線圈系統的全部內容， 在此將之列爲本發明的參考文獻。 該微電子電路可能有利地形成於晶片上及/或晶片內， 516213 五、發明説明（8 ) 意圖。 較佳實施例的詳細說明 第1圖顯示的是一種用來施行根據本發明之變壓器的可 能配置。在最簡單的例子裡，兩個依迴旋方式配置的金屬 互連結構都是其橫向間隔爲d而具有n圈的引線（初階及 二階線圈）。因此能夠藉由該配置的幾何設定各電感與該 線圈的耦合作用。初階線圈內的電流會產生垂直於該變壓 器平面的磁通量，該磁通量則轉而在二階線圈內誘發電壓 。這裡可以想見且已付諸實行的是各幾何變量的多樣性。 爲了減低用來設計各變壓器性質的面積需求，吾人能夠使 用許多用於三維結構的金屬層。 第1圖顯不的是一種具有兩層金屬層的變壓器，該第一 金屬層的邊界係標示爲虛線而該第二金屬層的邊界則標示 爲實線。各金屬層係藉由各通孔V而相互連接的。在所顯 示的例子裡，施行的是兩種包括各金屬軌跡的初階線圈 Ρ1和Ρ2。由較窄金屬軌跡構成的二階線圈S1到S5係顯 示於各初階線圈外側。各初階線圈的連接結構係顯示爲 ΡΑ和ΡΒ。各二階線圈的連接結構係顯示爲SΑ和SB。在 所顯示的例子裡，各線圈軸都是垂直於該半導體基板的表 面。 在CMOS技術中，能夠取得許多例如4到6個平面以便 用於電氣導線。這類金屬化結構上的重要特色不僅包括各 水平連接元件，特別是具有低阻抗的互連結構，而且也包 括各垂直連接元件，特別是也具有低阻抗的各通孔’由於 -10- 516213 五、發明説明（9 ) 這類元件同樣地係由諸如銅之類良好電氣導體構成的緣故° 第2圖顯示的是一種其線圈軸沿著平行於半導體表面特 別是矽表面方向延伸的配置。此例中，較佳的是該線圈係 包括最頂部金屬層、最底部金屬層、以及兩個由各交錯金 屬層之通孔構成的堆疊。該線圈面積係由最頂部和最底部 之互連結構以及位於該最頂部和最底部金屬化平面之間的 垂直間隔形成的。其線圈軸沿著水平方向延伸的事實指的 是明顯地減小了穿透到該基板之內的磁場強度，結果是同 樣地減少了渦流的耗損。使用屬良好電氣導體之材料特別 是銅意味著其歐姆耗損是很低的。 較佳的是該半導體基板至少在各區域內係由砂或是砂的 化合物組成的。不過，本發明在任何情況下都不會受限於 該半導體基板的材料，其他半導體材料也同樣是適用的。 同樣地本發明並不受限於特定數目的結構表面。 使用銅當作用於佈線以及用於電鍍各穿孔的材料會引致 具有極低體電阻的導線迴路。特別是對變壓器而言，那指 的是具有極低的導線耗損。爲了減少基板內的渦流耗損 ，有利的是在各金屬化平面之內施行沿水平方向以取代沿 垂直方向定其軸的線圈，由於該磁場係優勢地在該線圈核 心內且較佳的是不在該基板內受到引導。 歸因於漏泄磁場進入該基板內的低穿透性，故吾人能夠 以追種幾何形式貫現極局的線圏品質係數。用來表達具有 這種線圈幾何之電感的公式如下： L= β Ο* // r*A*N2// 此例中，μ 0指的是導磁率常數（1 ·2Ε-6Η/Μ)，而v r 發明説明（1()) 指的則是相對導磁率（在鐡磁材料的例子裡大槪是1 〇〇,〇〇〇) 。A指的是垂直於該線圈軸的線圏截面積，N指的是其圈 數，而/指的是該線圈的長度。因爲依與習知設計有關的 方式加以說明的理由，在根據本發明的線圏內省略了磁性 核心。代替的是，根據本發明的基本槪念而放大了該圏數 的截面積。在歐洲專利申請案第ΕΡ-Α-0 725 407號文件中 所說明之解決方法的例子裡，這會需要非常長的互連結構 以便在各通孔接點（金屬間介電質）的給定厚度（通常是或在 標準的金屬化結構內）爲0.5到0.3微米下實現大槪10到 20平方微米的面積。不過，這類很長的互連結構係具有對 應的極高體電阻，結果是減小了該圈數的品質係數。若代 替地選擇了較高的圈數，則其體電阻同樣地會遵照更長的 導線長度而增高。 因爲各例中各通孔接點的較佳結構具有由兩個或更多個 相互配置其上之通孔元件構成之堆疊形式的優點，吾人能 夠分別依簡單的方式增加該圈數的截面且因此改良其品質 係數。能夠藉由使用許多用來當作通孔接點的堆疊式通孔 元件而達成得效應是能夠使用標準的金屬化結構以便製造 該線圏。這意味著並非必須使用具有對應深度之通孔接點 而特別厚的過度金屬介電質以便增加其截面積。特別深之 通孔接點的製造已偏離了標準的金屬化結構且只能在特殊 製程下達成，結果是這種線圈的製造方法將會是結構上極 複雜而成本極高的。根據本發明之線圈的另一優點是能夠 以很短的互連結構達成極大的線圈截面積。 •12- 516213 五、發明説明（11) 合倂式變壓器也能夠依這種方式施行，其中各變壓器係 因爲其品質係數上的更好性質且係因爲其在所需要面積上 的效率而顯得重要。比例中，各變壓器的幾何配置可能落 在直線上，或是可能具有環狀封閉式結構，或者依需求可 能實質上具有任何必要的輪廓。在最簡單的例子裡，該初 階及二階線圈係接續座落其中。 一種具有初階及二階線圈的變壓器係表爲第3a圖。在 所顯示的例子裡，該初階線圈係含有9圏而該二階線圈係 含有1 8圈。不過，在任何情況下該配置都不會受限於所 顯示的圈數或某一特定的圈數比例。藉由交錯配置該初階 及二階線圈，吾人能夠根據第3a圖有彈性地將個別線圈 的連續圈數建造成η和m且使之呈序列配置。如是能夠相 互制定出其磁性及電氣耦合作用。 如第3b圖所示，對不對稱的變壓器而言，吾人也能夠 將二階線圈配置於初階線圈的核心內，這會引致結合有極 高耦合作用而非常有效率的面積使用狀態。依這種方式， 能夠取決於對線圈截面以及其圈數的選擇而藉由其幾何的 多樣性施行廣泛種類的電感及耦合係數。此外，磁性耦合 作用會顯著地增加，而電容性耦合作用只會在少數位置特 別是在單獨線圈部位之間的過渡區域上出現增加。 爲了減少其漏泄元件的數目，權宜的是使該變壓器的軸 形成封閉的曲線。 第4、5、和6圖顯示的是其他較佳實施例，其中的變 壓器係將二階線圈配置於初階線圈的核心內，這會引致結 -13- 516213 五、發明説明（12) 合有極高耦合作用而非常有效率的面積使用狀態。依這種 方式，能夠藉由其幾何的多樣性施行廣泛種類的電感及耦1 合係數。特別是適用的可變參數有線圈截面以及其圈數。 用以顯示一種包括落在不同金屬平面上各互連結構之線 圈的平面圖示係表爲第4圖。理論上對各金屬平面的選擇 是任意的，但是有利的是在各單獨的金屬平面之間選擇最 大可能間隔。在所顯示的例子裡，各互連結構係位於該第 一和第六金屬層內。由各通孔亦即在所顯示的例子裡的通 孔1到通孔5構成的堆疊係位於該第一與第六金屬層之間。 第4圖右手邊的副圖係用以顯不另一1種線圏的平面圖不 ，其中該線圈係由落在該第二與第五金屬層內之各互連結 構以及具有通孔2和通孔4之堆疊組成的。 第5圖係用以顯示一種變壓器的平面圖示，其中一種用 來當作二階線圈的線圈係位於初階線圈之內。 第6圖係用以顯示沿著該線圈上具有區段AB及CD之 各圈之截面圖示。 較佳的是將各電感形成爲線圈形式，各例中每一圈都是 由位於最底部金屬化平面以及最頂部金屬化平面上之各互 連結構片段或是各互連結構形成的，同時係由包括由位於 各金屬化平面之間的兩個或更多個通孔元件構成之各堆疊 而扮演著垂直連接結構角色的各通孔接點形成的。此外， 吾人能夠在該變壓器的核心內引進具有較高導磁率的材料。 該變壓器的軸不再是定向在垂直於該矽基板的方向上， 而是能夠實質上在任何必要路徑上沿水平方向引導。結果， -14- 516213 五、發明説明（13) 吾人也能夠施行具有極高圈數的線圈。此例中特別有利的 是使用一種根據習知設計的銅多重層金屬化結構。 該軸可能依封閉輪廓的形式而施行。除了各漏泄磁場之 外，所有的磁力線都會因此在其核心內受到引導。各期望 狀態係包含減小耗損且因此改良其品質係數以及該變壓器 的效率。另外，吾人能夠在該核心內使可導磁的材料。 使諸如使用各金屬化結構、具有極高阻抗的各電鍍穿4孔 、以及能夠取得極高數目的金屬層之類用於施行的技術性 預設條件獲得滿足以便用於根據本發明的各製程。 較佳的是能夠藉由CMOS製程製造出根據本發明的各線 圈幾何形式’結果是不需要額外的遮罩、膜層、或蝕刻程 序。因此能夠使各線圈的製造及很少的費用合倂到微電子 電路的製造程序之內。 gj?之說明 P1，P2 初階線圈 PA，PB 連接結構 S 1-S5 二階線圈 V 通孔 1-6 金屬層 1，〜6’ 通孔 -15-516213 V. Description of the invention (1) Background of the invention The present invention relates to an integrated circuit including a semiconductor substrate and at least two inductors. In particular, the invention relates to a transformer. In addition, the present invention relates to a method for manufacturing an integrated circuit including a semiconductor substrate and at least two inductors. Description of Related Technology Inductors (line coils) are components required in multiplexed circuit types such as oscillators, amplifiers, and mixers. This inductor is a component type whose integrated circuit on the chip will cause problems with the remaining circuit parts. This currently refers to the fact that in many cases inductors are still used as discrete components because they would otherwise have the same disadvantages as coils formed on a wafer in a combined manner. At a very high frequency, that is, its frequency falls in a range much higher than 1 GHz, because it would become difficult to transmit signals through the leads of the separate coils at that time, in any case, A combined inductor must be used. For example, known coil types are used in standard CMOS processes. In this process, a substrate with a very low impedance is used, and a corresponding low coil quality factor is obtained. If a high-impedance substrate is used instead, its loss will decrease and its coil quality factor will increase. However, high-impedance substrates may have an adverse effect on the entire family of transistor properties. If a high-impedance substrate is used, the standard CMOS process can no longer be used in any case, and therefore a different process control must be used. However, this is not the result I want. 516213 V. Description of the invention (2) Another possible method for improving the coil quality factor is to remove the substrate material falling directly under the coil by an appropriate engraving method. A metal layer is then applied between the coil plane and the substrate. By introducing the slits, we can prevent eddy currents while achieving a shielding effect against the substrate. However, the disadvantage of this solution is that there is one less metal plane that can be obtained for coil winding. In addition, only a slight improvement in the coil quality factor can be achieved therein. European Patent Application No. EP-A-0 725 407 describes a three-dimensional coil incorporated in a microelectronic circuit, in which the coil axis falls in a horizontal direction relative to the surface of the wafer. The coil contains one or more turns, each turn being through the interconnect structure of the lower metallized plane and the interconnect structure of the upper metallized plane and at the same time via via contacts used to connect them. Generally speaking, "through-hole" is understood to mean the connection between two metal planes. In the known solution, the inductance is achieved by a core made of a material having a higher magnetic permeability, and the core is introduced between the interconnect structure and the through-hole contacts to form this known The basic characteristics of the solution, in the example of the coil geometry disclosed in European Patent Application No. EP-A-0 725 407, only a small part of the magnetic field will penetrate into the substrate, and the result is related to this phenomenon The associated losses are reduced and the quality factor of the coil is necessarily improved. Despite this advantage, this coil geometry has not been used so far. This is due to, for example, the fact that a semiconductor-compatible material is currently not available. In addition, all high-permeability materials exhibit magnetization-reversing losses at extremely high frequencies, and this loss in turn limits the coil quality factor. In addition, in the case of using a metallization layer, its through-hole resistance is usually -4- 516213 V. Description of the invention (3) The impedance will be too high. A basic specification for coil quality or transformers refers to the quality factor Q. In most cases, this will determine the analog nature of the entire circuit. For microelectronically integrated transformers, this parameter is basically defined on the constant difference number by two loss mechanisms. Depending on the operating frequency of the element, there is no ohmic loss of metal tracks on the core or eddy currents caused by the magnetic field in the substrate. Although the metallization from aluminum to copper in the new process will produce less conductor loss, according to the opposite operation, a substrate material with considerable conductivity is used to form a sub-micron transistor. Higher frequency circuits clearly cause severe eddy current losses. This is more like pointing out that even for future processes, a worse transformer quality factor will be obtained. To solve this problem, plans for switching to a high-impedance substrate have been proposed in the past. However, this has deviated from the standard process' and is therefore related to higher or considerable costs on the other hand, or it may cause additional problems such as latches for CMOS processes. By introducing a metal plane with a slit as a shielding structure directly above the substrate, it is possible to achieve only decorative improvements in its coefficient of quality. However, this means that this metal layer can no longer be used to form a transformer. In addition, U.S. Patent No. 6,008,102 describes a method for manufacturing a three-dimensional coil in which a first photoresist layer is coated on a substrate, and a trench is formed therein and filled with metal. Subsequently, a second photoresist layer is deposited and a first trench and a second trench are formed therein and are then filled with metal. Subsequently, a third photoresist layer is coated, and another trench is formed in the third photoresist layer and 516213 V. Description of the invention (4) Instead, it is filled with metal. These three photoresist layers are subsequently removed, thus exposing the coil. U.S. Patent No. 5,8,84,990 describes a method for manufacturing a two-dimensional one-piece closed loop coil in which a first dielectric layer is formed. A metal coil is formed by introducing a metal into each trench of the first dielectric layer and dividing the metal structure into separate first metal segments. A second dielectric layer is coated on each first metal segment and a metal is filled into the trenches of the two dielectric layers, wherein the metal is connected to each of the first dielectric layers through the through holes in the second dielectric layer. A metal segment makes contact. European Patent Application No. 0 512 718 A1 describes another multilayer structure containing a single-piece, combined magnetic element. SUMMARY OF THE INVENTION The present invention is based on the purpose of avoiding the disadvantages of conventional designs. In particular, the object of the present invention is to provide a component of a general type having the highest possible quality factor. According to the invention, this object is achieved by the advantage of the fact that the axis of each inductor extends substantially in a direction parallel to at least a certain structural plane on the semiconductor substrate. In addition, it is advantageous that the integrated circuit is constructed in such a way that one of the inductors falls within the other inductor. This enables us to perform, for example, a transformer operation within the integrated circuit. Preferably, each interconnect structure and / or each interconnect segment at the same time each through-hole contact is combined with the cross section of the coil. This cross section is determined by the vertical spacing between the interconnect structures. This type of length is attributed to the bulk electric of each wire -6-516213 V. Invention description (5) Resistance (bulk re s stance) can be freely selected within its limits. Inevitably, a corresponding larger cross-sectional area can be obtained with a longer wire segment on each corresponding metallization plane. By way of example, the interconnect structures and / or interconnect segments used to form one or more turns on a coil are configured with a 4 micron gap between them. The interconnect structures and / or interconnect segments provided between the individual via elements and / or the via elements and / or the component parts on the metallized plane are advantageously made of copper, in particular by Formed by electrolytically deposited copper. When using copper, each component has only a very low resistance. If copper is used as the interconnection material, the resistance of each via contact formed in a stack made of two or more via elements can also be kept low. For example, in the case of the 0.18 micron technology, this resistance may be 3 ohms. By stacking with η-through holes, we can reduce this resistance to 1 / η times by connecting in parallel. If the coil is manufactured using a standard metallization operation with copper, we can also fill the vertical connection segments (through-hole elements) between the metal planes with low-impedance copper cymbals during this method, for example. In a particularly advantageous manner, copper deposited by electrolytic methods is used. This method of producing copper is known per se. This method is described, for example, in papers entitled "Copper Electroplating" published by Alexander E. Brown and others in the April 1999 issue of Semiconductor International, page 58, The disclosure of this document is hereby incorporated by reference. -7-516213 V. Description of the invention (6) Each inductor is designed as an integrated circuit arranged on the wafer and / or in the wafer according to an expedient manner, and the axis of each coil is oriented in a horizontal direction relative to the surface of the substrate. This allows us to reduce the penetration of each leakage field into the substrate, resulting in a higher coil quality factor. It is preferable to arrange the start point and the end point of the coil to be adjacent to each other. As a result, the coil axis will form a line segment that is at least close to each other, especially a circular line segment. This form of coil shaft will reduce leakage loss, which will further improve its coil quality factor. Especially when the coil shaft forms a large circular line segment, this geometry will allow us to shield the coil laterally in an appropriate manner, as will be explained in more detail below with reference to the coil system according to the present invention explanation of. The through-hole stacks can advantageously be oriented in a direction where the large ridge is perpendicular to the coil axis. In another refinement, we can provide at least one shielding plane to shield the coil in a vertical manner. It is expedient to equip the microelectronic circuit with an interactive coil. This enables us to produce a microelectronic circuit in which coils or coil systems with extremely high quality coefficients can be combined, so that we can also use them at very high frequencies, for example, whose frequency falls above 1 GHz This microelectronic circuit. Regarding the advantages, functions, effects, and methods of the operation of the microelectronic circuit according to the present invention, reference is also made to the above-mentioned entire contents for explaining the coil according to the present invention and the coil system according to the present invention. This is a reference for the present invention. The microelectronic circuit may advantageously be formed on and / or within the wafer, 516213 V. Description of the Invention (8) Intent. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 shows a possible arrangement for implementing a transformer according to the invention. In the simplest example, two metal interconnects configured in a convolutional manner have leads (native and second-order coils) with n turns at a lateral spacing of d. Therefore, the coupling effect of each inductor and the coil can be set by the configuration geometry. The current in the primary coil produces a magnetic flux perpendicular to the transformer plane, which in turn induces a voltage in the secondary coil. What can be imagined here and put into practice is the diversity of various geometric variables. In order to reduce the area requirements for designing the properties of each transformer, we can use many metal layers for three-dimensional structures. Figure 1 does not show a transformer with two metal layers. The boundary of the first metal layer is marked by a dashed line and the boundary of the second metal layer is marked by a solid line. The metal layers are connected to each other through the through holes V. In the example shown, two primary coils P1 and P2 are implemented which include individual metal tracks. The second-order coils S1 to S5 composed of narrower metal tracks are displayed on the outside of each of the first-order coils. The connection structure of each primary coil is shown as PA and PB. The connection structure of each second-order coil is shown as SA and SB. In the example shown, each coil axis is perpendicular to the surface of the semiconductor substrate. In CMOS technology, many, for example, 4 to 6 planes can be obtained for electrical wiring. Important features on this type of metallized structure include not only horizontal connection elements, especially interconnect structures with low impedance, but also vertical connection elements, especially vias that also have low impedance. 5. Description of the invention (9) This type of component is also composed of a good electrical conductor such as copper. Figure 2 shows a configuration in which the coil axis extends parallel to the semiconductor surface, especially the silicon surface. In this example, it is preferred that the coil system includes a topmost metal layer, a bottommost metal layer, and a stack of two through-holes of each staggered metal layer. The coil area is formed by the topmost and bottommost interconnect structures and the vertical spacing between the topmost and bottommost metallization planes. The fact that its coil axis extends in the horizontal direction means that the strength of the magnetic field penetrating into the substrate is significantly reduced, and as a result, the eddy current loss is also reduced. The use of materials that are good electrical conductors, especially copper, means that their ohmic losses are very low. Preferably, the semiconductor substrate is composed of sand or a sand compound at least in each region. However, the present invention is not limited to the material of the semiconductor substrate in any case, and other semiconductor materials are also applicable. Likewise, the invention is not limited to a specific number of structural surfaces. The use of copper as a material for wiring and for plating perforations results in wire loops with extremely low bulk resistance. Especially for transformers, that means extremely low wire losses. In order to reduce the eddy current loss in the substrate, it is advantageous to implement a horizontal direction within each metallization plane to replace the coil whose axis is oriented in the vertical direction, because the magnetic field is advantageously in the core of the coil and preferably not The substrate is guided inside. Due to the low permeability of the leaked magnetic field into the substrate, we can realize the extreme line quality coefficient in a retrospective geometric form. The formula used to express the inductance with this coil geometry is as follows: L = β Ο * // r * A * N2 // In this example, μ 0 refers to the permeability constant (1 · 2E-6Η / Μ), The vr invention description (1 ()) refers to the relative magnetic permeability (in the case of a magnetic material, 槪 is 10,000,00). A refers to the cross-sectional area of the line perpendicular to the coil axis, N refers to the number of turns, and / refers to the length of the coil. For reasons explained in a manner related to the conventional design, the magnetic core is omitted in the coil according to the present invention. Instead, the cross-sectional area of this unit is enlarged according to the basic idea of the present invention. In the example of the solution described in European Patent Application No. EP-A-0 725 407, this would require a very long interconnect structure in order to give the via contacts (intermetal dielectric) a given Achieves an area of 10 to 20 square microns in thickness (typically or within a standard metallized structure) of 0.5 to 0.3 microns. However, this type of very long interconnect structure has a correspondingly high bulk resistance, with the result that the quality factor of the number of turns is reduced. If a higher number of turns is chosen instead, its bulk resistance will also increase in accordance with a longer wire length. Because the preferred structure of each through-hole contact in each case has the advantage of a stacked form consisting of two or more through-hole elements arranged on top of each other, we can increase the cross section of the number of turns in a simple manner, and Therefore, its quality factor is improved. The effect that can be achieved by using many stacked through-hole components used as through-hole contacts is the ability to use standard metallization structures to make the coil. This means that it is not necessary to use an excessively thick metal dielectric with through hole contacts of corresponding depth in order to increase its cross-sectional area. The manufacture of particularly deep through-hole contacts has deviated from the standard metallization structure and can only be achieved under special processes. As a result, the manufacturing method of this coil will be extremely complicated and costly. Another advantage of the coil according to the present invention is that it can achieve a very large coil cross-sectional area with a short interconnect structure. • 12-516213 V. Description of the invention (11) Combined transformers can also be implemented in this way, where each transformer is important because of its better quality coefficient of quality and because of its efficiency in the required area . In the proportion, the geometric configuration of each transformer may fall on a straight line, or it may have a ring-shaped closed structure, or it may have substantially any necessary contour as required. In the simplest case, the primary and secondary coil systems are located one after the other. A transformer system with primary and secondary coils is shown in Figure 3a. In the example shown, the primary coil system contains 9 圏 and the secondary coil system contains 18 turns. However, in any case this configuration is not limited by the number of turns displayed or a specific number of turns. By staggering the arrangement of the primary and secondary coils, we can elastically build the continuous turns of individual coils into η and m according to Fig. 3a and arrange them in sequence. If it is possible to formulate their magnetic and electrical coupling effects. As shown in Figure 3b, for asymmetric transformers, we can also arrange the second-order coil in the core of the first-order coil, which will lead to a very efficient area use state combined with extremely high coupling. In this way, depending on the choice of the coil cross section and the number of turns, a wide variety of inductances and coupling coefficients can be implemented with its geometric diversity. In addition, the magnetic coupling effect increases significantly, while the capacitive coupling effect increases only in a few positions, especially in the transition area between the individual coil parts. In order to reduce the number of leakage elements, it is expedient to form a closed curve of the transformer shaft. Figures 4, 5, and 6 show other preferred embodiments, in which the transformer is configured with a second-order coil in the core of the first-order coil, which results in the results of -13-516213 5. Description of the invention (12) High coupling effect and very efficient area use. In this way, a wide variety of inductances and coupling coefficients can be implemented with its geometric diversity. Particularly applicable variable parameters are the coil cross section and its number of turns. The plan view used to show a type of coil that includes interconnect structures falling on different metal planes is shown in Figure 4. The choice of each metal plane is theoretically arbitrary, but it is advantageous to choose the largest possible interval between the individual metal planes. In the example shown, interconnect structures are located within the first and sixth metal layers. A stack of vias, that is, vias 1 to 5 in the example shown, is located between the first and sixth metal layers. The auxiliary drawing on the right-hand side of FIG. 4 is a plan view showing another type of line coil, wherein the coil is formed by interconnect structures falling in the second and fifth metal layers and having through holes 2 and The stack of through holes 4 is formed. Fig. 5 is a plan view showing a transformer in which a coil system used as a second-order coil is located inside the first-order coil. Fig. 6 is a cross-sectional view showing each circle along the coil having sections AB and CD. It is preferable to form each inductor in the form of a coil, and in each case, each turn is formed by each interconnecting structure segment or interconnecting structure located on the bottommost metallized plane and the topmost metallized plane. It is formed by each through-hole contact including a stack of two or more through-hole elements located between the metallization planes and playing a role of a vertical connection structure. In addition, we can introduce materials with higher magnetic permeability into the core of this transformer. The axis of the transformer is no longer oriented in a direction perpendicular to the silicon substrate, but can be guided in a horizontal direction on virtually any necessary path. As a result, -14-516213 V. Description of the invention (13) We can also implement coils with extremely high turns. It is particularly advantageous in this case to use a conventional copper multi-layer metallization structure. The axis may be implemented in the form of a closed contour. With the exception of each leaking magnetic field, all magnetic lines of force are guided within its core. Each desired state involves reducing losses and thus improving its coefficient of quality and the efficiency of the transformer. In addition, we can make magnetically permeable materials in this core. Satisfying technically preset conditions for implementation, such as the use of metallized structures, 4 holes for each plating with extremely high resistance, and the ability to obtain a very high number of metal layers for use in processes according to the present invention . It is preferred that the coil geometries according to the present invention can be fabricated by a CMOS process. As a result, no additional masks, films, or etching processes are required. Therefore, it is possible to integrate the manufacturing of each coil with a small cost into the manufacturing process of the microelectronic circuit. Description of gj? P1, P2 primary coil PA, PB connection structure S 1-S5 secondary coil V through hole 1-6 metal layer 1, ~ 6 ’through hole -15-