TW515048B - Asymmetric high voltage metal-oxide-semiconductor device - Google Patents

Abstract

In accordance with the present invention, a structure of an asymmetric high-voltage MOS device is disclosed. The key aspect of the present invention is a high-voltage MOS device having a drift region underneath an isolation structure, wherein the high-voltage MOS device is isolated by shallow trench isolations and formed on a silicon-on-insulator (SOI) substrate. The asymmetric high-voltage MOS device comprises a substrate having an insulating layer thereon and a semiconductor layer of a first conductive type on the insulating layer. A plurality of shallow trench isolations defining an active area is formed in the semiconductor layer. A field oxide layer is formed in the active area of the semiconductor layer. A drift region of a second conductive type is formed under the field oxide layer in the semiconductor layer. A gate structure including a conductive layer and a gate dielectric layer is formed on the semiconductor layer in the active area and covers a portion of the field oxide layer. A first source and drain regions of the second conductive type having a first dopant concentration are formed opposite to each other aside of the gate structure in the semiconductor layer in the active area, wherein the first drain region is isolated from the gate structure by the field oxide layer. A second source and drain regions of the second conductive type having a second dopant concentration are formed in the first source region and the first drain region respectively, wherein the second dopant concentration is higher than the first dopant concentration.

Description

515048 V. Description of the invention (1) 5 -1 Field of invention: The present invention relates to an asymmetric high-voltage metal-oxide semiconductor device (HV M0S), and in particular to an asymmetric high-voltage double-doped diffusion (double-doped diffusion). ) Metal-oxide semiconductor device (hv DM0S), which is formed on the insulating layer with a substrate of Shi Xi (SOI) and uses shallow trench isolation technology to isolate the component to reduce the size of the component and reduce the substrate current. 5-2 Background of the Invention: When the gold oxide is continuously reduced to the strength of the metal oxide semiconductor, the electron borrowing energy in the channel will occur very high. Reverse-b generates many holes and substrates that are too large for the substrate, for example, the fabrication of electronic semiconductor devices is more and more dense, and the channel length is also the same, which makes the operation speed continue to accelerate. However, When the voltage of the applied body element is unchanged, and the channel length is shortened, the electric field is increased. As a result, when the electric field strength is increased, the energy obtained by accelerating with a higher electric field is increased, and the electrons are collapsed ( Electrical breakdown) is likely to occur when the drain voltage is too large, so that the electric field of the drain / substrate junction of the reverse bias i ased is accelerated by the electrons produced by electron-hole pairs in the vicinity of the junction. -Ionization impact of the electric lattice produces a very large substrate current, and the current has many destructive effects on the operation of high voltage components into junction breakdown and lateral double carrier (BJT) snapback voltage down) 〇

Page 7 Directional electricity without factors, areas, widely surrounded by micro-doping, reducing access to the source, generating complex metal oxides, and generating electricity, usually because of this, the combined field / dimer semiconductors in the drain region are used to collapse. Since the half caused a high resolution area, the purpose is strength. Regional

Subconductor conductor elements must be able to withstand high concentrations of performance that are not easily shaped. The same conductors have slightly doped regions in the impervious regions and make them usually work. However, the drain voltage collapses the voltage / drain a kind of now doped region. The formation of a light bit, and further the disadvantage is that it will benefit from the low-voltage components. The voltage element conductor substrate voltage element channel is formed to reduce the high electricity for absorption. However, the size increases significantly into two joints and shallow. Source rate decreases. The body of the part of the electric hybrid technology of the lightly jointed electric field is based on the traditional South Voltage Gold Oxygen Molybdenum-Isolation Technology (L0C0S). One piece of 70 pieces is made of regional oxygen to obtain a higher joint collapse. Voltage, thermal factor? Dagger-shaped Difficult. In addition, the area with reduced size = faced with the technology of reducing the element size of the adjacent active area in the semiconductor device, which will reduce the reliability problem when @@ is reduced. Therefore, the effective isolation distance, and therefore the size is greatly reduced, x can eliminate the bottom 5 has a high junction breakdown voltage and path can be eliminated to a minimum of high electrical oxygen ^ substrate (substrate current. To the milk + conductor components is expected 5-3 Invention Purpose and Overview:

515048 V. Description of the invention (3) In view of the various metal-oxygen semiconductor devices produced above, formed in a partition. Isolating the semiconductor device can obtain a more bipolar oxygen-semiconductor semiconductor. Therefore, it is obtained that the present invention exhibits many disadvantages, such as the background of the invention, and the device element. The insulation layer of this hair is under the structure of Shi Xi, and uses. Utilize shallow trenches for high junction breakdowns. Fast junction crystals are formed in the insulation. With the improvement of high voltage, for example, the junction (k i n k) is full of traditional, clear and focused substrates. Shallow trenches are used to isolate the superior voltage. On the bottom layer of the voltage drop, there are the electric fields and regions of the silicon oxide semiconductor device. High-voltage metal-oxide semiconductors provide a non-corresponding one-point-voltage metal-oxide semiconductor, which has the advantages of being away from the technical point, the material current (SOI), the body element, and the current voltage.

Isolation of South China Power in a drift zone requires sacrificing element bonding and collapse. The reliability curve can be due to the high substrate. _ It is provided that a south electric edge layer is on a first substrate, a trench isolation active region, a drift region with an area under the asymmetric high-voltage metal-oxide semiconductor substrate described above and a semiconductor type. The foregoing is, for example, formed in a semiconductor domain. Field oxidation in a p-type silicon layer of a second conductor type. Purpose, in a preferred embodiment, the present invention enhances the structure of a metal-oxide semiconductor device. A non-pairing component includes a substrate, and the substrate has an insulating conductor layer on the insulating layer, wherein the semiconductor layer with the substrate may be an insulating layer with Shi Xi ($ 〇I) on the layer with P-type silicon Substrate of the layer. Within a plurality of shallow trench layers, where a plurality of shallow trench isolation definitions are defined—area is formed in the semiconductor layer under the oxidized area on the semiconductor layer of the active area, which is drifted; for example, an N-type drift region is formed in a field oxygen-gate structure Semiconducting

D1DUHO V. Description of the invention (4) The body layer is formed to cover an inter-dielectric layer and ... domain ... at least the enclosing structure is formed to face each other. —Semi-source region and -th-drain (for example, p-type stone layer), the semiconductor layer of the active region on the side of the '= f 2 structure ^-it ^ (', the first source region and the first One drain region is a conductor type (such as N-in, one LH, used to isolate the gate structure; two clutter, and the field oxidation region is the second drain region.-The source region and -, Straight-$ hr; in the source region and the first drain region type) and-the second doped G region has a second conductor type (for example, N is higher. Moreover, the concentration of the first doping is higher than First Doping Concentration 5-4 Detailed Description of the Invention Some embodiments of the present invention will be described in detail as follows. In addition to the above, the present invention can also be widely implemented in other embodiments: Examples: The scope of the present invention is not limited, and Subject to the scope of the following patents. The present invention provides an asymmetric high voltage. According to a preferred embodiment of the present invention, the first a / two body and two cows: the production of asymmetric high voltage metal-oxide semiconductor device .As described in the first asymmetric high-voltage metal-oxide semiconductor device 10 (), the package m has an insulating layer U0 at the bottom. On 1G1 and-on the half 1G edge layer U0, where the semiconductor layer 112 has one: shallow trench isolation (STI) 114 is formed in the semiconductor layer 112, J 515048 5. Description of the invention (5) trench isolation 11 4 definition An active region 丨 6. A field of oxidized region 1 2 0 forms a semiconductor layer 112 of a movable region 116. A drift region 118 is formed in the semiconductor layer 丨 2 below the substrate region 1 2 0, among which the drift region 1 1 8 with a second conductor type. A gate structure 122 is formed on the semiconductor layer 1 12 of the active area 116 to cover a part of the field oxidation area 丨 2 〇, wherein the gate structure 122 includes at least a gate dielectric Layer 124 and a conductor layer 126. The first source region 1 2 8 and the first drain region 丨 3 are formed opposite to each other in the gate structure 丨 2 2 in the semiconductor layer 1 12 of the active region 1 16 on the side, where The first source region 128g and the first drain region 130 have a second conductor type and a first doping concentration, and the% oxidation region 1 2 0 is used to isolate the gate structure 丨 2 2 from the first drain region 1 3 ◦ The second source region 1 3 2 and the second drain region 1 3 4 are formed in the first source region, respectively. 1 2 8 and the first drain region 130, wherein the second source region 13 2+ and the second drain region 134 have a second conductor type and a second doping concentration, and the second doping concentration is smaller than The first doping concentration is high.

... 苐 A to D are cross-sectional views of various stages of the present invention in forming an asymmetric high voltage according to a preferred embodiment. Referring to the first A diagram, a substrate 101 has an insulating layer on the substrate and a semiconductor layer 112 on the insulating layer no. The semiconductor layer 112 has a first conductor type. The structure of the substrate 101 may be a substrate structure having silicon (s〇 丨) on the insulating layer, that is, the semiconductor layer 112 is a silicon layer having a first conductor type, for example? Type = layer = on an insulating layer such as a silicon oxide layer. One of the key points of the present invention is that the asymmetric 冋 voltage metal-oxide semiconductor element is formed on a substrate with silicon on the insulating layer, so it can block the current path of the substrate and avoid joint collapse and lateral double-layering.

Page 11 V. Description of the invention (6) ___ Sub-junction transistor (BJT) rapid pressure, — ST " Π4 is formed in, for example, a p-type stone evening ^ shallow trench isolation (active area 11 6 'and use plural: 2 U 2 Here, the purpose of defining the junction breakdown voltage between one plus 7L pieces is to increase the size of the symmetrical metal-oxide semiconductor device: a few pieces in size. In other words, in the active region 4 of the non-type semiconductor layer, for example, p-type The silicon layer has a first conductor element. The current technology formation and use of shallow trench isolation technology to isolate the trench isolation pattern to the semiconductor at least two steps include at least, transferring shallow to form shallow trench isolation. Product ,,, Bar,, The material in the semiconductor layer is shown in Figure 1B, and the silicon layer 220 is sequentially in the semiconductor; n ^ engraved 塾 oxide layer 210 and nitride: conductor layer-. "The first type of drift region 118 is in the exposed half Taking the formation of the second conductor stone layer as an example, N-type ion implantation is performed in iH2, that is, P-type P-type silicon layer. After narrowing, ^ to form an N-type drift region and expose 120 to Semiconductor layer u'2 ,, =; ^ formation process to form field oxidation The area extension element drain and field oxidation regions are used to enhance the junction breakdown. The smoothing of the interface is said to be the "field oxidation region reduction. Closed: = two halves" on the body layer, and is formed in the active region 11β pole structure 122 It contains at least one or two :; P: field oxidation region 120, in which the steps of the gate electrode structure are not included? On the conductor layer, and then the two dielectric layers and the conductor layer are defined to form a semi-conductive gate. Photoresistance of Pattern Transfer of Pole Structure on Conductor 第 12 页

V. Description of the invention (8) = $ 体 7 °: Including,-the substrate has-an insulating layer and a p-type stone dwelling knife ^ Ϊ. A plurality of shallow trench isolations are formed in P-type silicon; inner basin 221: Definition of shallow trench isolations-main Gangxi ^ p-type stone layer under the field f = type II drift region is formed on the field oxidation area, A p-type silicon layer covering a portion of the field nf, a p-type silicon layer formed in the active region, and a lightly doped N-type drain region region // a p-type silicon layer in the active region of a doped N-type source region ;: U pairs are formed on the side structure of the gate structure and the lightly doped N-type drain region and the oxide region are used to isolate the gate junction ytterbium-type drain region. Two-heavy doped N-type source region and- Within the heavily doped drain region. == The micro-doped N-type source region and the slightly N-type drain region are used as high potentials; 妾 Ϊ :: The source region and the slightly doped layer are in contact. The barrier can be joined, and it can also be insulated with the above. It is only for the present invention that the scope of the patent application for the present invention is applied; the examples are implemented and 6 'is not intended to limit the equivalent changes made in the spirit. It does not depart from the patent disclosed in the present invention Within range. ^ b ornaments should be included in the following application 515048 diagrams to briefly explain the purpose, characteristics and advantages of the present invention can be clearly seen from the following detailed description and the description of the drawings: The first A is the shallow trench isolation of the present invention A cross-sectional view formed on a semiconductor layer; FIG. 1B is a cross-sectional view of the ion implantation drift region of the present invention in the semiconductor layer; FIG. C is a first source region and a first drain of the ion implantation of the present invention. A cross-sectional view of a region in a semiconductor layer; and a first D diagram is a cross-sectional view of a second source region and a second drain region of the ion implantation in the semiconductor layer of the present invention. Representative symbols of main parts: 100 high-voltage metal-oxide-semiconductor element 101 substrate 110 insulating layer 11 2 semiconductor layer 114 shallow trench isolation 116 active region 118 drift region 1 2 0 field oxidation region

Page 15 515048 Brief description of the diagram 122 Gate structure 124 Gate dielectric layer 126 Conductor layer 128 First source region 130 First drain region 132 Second source region 134 Second non-polar region 210 Pad oxide layer 220 Nitrogen Siliconized layer 230 First ion implantation 232 Second ion implantation 234 Third ion implantation

Page 16

Claims (1)

515048 6. Scope of patent application1. A high-electricity-substrate layer is separated from the shallow trenches of the insulation by a field of oxygen-drift, wherein the drift is a pole cover part of the first gold metal oxide 'on the bottom layer. The shallow trench isolation region defines a region-shaped region with a structure-shaped field oxidation source region semiconductor element, including: a material having an insulating layer on the substrate and a semiconductor, wherein the semiconductor layer has a first conductor type; and an isolation is formed on the material. In the semiconductor layer, wherein the plurality of active regions are formed on the semiconductor layer in the active region; in the semiconductor layer under the field oxidation region, the body shape; on the semiconductor layer in the dynamic region, a first The source region and the first concentration at the sides of the two-conductor gate structure, and the region; and formed in the main region; the region and a first active region non-polar region field oxidation region are used for a second source region and A first doped region having the second conductor source region and the second drain region has a doping concentration that is greater than the first doping and a drain region formed opposite each other in the Within the semiconductor layer, wherein the first conductor type and a first doping isolate the gate structure and the first drain-drain region from being formed in the first, respectively, wherein the second source The polar region, the type and a second doping concentration, and the degree is high. 2. As the element in the scope of patent application, the above substrate is a substrate with Shi Xi (S 0 I) on the insulating layer. 3. The element according to item 2 of the scope of patent application, wherein the semiconductor is formed as described above. Page 17 515048 6. Scope of patent application The layer is a P-type layer. 4. The element according to item 3 of the scope of patent application, wherein the drift region formed with the second conductor type is an N-type drift region. 5. For the device according to item 3 of the patent application, wherein the first source region and the first drain region are a lightly doped N-type source region and a lightly doped N-type drain region. 6. For the device according to item 3 of the patent application, wherein the second source region and the second drain region are a heavily doped N-type source region and a heavily doped N-type > and a polar region. Please refer to the special and special gates for the first and second layers as in package 7. The item layer body with few pieces of elements leads to the structured pole gate. 8. If the element of the scope of patent application for item 1 is mentioned above, The first source region and the first drain region are in contact with the insulating layer. 9. A high-voltage metal-oxide semiconductor device comprising: a substrate having silicon (SOI) on a P-type insulating layer; the substrate having silicon on the P-type insulating layer having an insulating layer and a P-type silicon layer; On the insulation layer; a plurality of shallow trench isolations are formed in the P-type silicon layer, wherein the plurality of shallow trench isolations define an active area; Page 18 6. The scope of patent application Field formation area is formed on the p-type stone layer in the active area; t coffee shift area is formed on the p-type stone layer under the field oxidation area-the leisure pole structure is formed in the active area On the P-type stone layer, a part of the field oxidation region is frosted; a lightly doped N-type source region and / or a lightly doped N-type drain region are formed opposite to each other on the active side of the gate structure Within the P-type silicon layer of the region, and the field oxidation region is used to isolate the gate structure from the lightly doped N-type electrodeless region; and A heavily doped N-type source region and a heavily doped N-type drain region are formed in the lightly doped N-type source region and the lightly doped v-type drain region, respectively. -I 0 · The element according to item 9 of the scope of patent application, wherein the gate structure mentioned above includes at least a gate dielectric layer and a conductor layer. II. The device according to item 9 of the patent application, wherein the lightly doped 1 ^ -type source region and the lightly doped N-type drain region are in contact with the insulating layer. See 12. — A high-voltage metal-oxide semiconductor device, comprising a substrate with silicon (S0I) on an N-type insulating layer, and a substrate with Shi Xi on the v-type insulating layer having an insulating layer and an N-type A silicon layer is formed on the insulating layer; a plurality of shallow trench isolations are formed in the N-type stone layer, wherein the plurality of shallow trench isolations define an active area; Page 19 Μ 5048 6. Scope of Patent Application—The N-type silicon screen with a field oxidation region formed in the active region; and a P-type drift region with a gate structure formed in the active silicon region. On the N-type silicon layer in the region, a part of the field oxidation region; a lightly doped P-type source region and a lightly doped P-type drain region are formed opposite to each other on the active side of the gate structure Region of the N-type stone layer and the field oxidation region is used to isolate the gate structure from the lightly doped ρ ^ drain region; and 'a heavily doped P-type source region and a heavily doped ρ-type drain Regions are formed in the lightly doped P-type source region and the lightly doped P-type drain region, respectively. 1 · As in the element of the patent application No. 12, wherein the gate structure includes at least a gate dielectric Layer and a conductor layer. 1 4 · The element according to item 12 of the patent application range, wherein the lightly doped p-type source region and the lightly doped p-type drain region are in contact with the insulating layer. Page 20