514990 五、發明說明（1) - 發明領域： 本發明與一種半導體元件有關，特別是一 抵穿阻擋（punchthrough stop)之金氧半導辨二 士此. $ 體（M0S) 發明背景： 金氧半場效電晶體（M0SFET)在積體電略工業中 是一典型且被廣泛應用於電路設計中的元件之二 在電晶體中，通道（channel )之區域通常摻雜<與、及極 /源極相反電性之離子。操作之過程包含在二/ ° ^ ^ %閘極施以 電壓。藉由調整電壓值，可以將通道之離子電性反 轉進而產生通道電流於其中。一般的場效電晶體其 通道、汲極與源極均形成在單晶矽底材之中。B高i生 能MOSIt術已經發展好些年了，為了得到高構裝密度 之晶圓以用於超大型積體電路（ULSI)中，元件的尺& 寸已縮小至以次微米計，然而在縮小元件時也付出 了相當的代價。例如，寄生效應將降低RC延遲及源 極與汲極之串連電阻，在先前技術中曾揭示造成傳 遞延遲（Tpd)降低之因素為閘極電阻（Rgsh)，而閘極 片電阻正好是通道寬度的函數。請參見論文”A Novel 0.15// m CMOS Technology using W/WNX/Po1ysi1icon Gate Electrode and Ti Silicided Source/Drain Diffusions, Μ. T. Takagi et al·， 1996， IEDM 96-455.n。該文作者514990 V. Description of the invention (1)-Field of the invention: The present invention relates to a semiconductor device, in particular a metal-oxygen semiconducting device with a punchthrough stop. 体 (M0S) Background of the Invention: Gold-Oxide The half field effect transistor (MOSFET) is a typical and widely used component in circuit design in the integrated electronics industry. In the transistor, the channel area is usually doped with < and, and / The source is an oppositely charged ion. The operation consists of applying a voltage to the gate at two / ° ^ ^%. By adjusting the voltage value, the ionization of the channel can be reversed to generate the channel current in it. The channel, drain and source of a general field effect transistor are all formed in a single crystal silicon substrate. B high-energy MOSIt technology has been developed for several years. In order to obtain wafers with high packaging density for use in ultra large integrated circuits (ULSI), the size of the components has been reduced to sub-micron, however A considerable price is also paid when downsizing components. For example, the parasitic effect will reduce the RC delay and the series resistance of the source and the drain. In the prior art, it has been revealed that the factor that causes the reduction of the transmission delay (Tpd) is the gate resistance (Rgsh), and the gate resistance is exactly the channel A function of width. See the paper "A Novel 0.15 // m CMOS Technology using W / WNX / Po1ysi1icon Gate Electrode and Ti Silicided Source / Drain Diffusions, M. T. Takagi et al., 1996, IEDM 96-455.n. Author of this article
i 514990 五、發明說明（2) --- 於是建議藉著使用較低之Rgsh可以增加在Μ〗設計中 的自由度。而自對準矽化金屬製程是 的方法之-。此外，自==金ΐ 二速度此優點正好為超短 對ULSI電 的尺度，因此 件中一個很重 會受到 強度。 多種閘 可靠度 抗輻射 層，很 如，利 層。另 閘極氧 以離子 用含有 一個方 化層是 植入法 峪而言 ’該超 要的問 报多因 為了使 極氧化 氮原子 法則是 藉由沈 注入石夕 ，其閘極氧化層會縮小至極薄 薄氧化層的可靠度亦是縮小元 題。一般而言，超薄氧化層的 素的影響’諸如熱載子效應及 MOSFETs具有可靠的閘極氧^ 層的結構被提出來討論。例 的氧化層來取代單純的熱氧化 使用氟化閘極氧化層，該氟化 浸石夕原子於HF溶液中或是把氟 閘極中所形成的。 抵穿現象（pUnchthrough)為元件縮小後所面臨 之困難之一，元件之抵穿電位為汲極電位造成元件 之沒極空乏區域延伸至源極區域，而造成M〇s失去作 為開關之功效。一般包含兩種方式防止上述現象， 一為雙獨離子佈植至P型基板用以形成N通道加強模 式 M0S。另一種方法採用 LATIps(large —angle implanted punchthrough stopper )技術防止抵穿現i 514990 V. Description of the Invention (2) --- It is suggested that the degree of freedom in the design can be increased by using a lower Rgsh. The self-aligned silicide process is one of the methods-. In addition, the advantage of self-== golden two speeds is just an ultra-short to ULSI scale, so one of the pieces will be subject to strength. A variety of gate reliability radiation-resistant layers, such as the profit layer. In addition, the gate oxygen is implanted with a squared layer for ions. In terms of this, the most important question is because the law of polar nitrogen oxides is injected into the stone by sinking, and its gate oxide layer will shrink. The reliability of extremely thin oxide layers is also a narrowing issue. In general, the effects of the elements of the ultra-thin oxide layer such as the hot carrier effect and the structure of the MOSFETs with a reliable gate oxide layer are proposed and discussed. The example oxide layer is used instead of pure thermal oxidation. A fluorinated gate oxide layer is formed by fluorinated immersion stone atoms in an HF solution or a fluorine gate. PUnchthrough is one of the difficulties faced after the device is shrunk. The breakdown potential of the device is the drain potential, which causes the non-empty area of the device to extend to the source area, which causes Mos to lose its function as a switch. Generally, there are two ways to prevent the above phenomenon. One is to implant double-separated ions on the P-type substrate to form the N-channel enhanced mode MOS. Another method uses LATIps (large —angle implanted punchthrough stopper) technology to prevent puncture
514990 五、發明說明（3) _ 象。此技術植入高濃度p型區域 抵穿現象。 —；f極下方防止上述 發明目的及概述： 本發明之目的在提供 件以及其製造方法。 種具有抵穿阻擋之M〇s元 一種製造具有抵穿阻擋之電曰 含··形成閘極氧化層於半導體曰曰遐之方法至少包 極於閘極氧化層上，倒_ p卩氐上，形成倒τ型閘 下寬。之後執行第一次離%~=之截面:结構係為上窄 於半導體底材中並部分位於倒成第摻雜區域 得注意之處在於此處佈植 f極下側，其中值 子，態相同。部分離子將穿透與基板之離 局卓幕，進仃第二次離子植入 閘極做 於該半導體底材中做為LDD，再形/ 一/參雜區域 倒T型閘極之側壁 貝1壁間隙於 該倒τ型閉極做為罩壁間隙與 ί ΐ ί :極於半導體底材中。形成第二側壁入二形成 1 土間隙之侧壁上（此步驟可以省略）。’、於 導體i 之電晶體包含：閘極氧化層，形成於丰 材上^型問極，位於該閘極氧化層上% 514990 五、發明說明（4) 一離子摻雜區域，位於該半導體底材中並部分位於 該倒T型閘極下側；第一側壁間隙，位於該倒T型閘 極之側壁之上；第二離子摻雜區域，位於該半導體 底材中做為LDD ;第二側壁間隙，位於該第一側壁間 隙之側壁上；及第三離子摻雜區域，做為汲極與源 極位於該半導體底材中。其中上述之第一離子摻雜 區域包含第一型態離子，例如硼。第二、第三離子 摻雜區域係包含第二型態離子，例如磷。倒T型閘極 包含多晶矽，或是倒T型閘極包含金屬及多晶矽形成 之堆疊結構。再者，倒T型閘極包含金屬、阻障層及 多晶矽形成之堆疊結構。 發明詳細說明： 參照圖一，在一較佳之具體實施例中使用一具 < 1 0 0 >晶向之單晶底材2，熟知該項技藝者可知，其 他類型之半導體也可以作為本發明之基板。如基板2 為結晶面向< 11 1 >的單晶矽。其它之半導體材質如砷 化鉀或鍺亦可以使用。在底材2上形成一薄氧化層4 以做為閘極氧化層。在一較佳之具體實施例中，該 閘極氧化層4是由在溫度約8 0 0至11 0 0°C之氧蒸氣環 境中形成的氧化矽所構成。同理，該閘極氧化層4亦 可以合適的氧化物之化學組合及程序來形成。例514990 V. Description of the invention (3) _ Elephant. This technique implants high-concentration p-type regions to resist the phenomenon. — The bottom of f prevents the above-mentioned object and summary of the invention: The object of the present invention is to provide a part and a manufacturing method thereof. A kind of MOS element with a breakdown barrier. A method of manufacturing an electricity with a breakdown barrier. The method of forming a gate oxide layer on a semiconductor is at least included on the gate oxide layer. , Forming the width under the inverted τ gate. After that, the first cross section from% ~ = is performed: the structure is narrower than the semiconductor substrate and partially located in the inverted doped region. The attention is that the lower side of the f pole is implanted here, the median, the state the same. Part of the ions will penetrate the substrate and leave the curtain. The second ion implantation gate will be used as the LDD in the semiconductor substrate, and the shape of the side wall of the inverted T-shaped gate in the / one / mixed region 1 wall gap in the inverted τ closed pole as the cover wall gap and ί :: extremely in the semiconductor substrate. Form the second side wall into the second side wall with 1 soil gap (this step can be omitted). 'The transistor in conductor i includes: a gate oxide layer formed on the material ^ -type interrogator, located on the gate oxide layer% 514990 V. Description of the invention (4) An ion-doped region located in the semiconductor The substrate is partially located below the inverted T-gate; the first sidewall gap is located above the sidewall of the inverted T-gate; the second ion-doped region is located in the semiconductor substrate as LDD; Two sidewall gaps are located on the sidewalls of the first sidewall gap; and a third ion-doped region is located in the semiconductor substrate as a drain and a source. The first ion-doped region includes a first-type ion, such as boron. The second and third ion doped regions contain a second type of ion, such as phosphorus. The inverted T-gate includes polycrystalline silicon, or the inverted T-gate includes a stacked structure formed of metal and polycrystalline silicon. Furthermore, the inverted T-gate includes a stacked structure formed of metal, a barrier layer, and polycrystalline silicon. Detailed description of the invention: Referring to FIG. 1, in a preferred embodiment, a single crystal substrate 2 with a crystal orientation of < 1 0 0 > is used. Those skilled in the art know that other types of semiconductors can also be used as the substrate. Invented substrate. For example, the substrate 2 is a single crystal silicon having a crystal face < 11 1 >. Other semiconductor materials such as potassium arsenide or germanium can also be used. A thin oxide layer 4 is formed on the substrate 2 as a gate oxide layer. In a preferred embodiment, the gate oxide layer 4 is composed of silicon oxide formed in an oxygen vapor environment at a temperature of about 800 to 1100 ° C. Similarly, the gate oxide layer 4 can also be formed by a suitable chemical combination and procedure of the oxide. example
五、發明說明（5) 如，該閘極g儿a , 成之二氧化：：4可乂是使用化學氣相沈積法所形 /ΦΡΑΟΝ. , Μ化學氣相沈積法是以正石夕酸乙舻 :?);溫度6°0至間且壓力約0.1至心二 厚度大約B 圭9之具體實施例中，該閘極氧化層4之 氧化層4上Ί :埃。藉由化學氣相沈積法在閘極 :ί 2 f日日石夕層6以形成倒7型閘極。p型底材4 i =蝴做為摻雜，濃度大約為E15 atQms//方 :A : i型r閘極之截面結構下側部分兩端較薄，也就 疋其結構係為上窄下寬之截面。 也就 參照圖二， 罩幕，進行第一 一次離子佈植之 同，舉例而言， 部分離子將穿越 摻雜區域位於倒 LATIPS植入高濃 現象。硼離子劑 為 3 0 - 1 2 0Kev。 為 E1 7 a toms/立 倒T型閘極在形成後，以其做為佈 次離子佈植。必須注意的是上述第 離子態樣必須與基板之離子態樣相 形成P型摻雜區域於P型底材2之中目 倒T型閘極較薄之區域，而部分p ’ T型閘極之下方。其可以不採用 度p型區域於閘極下方防止上述抵 量約為5E12/平方公分及佈植能量 此佈植將接近底材之表面濃 = 方公分。 及w周整 完成之後，接續實施第二次離子佈植，以 〜LDD於底材2之中，閘極之側用以降低熱載子‘成V. Description of the invention (5) For example, the gate electrode g a, the oxidization of 2: 4 can be formed by using a chemical vapor deposition method / ΦΡΑΟΝ., M chemical vapor deposition method is based on orthorhombic acid (E) :?); In a specific embodiment where the temperature is 6 ° 0 to 0 ° and the pressure is about 0.1 to the thickness of the core 2 is about 9 °, the oxide layer 4 of the gate oxide layer 4 is on the upper layer: Angstroms. By chemical vapor deposition at the gate: ί 2f rixi stone layer 6 to form an inverted 7-type gate. p-type substrate 4 i = butterfly as doping, the concentration is about E15 atQms // square: A: i-type r gate cross-sectional structure of the lower part of the lower part of the thinner, that is, its structure is narrow top Wide cross section. Also referring to Figure 2, the mask is the same as the first ion implantation. For example, some ions will pass through the doped region and are located in the inverted LATIPS implantation with high concentration. The boron ionizer is 3 0-1 2 0 Kev. After the formation of E1 7 a toms / vertical T-gate, it is used as the ion implantation. It must be noted that the above-mentioned ionic state must form a P-type doped region with the ionic state of the substrate. In the P-type substrate 2, the T-type gate is relatively thin, and some p ′ T-type gates are formed. Below. It is not necessary to use a degree p-type area under the gate to prevent the above-mentioned offset of about 5E12 / cm 2 and the planting energy. This planting will be close to the surface concentration of the substrate = square centimeter. After the completion of w and the whole week, the second ion implantation is carried out successively, with ~ LDD in the substrate 2, and the side of the gate is used to reduce the hot carrier ’s
第8頁 514990 五、發明說明（6) 應。可以控制製程使得閘極下方兩側之厚度，N_LDD 佈植之能Ϊ較低而使第一次離子佈植之離子穿透閘 極而第二次離子佈植無法穿透。其兩側較薄之處可 以控制厚度約為5 0 0至2 0 0 0埃之間。 利用一 >儿積膜層以及非等向性姓刻製程製作第 一側壁間隙1 0位於倒τ型閘極6側壁之上。此第一側 壁間隙1 0係利用沈積膜層再蝕刻之技術製作，其可 採用絕緣材質如二氧化矽或是氮化矽製作。二氧化 矽層一般為利用化學氣相沈積法以TE0S為反應物可 =形成二氧化矽層6。氮化矽可於溫度攝氏3^0至8〇〇 =圖三’之後再進行第三次離子佈植以形成 隙14(此步驟可以省略'選，性製作絕緣閘極侧壁間 上以及執行金屬4製程$後再沈積'絕緣層於閘極 次離子佈植係採用N型離。早第彳；"次離子佈植以及第三 土雕子例如磷離子。 其中上述之LDD也< ，— 植，再製作第一側壁間以在製作第一側壁間隙後佈 16。 9隙’之後製作汲極與源極 參照圖四與圖五，八 、 刀別為本發明閘極之組成Page 8 514990 V. Description of Invention (6) Application. The process can be controlled so that the thickness of the two sides below the gate electrode is lower. The energy density of N_LDD implantation is lower, so that the ions implanted for the first time can penetrate the gate and cannot be penetrated for the second time. The thinner sides can control the thickness from about 500 to 2000 angstroms. The first side wall gap 10 is formed on the side wall of the inverted τ gate 6 by using a > child film layer and an anisotropic surname engraving process. The first side wall gap 10 is made by a technique of depositing a film layer and then etching, and it can be made of an insulating material such as silicon dioxide or silicon nitride. The silicon dioxide layer is generally formed by chemical vapor deposition using TEOS as a reactant. Silicon nitride can be implanted for the third time to form the gap 14 after the temperature is between 3 ^ 0 and 800 ° C = Figure III. (This step can be omitted. After the metal 4 process, the 'insulation layer' is deposited on the gate secondary ion implantation system using N-type ionization. The "secondary ion implantation" and the third earth sculpture such as phosphorus ion. The above-mentioned LDD is also < Planting, and then making the first side wall to fabricate 16. After making the first side wall gap, the drain and source are made after 9 gaps. Refer to Figure 4 and Figure 5, and 8. The knife is the composition of the gate of the present invention.
514990 五、發明說明（7) 由上 閘極 別為 圖四之閘極組成係為兩層膜層所構成之結構， 而下分別為金屬層6b以及多晶矽層6a。圖五之 組成係為三層膜層所構成之結構，由上而下八 金屬層6 c阻障層6 b以及多晶矽層6 a。 刀 本發明之電晶體包含：閘極氧化層，形成於“ 體底材上；倒T型閘極，位於該閘極氧化層上/半導 離子摻雜區域，位於該半導體底材 曰八’第一 倒T型閘極下側；第一側壁間隙 \亚口丨刀位於該 之側壁之上；第二離子摻雜區域，； 倒^型閘極 材中做為LDD ;第二側壁間隙，仅 ；5亥半導體底 之側壁上；及第三離子摻雜區域，、以一側壁間隙 位於該半導體底材中。其中上述$ 2 =與源極 域包含第一型態離子，例如硼。 够—操雜區 雜區域係包含第二型態離子，例=:、第:離子換 含多晶矽，或是倒T型閘極包含全°//型閘極包 堆疊結構。再者，.〗T型閘極包含：：夕：：形成之 晶石夕形成之堆疊結構。 匕…、阻障層及多 從上述揭露可以了解本發明 (1)本發明按爾在丨Τ刑Μ托π k供了下列優點： 知θ私用倒τ型閘極不必使用 子佈植於問極下方製作抵穿阻4用LATI_術將離 本發明雖以一較佳實例闌明如上，然其並非用以 514990 五、發明說明（8) 限定本發明精神與發明實體，僅止於此一實施例 爾。對熟悉此領域技藝者，在不脫離本發明之精神 與範圍内所作之修改，均應包含在下述之申請專利 範圍内。 514990 圖式簡單說明 圖式簡單說明： 藉由以下詳細之描述結合所附圖示，將可輕易的了 解上述内容及此項發明之諸多優點，其中： 圖一為半導體晶片之截面圖，顯示在一半導體底材 上形成倒τ型閘極以及第一次離子佈植之步驟。 圖二為半導體晶片之截面圖，顯示形成第一側壁間 隙及第二次離子植入之步驟。 圖三為半導體晶片之截面圖，顯示形成第二側壁間 隙及第三次離子植入之步驟。 圖四為本發明第二實施例之截面圖。 圖五為本發明第二實施例之截面圖。 圖號說明 底材2 閘極氧化層4 閘極6 第一摻雜區域8 第一側壁間隙1 0 第二摻雜區域12 第二側壁間隙1 4 第三摻雜區域16514990 V. Description of the invention (7) The structure of the upper gate is shown in Figure 4. The gate is composed of two layers, and the bottom is a metal layer 6b and a polycrystalline silicon layer 6a. The composition shown in Fig. 5 is a structure composed of three film layers, from top to bottom, a metal layer 6 c, a barrier layer 6 b, and a polycrystalline silicon layer 6 a. The transistor of the present invention includes: a gate oxide layer formed on a "substrate"; an inverted T-shaped gate electrode located on the gate oxide layer / semiconductor ion-doped region and located on the semiconductor substrate. The lower side of the first inverted T-shaped gate; the first side wall gap \ sub-port knife is located on the side wall; the second ion doped region; the LDD in the inverted gate material; the second side wall gap, Only; on the side wall of the semiconductor substrate; and a third ion-doped region, which is located in the semiconductor substrate with a side wall gap. The above $ 2 = and the source domain include a first type ion, such as boron. —The miscellaneous region of the miscellaneous region contains the second type of ions, for example = :, the first: the ion contains polycrystalline silicon, or the inverted T-type gate includes a full ° // type gate packet stack structure. Furthermore,. 〖T The type gate includes: a: a stacked structure formed by a spar. A dagger ..., a barrier layer and many more can be understood from the above disclosure. (1) The present invention is based on It has the following advantages: It is not necessary to use the sub-fabrication of the inverted τ-type gate for the private use of the θ to make a puncture resistance. Although the present invention is described above with a preferred example, it is not intended to be used for 514990. 5. Description of the invention (8) The spirit and the entity of the invention are limited only to this embodiment. For those skilled in the art Modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application as follows. 514990 Schematic illustrations Schematic descriptions: With the following detailed description combined with the attached drawings, Easily understand the above content and many advantages of this invention, including: Figure 1 is a cross-sectional view of a semiconductor wafer, showing the steps of forming an inverted τ gate on a semiconductor substrate and the first ion implantation. Figure 2 is A cross-sectional view of a semiconductor wafer shows the steps of forming a first sidewall gap and a second ion implantation. Figure 3 is a cross-sectional view of a semiconductor wafer showing the steps of forming a second sidewall gap and a third ion implantation. Sectional view of the second embodiment of the present invention. Figure 5 is a sectional view of the second embodiment of the present invention. The drawing number illustrates the substrate 2 gate oxide layer 4 gate 6 first doped region 8 first Sidewall gap 1 0 second doped region 12 second sidewall gap 1 4 third doped region 16