TW513781B - Interconnect structure with covered metal barrier layer and its manufacturing method - Google Patents

Abstract

An interconnect structure includes the followings: at least two adjacent metal conducting wires, which are separated from each other by an opening formed between them; a metal barrier layer, which is formed on the sidewall of the metal conducting wire; a dielectric layer, which is formed to cover the metal barrier layer and the exposed region of the metal conducting wire so as to fill up the opening to a predetermined height; and a contact plug, which penetrates the dielectric layer to form an electric connection with the top portion of the metal conducting wire.

Description

513781 V. Description of the invention (1) The present invention relates to an interconnect structure of a semiconductor circuit with a high accumulation degree, and more particularly to an interconnect structure covered with a metal barrier layer and a manufacturing method thereof. In the ultra-large-scaie integration (ULSI) process, the multi-metal interconnect structure is made of many metal wires in different layers to improve the circuit performance of the component and the functional complexity of the circuit. The gap between adjacent metal wires needs to be filled with an internal metal dielectric layer (IMD) with a low dielectric constant, which can not only prevent the penetration of water vapor, but also reduce the adjacent metal wires. Between the capacitors. Therefore, the current important issue is how to improve the general deposition process to form a high-quality, non-porous inner metal dielectric layer. Please refer to FIGS. 1A to 1D. U.S. Patent No. 6, 1 1 7, 345 proposes a method for fabricating an inner metal dielectric layer using a high-density plasma chemical vapor deposition (HDPCVD) process. . As shown in the figure, the surface f of the semiconductor substrate 1 {) is deposited with a surface layer 12, a wire layer 14, a protective layer, and a cap layer 18, and a photoresist layer 20 having a predetermined pattern is a defined cap layer. 18, a plurality of predetermined areas 22 are exposed. After the presentation, as shown in FIG. 2B, the photoresist layer 22 is used as a mask, and the cover layer 18, the protective layer 16, the wire layer "and the table" under the #j domain 22 are sequentially formed to form a plurality of openings 26, and then The photoresist layer 20 is removed. In this way :: The conductive wire layer 14 separated by the opening 26 is defined to form a complex 1 ′. Then, as shown in FIG. Κ, a HDPCVD process having a high enough ratio is used to: 10 = to / condition on the whole base

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0702-6245TWF; 90P39; Cherry.ptd

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HDPCVD oxidation layer 28. In the initial stage of the HDPCVD process, the top corners of the cover layer 18 will be engraved, so the HDpcVD oxide layer 28 deposited on top of the cover layer 8 will form a taper, and the subsequent stage can make the HDpcvD oxide layer 28 All the openings 26 are filled in, and the HDPCVD process is not ended until the HDPCVD oxide layer 28 is deposited to the south of the protective layer 16. Then, as shown in FIG. 1D, the entire table enhanced chemical vapor deposition (plasma enhanced chemical vapor oxide layer 28) is caused by the wall at the time of the above-mentioned technical resistance layer 20, resulting in the conductivity of the metal wire. Sex tolerance. Second, such as adhesion, it is also an organic low dielectric constant gas (outgassing) to solve these problems, to separate the interconnect junction plus the interconnect structure and in view of this, a semiconductor substrate on the line is formed on The wires are separated by a side wall of the wire; during the operation of a depos, the clear wire 2 4 5 used to increase the presence of a material must be formed in and out of the metal. A dielectric layer (PECVD) process is used to form a PECVD oxide layer 29 in HDPCVD. There are still some disadvantages. First of all, the pattern on the side of the metal wire 24 is easily invaded when the photo-washing solvent is removed, which will not only reduce the gold but also the misalignment between the metal wire 24 and the HDPCVD oxide layer 28 during the subsequent fabrication of the contact plug. The problem. In addition, if the inner metal dielectric layer is used instead, it will result in a decrease in the electrical performance of the product. In order to cover the interconnection structure with a covering layer, a metal dielectric layer may be used, and the adhesion between the dielectric layers may be controlled by the covering layer. An interconnect structure is proposed, which is fabricated on the surface of the substrate which includes at least two adjacent metal conductors, and the two adjacent metal conductors are a metal, and a barrier layer is formed on the metal conductor. Covering the metal barrier layer and the metal

513781 V. Description of the invention (3) The exposed area of the wire fills the opening to a predetermined height; and a contact plug penetrates the dielectric layer and forms an electrical connection with the top of the metal wire. The invention provides a method for manufacturing an interconnect structure, which includes at least the following steps: providing a semiconductor substrate, the surface of which includes at least two adjacent metal wires, and at least one opening for separating the two adjacent Forming a metal barrier layer on a side wall of the metal wire; forming a dielectric layer on the metal wire layer, and filling the opening to a predetermined height with the dielectric layer; the dielectric layer The surface is flattened; a contact hole is formed above the metal wire, so that the contact hole penetrates the dielectric layer and exposes the top of the metal wire; and a conductive layer is formed, and the conductive layer fills the contact hole. Brief description of the drawings: Figures 1A to 1D show cross sections of the conventional method for fabricating an inner metal dielectric layer, which is not intended. Figures 2A to 2I are schematic cross-sectional views showing a method for manufacturing an interconnect structure according to the present invention. Explanation of symbols: Surface layer ~ 12; protection layer ~ 16; photoresist layer ~ 2 0; metal wire ~ 2 4; HDPCVD oxide layer ~ 28; semiconductor substrate ~ 10 wire layer ~ 1 4; cover Layer ~ 1 8; predetermined area ~ 22; opening ~ 2 6;

0702-6245TWF; 90P39; Cherry.ptd page 6 513781 Description of the invention (4) PECVD oxide layer ~ 29. The present invention provides a first titanium layer ~ 3 1; an aluminum copper layer ~ 3 3; a second titanium nitride layer ~ 3 5; a cover layer ~ 38; a predetermined area ~ 4 1; a metal wire ~ 4 4; an HDPCVD oxide layer ~ 48; contact hole ~ 5 2; conductive layer ~ 56. Semiconductor substrate ~ 30; first titanium nitride layer ~ 32; second titanium layer ~ 34; metal wire layer ~ 36; photoresist layer ~ 40; opening ~ 4 2; metal barrier layer ~ 46; PECVD oxide layer ~ 50; Barrier layer ~ 5 4; Example · Please refer to Figs. 2A to 21, which is a 5-丄 々 氺 丄 々 氺 立 丨 丨 品-立 固 l junction. It is not shown in the cross section of the method for making an interconnect structure according to the present invention. As shown in Fig. 2A a-and point 丨 products are as good as π ... The figure does not provide a semiconductor substrate 30, for example: 'It can be made with transistors, diodes, other conventional semiconductor components or It is the other metal direction, strike & rabbit interconnector layer. The surface of the semiconductor substrate 30 includes a metal wire layer 36, which may be made of any of the following materials, such as aluminum, an aluminum alloy containing silicon or copper, a copper alloy, or a multilayer structure. In the preferred embodiment of the present invention, the metal wire layer 36 comprises a first titanium (Ti) layer 31, a first titanium nitride (TiN) layer 32, an aluminum copper (A1Cu) layer 33, and a first The two titanium layers 34 and a second titanium nitride layer 35 are formed. In addition, a cover layer 38 is deposited on the surface of the metal wire layer 36, and a photoresist layer 40 having a predetermined pattern is defined on the surface of the cover layer 38 to define a plurality of predetermined areas 41. In the preferred embodiment of the present invention

0702-6245TWF; 90P39; Cherry.ptd Page 7 513781 5. In the description of the invention (5), the covering layer M may be made of oxynitride (SiO) material, which is used as the exposure process for the photoresist layer 40. The anti-reflection layer can prevent light from passing through the cover layer 38 or reflecting back to the photoresist layer 40. Secondly, the cover layer "can also be used as a hard mask layer for subsequent etching of the metal wire layer 36. In addition, the cover layer 38 can also serve as a protective layer for the metal wire to prevent subsequent HDpcvD processes from etching the metal wire. At the corner, as shown in FIG. 2B, the cover layer 38 and the metal wire layer 36 (including the multilayer structure 35, 34, 33, 32, and 31) under the predetermined area 41 are sequentially etched.

The photoresist layer 40 is removed to form a plurality of openings 42 and the photoresist layer 40 is removed. As such, the metal wire layers 36 separated by the openings 42 are defined to form a plurality of metal wires 44. Then, as shown in FIG. 2G, a metal barrier layer 46 is uniformly deposited on the entire surface of the semiconductor substrate. Subsequently, as shown in FIG. 2D, a non-isotropic etching method, such as a reactive zed etcher (R IE) process, is used to expose the metal barrier layer at the bottom of the opening 42: Wang Removal to expose it. The substrate 30 surface. At the same time, the metal barrier layer 顶部 on the top of the cover layer 38 can also be removed according to the control situation of the manufacturing process. In this way, the remaining metal barrier layer 46 covers a metal conductive layer of the United States.

J In a preferred embodiment of the present invention, the metal barrier layer 46 may be made of metal, such as: Ti, TiN, Ta, TaN, Cu j may be made by CVD, PVD, or electroplating processes. When the photoresist layer is removed at 40 ° C, the cleaning solvent causes: The "knowledge" can be compensated by the metal barrier layer 46 to ensure that the metal wire 44 has sufficient conductivity and can increase subsequent Making contact plugs

513781 V. Inaccuracy tolerance of invention description (6). The second purpose is that the metal barrier layer 46 can improve the adhesion between the metal wire 44 and the metal dielectric layer in the subsequent fabrication. The third purpose is that when an organic low dielectric constant material is used for the inner metal dielectric layer, the metal barrier layer 46 can be used to prevent outgassing of the inner metal dielectric layer. As shown in FIG. 2E, an HDPCVD process is performed to form an HDPCVD oxide layer 48 on the entire surface of the substrate, and the HDPCVD oxide layer 48 completely fills the opening 42. Since the HD P C V D process is a simultaneous deposition process and an engraving process, the HDPCVD oxide layer 48 formed on top of the cover layer 38 is tapered. Next, as shown in FIG. 2F, a PECVD process is performed to form a pec VD oxide layer 50 'having a sufficient thickness on the surface of the HDPCVD oxide layer 48, and the surface height of the PECVD oxide layer 50 is the same as that of the HDPCVD oxide layer 48. The surface is undulating with similar contours. In other preferred embodiments of the present invention, the materials of the HDPCVD oxide layer 48 and the PECVD oxide layer 50 may be replaced with organic low-dielectric constant materials, such as: spin-on polymer (Spin-On Polymer, SOP) , Which is FLARE, SILK, Parylene or PAE-II, etc., and can be manufactured on the surface of the substrate 30 by a spin coating method. As shown in FIG. 2G, a chemical mechanical polishing (CMP) process is performed to planarize the surface of the PECVD oxide layer 50 to provide a comprehensive planarization surface for subsequent contact plug processes. The HDPCVD oxide layer 48 and the PECVD oxide layer 50 surrounding the metal wire 44 are used as the inner metal dielectric layer. Next, according to the process requirements, a contact plug process can be performed. As shown in Figure 2H, the PECVD oxide layer 50, HDPCVD oxide layer 48, and cover layer 38 over the metal wire 44 are removed by lithography and etching processes. Gold

0702-6245TWF, 90P39; Cherry.ptd Page 9 M3781 V. Description of the invention (7) A contact hole 5 2 is formed above the wire 4 4. Then, as shown in FIG. 2I, a barrier layer 54 is formed on the sidewall and the bottom of the contact hole 52, and a conductive layer 56 is internalized in the contact hole 52. Finally, the conductive layer 56 and PECVD oxygen are CMP method. Layers 5 and 6 can be cut in degrees. In this way, the conductive 54 remaining in the contact hole 52 can be contacted with the plug. In the preferred embodiment of the present invention, the barrier layer; the conductive layer 56 may be composed of any of the following materials: TJN, Ta or steel, aluminum alloy, copper alloy, aluminum, silicon, etc. Although the present invention Has been constructed. To limit the present invention, any familiar C: if i 'then it does not use the scope of protection as the attached changes and fullness', therefore, the companion of the present invention is defined by the scope of the Kappa patent, Guangyue Bao 0702-6245TWF; 90P39; Cherry.ptd Page 10

Claims (1)

1. An interconnect structure, including: a surface formed on a semiconductor substrate to at least two adjacent metal conducting surfaces, and the two adjacent metals,, and 'are formed on the semiconductor The base surface is a metal barrier layer, which is formed by an opening between the wires; a dielectric layer covering the gold = the t belongs to the side wall of the wire; the area is filled with the opening to the box ^, The exposed-contact plug of the barrier layer and the metal wire penetrates the JJ height; and forms an electrical connection. Μ ′ 丨 The interconnection structure described above with the dielectric layer on top of the metal wire and the dielectric layer 2 and 2 ′, where the vaPor is incorporated into the emperor as the interconnection structure described in item 1 of the scope of patent application Wherein, the material of the Γ I is an organic low dielectric constant material manufactured by a spin coating method. 4. The interconnect structure according to item 1 of the scope of the patent application, wherein the dielectric layer includes at least: a first silicon oxide layer covering the metal wire and filling the opening; and a second silicon oxide The layer is formed on the surface of the first silicon oxide layer to a predetermined thickness. 5. The interconnect structure as described in item 4 of the scope of the patent application, wherein the first silicon oxide layer is subjected to high density plasma chemical vapor deposition (HDPCVD) 0702-6245TWF; 90P39; Cherry.ptd Page 11 513781 6. Scope of Patent Application Manufactured by method. 6. The interconnect structure described in item 4 of the scope of the patent application, wherein the second silicon oxide layer is made by a plasma enhanced chemical vapor deposition (PECVD) method. 7. The interconnect structure described in item 1 of the scope of the patent application, wherein the metal barrier layer is made of any of the following materials: T i, τ i N, Ta, TaN, Cu, and copper alloy. 8. The interconnect structure described in item 1 of the patent application scope, further comprising a cover layer formed on top of the metal wire. 9 · A method for manufacturing an interconnect structure, including at least the following steps: 'Provide a semiconductor substrate, the surface of which includes at least two adjacent metal wires, and at least one opening for separating the two adjacent A metal barrier forms a metal barrier layer on a side wall of the metal wire; a dielectric layer is formed on the metal wire layer, and the dielectric layer fills the opening to a predetermined height; a surface of the remote dielectric layer Ping 丨 Yuanhua · On the metal wire, a square 忐 larus, door | ^ ^ into the currency administration Congyi I ★ AB heart into a contact hole, so that the contact hole penetrates the dielectric layer and exposes the metal wire The top; and "a conductive layer" is formed and the contact hole is filled with 4 conductive layers by 4 w > on t 士 1 η. 10 · The material of the ninth electrical layer in the dry wall of Shen Qing patent is through the chemical compound 4 "^ Chavan, the middle oxygen phase > chemical product (chemical vapor 0702-62451W; 90P39; Cherry.ptd Page 12 513781 material. Forming a second silicon oxide layer to cover the first method, wherein the interposed organic low-dielectric constant corpse stinger < manufacturing method, wherein the interposing step: to cover the metal wire and fill the The surface of the silicon oxide layer is opened to a predetermined thickness. 13 3. The manufacturing method as described in item 12 of the scope of the patent application, wherein the first silicon oxide layer is made by a high " lensity plasma chemical vapor deposition (HDPCVD) method . 1 ^ · The manufacturing method as described in item 丨 2 of the patent application scope, wherein the second silicon oxide layer is made by a plasma enhanced chemical vapor deposition (PECVD) method 1 5 · 如The manufacturing method described in item 9 of the scope of the patent application, wherein the metal barrier layer is made of any one of the following materials: Ti, TiN, Ta, TaN, Cu, and copper alloy. 16 · The manufacturing method as described in item 9 of the scope of patent application, wherein the manufacturing method of the metal barrier layer includes at least the following steps: · depositing the metal barrier layer on the metal wire and the semiconductor substrate 0702-6245TW; 90P39; Cherry.ptd page 13 513781 VI. Patent application scope on exposed surface; and removing the metal barrier layer on the surface of the semiconductor substrate. 1 7. The manufacturing method as described in item 9 of the scope of patent application, wherein the method of planarizing the surface of the dielectric layer is a chemical mechanical polishing (CMP) process. 1 8. The manufacturing method as described in item 9 of the scope of patent application, wherein the top of the metal wire further includes a covering layer. 0702-6245TWF; 90P39; Cherry.ptd Page 14