TW513757B - Manufacture method of ultra fine metal gate - Google Patents

Abstract

This invention discloses a manufacture method of metal gate using a damascene process. Firstly, a mask layer is formed on a semiconductor substrate and the mask layer is defined to from a gate opening. Then, according to requirements, a pair of dielectric separation layers is formed on the sidewall of the gate opening to further shrink width of the gate opening. A gate dielectric layer is formed on the substrate exposed by the gate opening and a polysilicon gate is formed at the bottom of the gate opening. A metal layer is formed on the mask layer and used to fill the gate opening. A planarization step is carried out on the metal layer to expose the mask layer so that a metal gate is formed on the polysilicon gate. After removing the mask layer, an ion implantation step is used to form source/drain regions to complete the preparation of the transistor.

Description

513757 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a method for manufacturing a metal gate in an integrated circuit, and more particularly to a method for manufacturing an extremely fine metal gate by using a damascene process. method. [Background of the Invention] With the increasing precision and complexity of integrated circuits, in order to be able to fabricate integrated circuits with a high degree of integration on a limited wafer surface, many advanced processes must be matched to reduce the component size. The reduction of the π-piece size is accompanied by many problems. In addition to the short-channel effect (sh0rt-channei effect), the increase in contact resistance is also an important issue. After the metallization process, the contact resistance of the small-sized component (between the active area and the metal contact) is greater than the contact resistance of the large-sized component. At the same time, the performance of small-sized components will be reduced. Therefore, it is known in the art to use a metal gate to reduce the contact resistance between the substrate and the gate, and at the same time reduce the sheet resistance of the gate. There is a key difficulty for Tian Yi to make metal problems, which is the way that metal == is defined. Because of the & ' the present invention proposes a method of making a metal gate by a damascene process, to avoid etching of the metal gate. [Summary of the Invention] One of the objectives of the present invention is to provide a method for manufacturing a metal gate, which does not require etching of the metal gate. Manufacturing ΐ: Ming 二 2 :: The second is to provide a very fine metal gate surface display method, whose gate width can be less than the lithographic limit. V. Description of the invention (2) In order to achieve the above purpose, the second method of the present invention includes the following main steps: manufacturing of two kinds of metal gates, and defining the mask layer to expose the mask layer layer through an opening of a semiconductor substrate. On the substrate, a gate-gate opening is formed; at the gate, a polycrystalline silicon layer is formed on the gate dielectric; an acoustic layer; the surface of the gate opening is lower than the gate opening, and in the gate-back Etching the polycrystalline silicon layer to: shore: form a metal layer on the mask layer and fill it: forming a polycrystalline silicon gate: the layer is flattened until the mask layer is exposed, and the metal is made into a metal gate pole. The shape of the complex silicon gate electrode provided by the present invention includes the following main steps: forming a manufacturing method of ^ =, forming a mask layer on the semiconductor substrate in the mask, and forming an opposite sidewall to form a Intermediate 'two-one gate openings; exposed at the gate openings at the inter-electrode openings: i: Gewu, reducing the width of the closed-electrode openings; a polycrystalline stone layer is formed in the mouth to the closed-electrode dielectric layer; The gate is open; formation-gold strikes: the formation of the polycrystalline slab gate layer at the bottom of the interrogator opening is flattened to the layer and fills the gate opening; and the gold-metal gate is formed. The mask layer is pulled out, so that the shape and other features, features, and advantages of the polycrystalline silicon can be more clearly explained as follows: The preferred embodiment, in conjunction with the accompanying drawings, will be detailed [the simplicity of the drawings [Explanation] Figure 17 is a series of cross-sectional views used to illustrate a preferred embodiment of the present invention 0516-7142TWf; 90043; esmond.ptd page 5 513757 V. Description of the invention (3) The process of the metal gate electrode fabricated in the embodiment . To illustrate another preferred 12 ~ isolation structure of the present invention; 16 ~ gate openings; 18 ~ gate dielectric layer; 20a ~ polycrystalline silicon gate 2 4 ~ metal layer; M ~ source / drain Figures 8 ~ 10 of the polar region are a series of cross-sectional views of the metal gate electrode fabrication process. [Symbols] 10 ~ semiconductor substrate; Η ~ mask layer; 16a ~ reduced gate opening; 2〇 ~ Compound silicon layer; 22 ~ notch; 24a ~ metal gate; 28 ~ dielectric spacer. [Embodiment] The process shown in FIG. 7 is detailed to illustrate the rid of the metal gate electrode produced by the present invention. The isolation structure 12 is formed on the semiconductor substrate 10. The semiconductor substrate 10 is preferably an isolation structure on a monocrystalline silicon wafer. The substrate 2 is preferably a shallow trench isolation structure (sh & 丨 丨 **-trench is〇iati〇n), which is used for isolation. Several different active areas on the substrate are identified. As shown in FIG. 2, a mask layer "is formed on the semiconductor substrate 10, and its material is preferably silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The mask layer 14 can be formed by chemical vapor deposition. (CVD) deposition, its preferred thickness range is 1000 ~ 5000A. Please continue to refer to Figure 2, using lithography imaging and anisotropic etching (anis〇tr〇pic etching), in the mask layer η Define a gate opening 1 6. For subsequent processes, the gate opening J 6

0516-7142TWf; 90043; esmond.ptd

513757

A composite gate including a complex silicon gate and a metal gate was fabricated in the process. Referring to FIG. 3, a gate electrode layer 18 is formed on the substrate ι exposed by the gate opening 16. The gate dielectric layer 18 is preferably a gate oxide layer having a thickness of 15˜200 Å, which can be used. The thermal oxidation method is obtained at a temperature between 65 and 100 (rc and a reaction time of 5 36,000 seconds. Please continue to refer to FIG. 3. A polycrystalline spar layer 20 is deposited in the gate opening 16 in the gate electrode. The electrical layer 18. The polycrystalline spar layer 2 () can be deposited by low pressure chemical vapor deposition (LPCVD) between 525 ~ 575 ° C, and its thickness preferably ranges from 1 0 0 0 to 5 0 0 0 Between A, it is to be able to fill the gate openings. 6 For N-type components, phosphine or arsenide can be added to the silane gas when the polycrystalline silicon layer is deposited at 20 °. (Arsine) doped in-situ, or you can also deposit a polycrystalline silicon layer 20, and then ion implantation with phosphorus ions or arsenic ions, the implantation energy range is about 25 ~ 75 KeV Approximately 1E1 4 ~ 1 El 6 atoms / cm 2. Please refer to Fig. 4 for the polycrystalline silicon layer 20 to be etched back so that its surface is lower than the gate opening 16 to form a notch 2 2. At this moment step A coin-cut gas containing CI can be used to selectively remove the polycrystalline stone. The depth of the notch 22 is preferably lower than the upper surface of the cover layer 14 by 500 to 2000 A. The purpose of the notch 22 is to In order to allow the subsequent steps to be filled with metal gates, a polycrystalline silicon gate 20 a is defined at the bottom of the gate opening 16. Referring to FIG. 5, the mask layer 14 and the polycrystalline silicon gate are defined in FIG. 5. A metal layer 24 is deposited on the electrode 20a and fills the recess 22. The material of the metal layer 24 may be Ti, W, A1, Ta, Cu, Co, Cr, Pt or the aforementioned alloy or the aforementioned Metal nitrides, such as TiN, WN, TaN, etc. The metal layer 24 can be deposited using plasma enhanced chemical vapor deposition (PECVD), sputtering, or best

0516-7142TWf; 90043; e smond.p t d p. 7 513757 V. Description of the invention (5) The one ′ uses a chemical vapor deposition method. Referring to FIG. 6, the metal layer 24 is planarized by a chemical mechanical polishing method (CMP) until the mask layer 14 is exposed. In this way, a metal gate 24a is left in the gate opening 16 and stacked on the polycrystalline silicon gate 20a. In addition, although this step can also use etch-back to remove excess metal materials', it is less suitable in manufacturing process. The main advantage of the present invention is that the definition of the metal gate 24a here does not need to pass through the etching process, so it can avoid all the difficulties caused by the metal surname engraving. The metal gate 24a obtained in accordance with the present invention and the underlying polycrystalline silicon gate 20a together form a composite gate. Because the metal has a very low resistance, the sheet resistance of this composite gate is lower than that of most polysilicon (polly pesticide; poiysi 1 i con-si! Pesticide) gates. Referring to FIG. 7, the mask layer 14 is removed from the surface of the substrate 10 by wet etching or selective dry etching, leaving a gate structure. Next, the substrate is implanted with a composite gate electrode to perform ion distribution on the substrate to form an f-pole / drain region 26 in the substrate to complete a MOS transistor structure. For N-type elements, the ions used for the a 'distribution may be arsenic or phosphorus, and arsenic is preferred. When the source / drain region 26 is formed with arsenic ions, the implantation energy can be 100KeV, and the implantation dose can be 1E15 ~ 8E1 5 atom / cm2. Figures 8 to 10 show another preferred embodiment of the present invention. In this embodiment, before the gate structure is formed, a pair of dielectric spacers 28 are formed to further reduce the size of the gate opening. Please refer to Fig. 8: After following the steps shown in Figs. 1 and 2, open the two dielectric spacers 28 on the opposite side of the gate opening 丨 6 to form a narrower gate. Opening ... The dielectric spacer 28 can be manufactured by first depositing a dielectric layer on the interlayer

0516.7142Bff; 90043; esraond.ptd page 8 ^ / 57, description of the invention (6) j port 16 and the mask layer 14, and then obtained by anisotropic etching. in this way . The width of the gate opening 16a can be reduced to a resolution smaller than that of the lithographic apparatus by the thickness of the dielectric spacer 28. Next, in accordance with the method described in the previous embodiment, a gate dielectric layer 18, a polycrystalline silicon gate 20 &, and an f gate 24a are sequentially formed in the reduced opening 16a. As shown in Fig. 9, the width of the gate structure is actually the gate width, and the width of the port 16 minus twice the width of the spacer 28, so it can exceed the micro-limit. After that, the mask layer 14 and the dielectric spacers 28 are removed, and the substrate 1G is ion-implanted with a gate electrode implanted curtain to form a source / negative degree. As shown in FIG. 10, the obtained transistor has a very fine gate width. Although the above-mentioned example of making a metal gate is formed by forming an NMOS device, the present invention is not limited thereto, and those skilled in the art may also Easily make PMOS or CMOS devices according to Zhaomei method. …, Although the present invention has been disclosed in the preferred embodiment as above,:; :: Anyone who is familiar with this technique will not be disengaged; hair = Erganwei will be determined by the scope of the attached patent. ’,

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Claims (1)

'Application patent scope 1 · A method for manufacturing a metal gate, including the following steps: forming a mask layer on a semiconductor substrate; defining the mask layer to form a free-electrode opening in the mask layer; A gate dielectric layer is formed on the exposed substrate of the gate opening; a polycrystalline stone layer is formed on the gate opening on the gate dielectric layer. The polycrystalline silicon layer is etched back to make the surface Below the gate opening, a polycrystalline silicon gate is formed at the bottom of the gate opening; μ forms a metal layer on the mask layer and fills the gate opening; and planarizes the metal layer until The cover layer is exposed to form a metal gate on the polycrystalline silicon gate. 2 · The manufacturing method of the metal gate electrode as described in item 1 of Shenjing's patent scope ', wherein the material of the cover layer is selected from the following groups: · stone oxide, silicon nitride, silicon oxynitride, and A combination of the foregoing. 3 · The method for manufacturing a metal gate electrode as described in item 1 of the scope of patent application ′, wherein the thickness of the cover layer is 1 000˜500 0 A. 4. The method for manufacturing a metal gate as described in item 1 of the scope of the patent application, wherein the gate dielectric layer is a gate oxide layer. 5 · The method for manufacturing a metal gate as described in item 1 of the scope of the patent application ′, wherein the polycrystalline silicon gate is lower than the gate opening by 50,000 to 20,000. 6 · The manufacturing method of the metal gate electrode as described in item 1 of the scope of the patent application, wherein the material of the metal layer is selected from the group consisting of: T i, W, Al, Ta, Cu, Co, Cr, Pt And the aforementioned alloy or nitride 0 7 · The manufacturing method of the metal gate as described in item 1 of the scope of patent application 0516-7142TWf; 90043; esmond.ptd Page 10 6. Scope of Patent Application ′ The flattening of! Is based on chemical mechanical polishing method. The method for manufacturing the metal interposer described in the UiC item further includes the following steps after removing the flattening of the ΪΠ: 9 by: = Please refer to item 8 of the patent scope, wherein after removing the cover layer, it further includes: In the following steps, in the manufacturing method, the shape area is used for the ion implantation of the implantation mask '... base ^ ^ t W ^ 8 ^ ^ ^ ^ ^ t ^ ^ Y ^ ^ A. The mask step further includes the following steps: An isolation structure is formed in the substrate to isolate the active area. 11. A method for manufacturing a metal gate, including the following steps, forming a mask layer on a semiconductor substrate; defining the mask layer to form a gate opening in the mask layer; A pair of dielectric spacers are formed on the side wall to reduce the width of the gate opening; a gate dielectric layer is formed on the substrate exposed by the gate opening; a polycrystalline stone layer is formed in the 4 gate opening; On the gate dielectric layer; engraving the polycrystalline silicon layer so that its surface is lower than the gate opening, and forming a polycrystalline silicon gate at the bottom of the interelectrode opening; forming a metal layer on the mask layer And fill the gate opening; β and, planarize the metal layer until the cover layer is exposed, thereby forming a metal gate on the polycrystalline stone gate. 12 · The manufacturer of the metal gate as described in item 11 of the scope of patent application_ Page 11 〇516.7142m; 90043; esmond.ptd The material is selected from the following groups: oxidized, lice fossils, i prepared ^ J 3 milk emulsion silicon, and the combination of the foregoing. # · The manufacturer of the metal gate electrode as described in item 11 of the scope of the patent application. \ The thickness of the cover layer in 4 is 1 0 0 0 ~ 5 0 0 Α. # · According to the manufacturer of the metal gate described in item 11 of the scope of the patent application, the gate dielectric layer is a gate oxide layer. 2. According to the manufacturer of the metal gate described in item 11 of the scope of the patent application, 'the polycrystalline stone gate in the eighth is lower than the gate opening 5 0 0 ~ 2 0 0 a. 16. The manufacturer of the metal gate described in item 11 of the scope of the patent application, 'wherein the material of the metal layer is selected from the group consisting of: Ti, 1 Ta, Cu, Co,' pt, and the foregoing Alloys or nitrides 17. The method for manufacturing a metal gate as described in the item 丨 丨 of the scope of the patent application, wherein the planarization of the metal layer is performed by a chemical mechanical polishing method. 18. The method for manufacturing a metal gate according to item 11 of the scope of the patent application, wherein the planarization of the metal layer further includes the following steps: removing the mask layer. 19. The method for manufacturing a metal gate electrode as described in item 18 of the scope of the patent application, wherein the method further includes the following steps after removing the mask layer: the metal gate electrode is used to fabricate the mask to perform ion distribution, A source / drain region is formed in the substrate. / Soil-2〇. The method for manufacturing a metal gate electrode as described in item 18 of the scope of patent application, wherein the method further includes the following steps before forming the cover layer: forming an isolation structure in the substrate to isolate the active area. 〇516.7142Wf; 90043; esmond.ptd Page 12