TW512608B - Receiver and method for receiving fast ethernet data without baseline wander effect - Google Patents
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512608512608
五、發明說明(1) -------- 【發明說明】 【發明領域】 本發明係關於快速乙太網路(Fast Ethernet)接收 器’特別是關於不具基準線飄移之快速乙太網路接收哭盥 接收方法。 〃 【習知技術】 在1 00Mbps的快速乙太網路應用中,資料經由 NRZ(Non-Re turn-to-Zero)至NRZI(Non-Re turn-to-ZeroV. Description of the invention (1) -------- [Explanation of the invention] [Field of the invention] The present invention relates to a Fast Ethernet receiver 'especially to a fast Ethernet without a baseline drift. Internet receiving crying receiving method.习 [Knowledge technology] In 100Mbps fast Ethernet applications, data passes from NRZ (Non-Re turn-to-Zero) to NRZI (Non-Re turn-to-Zero)
Inverse)轉換成MLT3(Multi-Level Transitl〇n 3)碼。該 MLT3碼經由發射器(transmitter)之變壓器(transf〇rme^ AC I馬合(couple)而送出信號,且該信號經過傳輸線 (cable)傳送到接收端(receiver)的變壓器。由於社丁3碼 波形之直流準位是不均等(DC unbalanced)的,且變壓器 會將傳送彳s號之直流成分濾掉,造成接收到之信號的直流 準位會隨著傳送信號之式樣(pa 11 e rη)飄移,即所謂基準 線飄移現象(baseline wander effect)。 圖1顯示一般快速乙太網路之接收器的架構圖。如該 圖所示’該接收器1 0 〇包含一直流偏移補償器(d c 〇 f ^ s e七 compensator) 11 0 、一 力口;^器(8(1(161〇120 、一等 ^匕器 (equal izer) 1 30、一 切換器(s 1 i ce r) 1 4 0、—MLT3 碼解碼 器(MLT3 decoder)150、以及一NRZ 至 NRZI 轉換器i6〇。加 法器1 20將輸入信號RX與直流偏移補償器1丨〇所提供之直流 偏移量相加,並輸出已補償直流偏移量的信號至等化哭 1 3 0。亦即’信號在進入等化Is 1 3 0之前,先將輸入信號加Inverse) into MLT3 (Multi-Level Transit 3) code. The MLT3 code is transmitted through a transmitter transformer (transforme AC I coupler) of the transmitter, and the signal is transmitted to the transformer of the receiver via the cable. Since the company ’s 3 code The DC level of the waveform is DC unbalanced, and the transformer will filter the DC component of the transmitted signal 彳 s, causing the DC level of the received signal to follow the pattern of the transmitted signal (pa 11 e rη) Drift, the so-called baseline wander effect. Figure 1 shows the architecture diagram of a general fast Ethernet receiver. As shown in the figure, 'the receiver 100 includes a DC offset compensator ( dc 〇f ^ se seven compensator) 11 0, a force mouth; ^ device (8 (1 (161〇120, first ^ equal device) 1 30, a switch (s 1 i ce r) 1 4 0, —MLT3 decoder 150 (MLT3 decoder) 150, and an NRZ to NRZI converter i6〇. The adder 1 20 adds the input signal RX to the DC offset provided by the DC offset compensator 1 丨 〇, And output the compensated DC offset signal to the equalization cry 1 3 0. 'Before entering the equalization signal Is 1 3 0, first input signal is applied
512608 五、發明說明(2) i:個預估,以消除基準線飄移現象所造成之直流 以避免忒基準線飄移現象對接收器之特性造成影 音。而等化器1 3 0之作用是消除僂於綠 dnter-Sy.bol I n t er f er ence . f^ ^ 切爐突1 M姑从A > / 1 S 1 )。專化後的信號經過 轉換成南低準位的信號後,再經 M50與至NRZI轉換器160後,即產生傳輸的資料解 但疋,一般的快速乙太網路接收器均需提供一 移補償器來預估直流偏移量,捭加 ’、 ’丨L ^ 曰加了该接收器之複雜度。 【發明概要】 有 至 NRZI 藉以利 同時達 為 X3X3 一 早兀, 信號延 號;一 消除電 之輸出 (0、+1 出信號 宴於上述的問題,本發明^^ n512608 V. Description of the invention (2) i: an estimate to eliminate the DC caused by the baseline drift phenomenon to avoid that the baseline drift phenomenon will affect the receiver's characteristics. The function of the equalizer 130 is to eliminate the green dnter-Sy.bol I n t er f er ence. F ^ ^ Cut the furnace protrusion 1 M from A > / 1 S 1). The specialized signal is converted to a low-level signal, and then the M50 and the NRZI converter 160 are used to generate the transmitted data solution. However, ordinary fast Ethernet receivers need to provide a shift. The compensator is used to estimate the DC offset. Adding ',' 丨 L ^ adds the complexity of the receiver. [Summary of the invention] It is to NRZI to achieve X3X3 at the same time, early signal, signal extension; one to eliminate the output of electricity (0, +1 signal to meet the above problems, the present invention ^^ n
絲π吳·Γ 的是提供-種將NRZ 轉換裔配置於專化之箭沾h、土 I刖的快速乙太網路接收器, 用NRZ至NRZI轉換器的特性消 條队 ^MD^7T „ 竹庄/自除基準線飄移現象並 到N R Z至N R Z I轉換的功能。 達成上述目的,本發明之接收 係用來接收輸入信號,並將兮仏 ^逐我去 ^ ^ ^ 將4輪入信號減去該輪入 遲一取樣週期的信號,產生 等化器,係接收延遲減法單元二•成7刀之取樣信 I線所造成之碼際干擾信並 卞刀換态,係接收箄 卜哭、 信號,並將該輸出信號切換成 、口口 俠成MLT3碼的三個位準 、-1),以及,一 M L T 3解碼哭 _ 听θ au ’係接收切拖哭之私 ,並將該輸出信號解碼。 叹刀換μ之輪 其中延遲減法單元 入7虎,並根據第 根據本發明快速乙太網路接收器, 包含:一第一取樣保持電路,係接&輸What π Wu · Γ provides is a fast Ethernet receiver that configures the NRZ conversion line to the specialized arrow and soil I 刖, and uses the characteristics of the NRZ to NRZI converter to eliminate the line ^ MD ^ 7T „The function of Zhuzhuang / self-division baseline drift and conversion from NRZ to NRZI. To achieve the above purpose, the receiver of the present invention is used to receive the input signal, and it will go ^^ by me ^ ^ ^ 4 rounds into the signal The signal which is one sample cycle later is subtracted to generate an equalizer, which is to receive the intersymbol interference signal caused by the delay subtraction unit II • 7-sampling letter I line and change the state of the knife, and to receive the cry , Signal, and switch the output signal to three levels of MLT3 code, -1), and a MLT 3 decoding cry The output signal is decoded. The delay subtraction unit enters 7 tigers, and the fast Ethernet receiver according to the present invention includes: a first sample-and-hold circuit, which is connected to the &
512608512608
一取樣脈衝對輸入 一第二取樣保持電 樣信號,並根據第 樣,並輸出第二取 樣信號與第二取樣 信號後產生不具直 k $虎進行取樣,並輪 路,係接收第一取樣 二取樣脈衝對該第一 樣信號;以及一減法 信號,並將第一取樣 流成分之取樣信號。 出第一取樣信號; 保持電路之第一取 取樣信號進行取 器,係接收第一取 信號減去第二取樣 【實施例] 快速乙太網路接收器之 以下參考圖式詳細說明本發明 架構與實施例。 由於基準線飄移的變化是緩慢的,故相鄰兩個取樣 (sample)值所遭受到的直流偏移量幾乎相同。所以,相鄰 兩個取樣值相減後,可視為不具基準線飄移(bwdine wandef free)的信號。本發明即利用NRZ至NRZI轉換過程 中所隱含觔後相鄰兩點相減的特性,而將這一部分之運算 移至等化器之前處理。 # 圖2所示為本發明快速乙太網路接收器之架構圖。如 該圖所示’該快速乙太網路接收器丨〇 (以簡 Η遲減法單元(…運算)20、一等化器’3〇、一 :): 器40、以及一MLT3碼解碼器50。該接收器1 〇係將習知接收 器(麥考圖1 )後端之NRZ-NRZ I轉換器之功能移至前端,且 該延遲減法單元20的功能包含NRZ-NRZI的轉換功能。由於 輸入信號RX+與RX-在進入等化器3〇之前先經過延遲減法單 元2 0,藉由該延遲減法單元2 〇將時序上相鄰之兩點的信號A sampling pulse is input to a second sampling and holding electric sample signal, and according to the first sample, and outputting the second sampling signal and the second sampling signal, the sample is generated without a straight k $ tiger, and is rotated, and the first sampling second is received. The sampling pulse is the first signal; and a subtraction signal, and the sampling signal of the first sampling stream component. The first sampling signal is obtained; the first sampling signal of the holding circuit is used to perform the fetching, and the first sampling signal is subtracted from the second sampling. [Embodiment] The following reference diagram of a fast Ethernet receiver will explain the architecture of the present invention in detail. And Examples. Since the change in the baseline drift is slow, the DC offsets experienced by two adjacent sample values are almost the same. Therefore, after subtracting two adjacent sample values, it can be regarded as a signal without bwdine wandef free. In the present invention, the characteristic of subtraction of two adjacent points hidden behind the tendons implicit in the NRZ to NRZI conversion process is used, and the operation of this part is moved to the equalizer before processing. # Figure 2 shows the architecture of the fast Ethernet receiver of the present invention. As shown in the figure, 'the fast Ethernet receiver 丨 〇 (in a simple subtraction unit (... operation) 20, first equalizer' 30, one :): device 40, and an MLT3 code decoder 50. The receiver 10 moves the function of the NRZ-NRZ I converter at the back end of the conventional receiver (Micau Figure 1) to the front end, and the function of the delay subtraction unit 20 includes the conversion function of NRZ-NRZI. Because the input signals RX + and RX- pass through the delay subtraction unit 20 before entering the equalizer 30, the signals of two points adjacent to each other in time are transmitted by the delay subtraction unit 20.
第7頁 512608 五、發明說明(4) 相減’而消除輸人信號RX+_X—的直 等化器3〇、切換器4◦、以歷 ^月匕與習知的接收器(參考明相同,在此不再重複說η 。以下僅針對延遲減法單元2〇的架構與功能詳細說明。 样軒本發明接收器1 〇之延遲減法單元20係用來將相鄰兩取 樣”、、占之一^唬相減後輸出,即所謂之卜ζ — i運算。因此,士 圖2所示,該延遲減法單元2〇包含第一取樣保持(Sampie° aM hold)單兀21、第二取樣保持單元22、類比數位轉換 器以及加法器24與25。第一取樣保持單元以係接收輪 入信號RX+與RX—,並以適當取樣脈衝CK1對該等輸入信號』 RX+與RX-進行取樣,且將取樣後之信號RX +,與以-,傳給^ 二取樣保持單元22與加法器24與25。第二取樣保持單元22 則接收信號RX +’與RX —,,並以適當取樣脈衝CK2對該等信 號RXV與RX-’進行取樣,且將取樣且反向後之信號RX + I,與 RX-π傳給加法器24與25。由於信號RX + "與RX-”經過兩次取 樣動作’所以信號RX + "與!^ —”會延遲信號RX +,與]^ —,一個 取樣週期。經過加法器24與25相加後之信號則傳給類比數 位轉換器2 3進行數位化。類比數位轉換器2 3產生之數位信 號則傳給等化器3〇。取樣脈衝CK1與CK2之頻率係高於快速 乙太網路之傳輸頻率。 圖3(A)與圖3(B)分別為輸入信號經過延遲減法單元20 前後的波形,其中輸入信號經過150米CAT. 5電纜線之IDLE 式樣的M L T 3波形。圖4 (A)與圖4 (B)分別為輸入信號經過延 遲減法單元2 0前後的波形,其中輸入信號經過1 5 0米CAT· 5Page 7 512608 V. Description of the invention (4) Subtracting 'to eliminate the input signal RX + _X— a direct equalizer 30, a switch 4, a calendar receiver and a conventional receiver (refer to the The same, I will not repeat it here. The following only describes the structure and function of the delay subtraction unit 20 in detail. The delay subtraction unit 20 of the receiver 10 of the present invention is used to sample two adjacent samples. One is the output after subtraction, which is the so-called ζ-i operation. Therefore, as shown in FIG. 2, the delay subtraction unit 20 includes a first sample hold (Sampie ° aM hold) unit 21 and a second sample. The holding unit 22, the analog-to-digital converter and the adders 24 and 25. The first sample-and-hold unit receives the incoming signals RX + and RX-, and samples the input signals "RX + and RX-" with an appropriate sampling pulse CK1. The sampled signal RX +, and-are passed to the second sample-and-hold unit 22 and the adders 24 and 25. The second sample-and-hold unit 22 receives the signals RX + 'and RX —, and uses appropriate sampling pulses. CK2 samples the signals RXV and RX- ', and samples the signals and reverses them. No. RX + I and RX-π are passed to the adders 24 and 25. Since the signals RX + " and RX- "go through two sampling operations', the signals RX + " and! ^ —" Will delay the signal RX +, And] ^ —, a sampling period. The signals after adding by the adders 24 and 25 are passed to the analog-to-digital converter 23 for digitization. The digital signals generated by the analog-to-digital converter 23 are passed to the equalizer 3 〇. The frequency of the sampling pulses CK1 and CK2 is higher than the transmission frequency of the fast Ethernet. Figure 3 (A) and Figure 3 (B) are the waveforms of the input signal before and after the delay subtraction unit 20, in which the input signal passes 150 CAT. 5 cable with IDLE MLT 3 waveforms. Figures 4 (A) and 4 (B) are the waveforms before and after the input signal passes through the delay subtraction unit 20, among which the input signal passes through 150 meters CAT · 5
第8頁 512608 五、發明說明(5) 電总線之Ki 1 ler式樣的MlT3波形。從圖3與圖4即可清禁砉 到’輸入信號經過延遲減法單元後,其峰值對;均二 ^ i :ak:t::average p〇wer rati〇)大幅降低,使得後續 ^ 為簡化。如圖3 (A )所示,在經過延遲減法單元2 0 其峰值約為。.6;而如圖3⑻所示遲咸 遲減,早U0後的波形’其峰值約為〇2。而如圖4(a)所 :如=過延遲減法單元2〇前的波形,其峰值約為"; :::·?所示,在經過延遲減法單元2。後的波形,其峰 元將ΪΠΓ信號RX在進入等化器之前先經過延遲減法單 以消“準ΪΪ之兩點的信號㈣,而消除直流成分,藉 :二應被消除之緣故,進入等 等,較為容易。復(tlmlng re⑶very)以及等化動作 圖5所示為本發明不具基準線 收方法流程圖。如該圖所示,該接收;^ 步驟S5 0 0 :開始。 匕3下列步驟: 步驟S5 0 2 :延遲減法步驟。該步驟 號’並將該輸入信號減去該輸入信 遲入信 的信號’產生不具直流成分之取樣信㉟。-取樣保持週期 v驟S 5 0 4 ·消除碼際干擾步驟。 法單元輸出之取樣信號,並消除電繞線;減 512608 五、發明說明(6) 擾0 步驟S5 0 6 : MLT3碼切換步驟。該步驟係接收等化哭之 輸出信號,並將該輸出信號切換成MLT3碼之三個準位: 步驟S5 08 : MLT3解碼步驟。該步驟係接收切換器 出信號’並將該輸出信號解碼。 11 而在步驟5 0 2之延遲減法步驟中,係包含一第一取樣 保持步驟,係接收輸入信號,並根據第一取樣脈衝對輸7入 仏號進行取樣,並輸出第一取樣信號;一第二取樣保持步 驟,係接收第一取樣保持電路之第一取樣信號,並根據第 二取樣脈衝對該第一取樣信號進行取樣,並輸出第二取樣 信號;一減法步驟,係接收第一取樣信號與第二取樣信 號’並將第一取樣信號減去第二取樣信號後產生不具直流 成分之取樣信號;以及一類比數位轉換步驟,係將不具直 流成分之取樣信號數位化。 當然,若第二取樣保持步驟中係產生反向之第二取樣 信號,則減法步驟可變更為加法步驟,將第一取樣信號加 上第二取樣#號後產生不具直流成分之取樣信號。 以上雖以實施例說明本發明,但並不因此限定本發明 之範圍’只要不脫離本發明之要旨,該行業者^進行各種 變形或變更。Page 8 512608 V. Description of the invention (5) Ki 1 ler-like MlT3 waveform of the electric bus. From Fig. 3 and Fig. 4, it is possible to clear the confinement until the input signal passes through the delay subtraction unit, and its peak pair is reduced; ^ i: ak: t :: average p〇wer rati〇) is greatly reduced, making subsequent ^ simplified . As shown in FIG. 3 (A), after passing through the delay subtraction unit 20, its peak value is approximately. .6; and as shown in Figure 3 (a), the peak value of the waveform after early U0 is about 0.2. As shown in FIG. 4 (a): if the waveform before the delay delay subtraction unit 20 has a peak value of about "; :::?, It passes through the delay subtraction unit 2. After the waveform, its peak element will be ΪΠΓ signal RX through the delay subtraction order to cancel the "two points of the signal ㈣" before entering the equalizer, and eliminate the DC component. By: two should be eliminated, enter, etc. It is easy to wait. Tlmlng reCDvery and equalization action Figure 5 shows the flowchart of the method of the present invention without a baseline collection. As shown in the figure, the receiving; ^ Step S50 0 0: Start. 3 The following steps : Step S5 0 2: Delayed subtraction step. The step number 'and subtracts the input signal from the input signal's late incoming signal' produces a sampling signal with no DC component.-Sampling and holding period v 5 4 4 · Cancel Inter-symbol interference step. Sampling signal output by the legal unit and eliminating electrical windings; minus 512608 V. Description of the invention (6) Disturbance 0 Step S5 0 6: MLT3 code switching step. This step is to receive the output signal of equalization cry, And the output signal is switched to the three levels of the MLT3 code: Step S5 08: MLT3 decoding step. This step is to receive the signal from the switch and decode the output signal. 11 And the delay subtraction step in step 5 0 2 Middle It includes a first sample-and-hold step that receives the input signal and samples the input 7 input signal according to the first sampling pulse and outputs the first sample signal; a second sample-and-hold step that receives the first sample-and-hold circuit. A first sampling signal, and sampling the first sampling signal according to a second sampling pulse, and outputting the second sampling signal; a subtraction step, receiving the first sampling signal and the second sampling signal, and subtracting the first sampling signal The second sampling signal is removed to generate a sampling signal without a DC component; and an analog digital conversion step is to digitize the sampling signal without a DC component. Of course, if the second sampling and holding step is to generate a reverse second sampling signal Then, the subtraction step can be changed to an addition step, and the first sampling signal is added to the second sampling # number to generate a sampling signal without a DC component. Although the present invention has been described with the embodiment, the scope of the present invention is not limited thereby. As long as they do not depart from the gist of the present invention, those skilled in the art will make various modifications or changes.
第10頁 512608 圖式簡單說明 【圖式之簡要說明】 圖1為習知快速乙太網路接收器之架構。 圖2為本發明快速乙太網路接收器之架構。 圖3為IDLE式樣之(RX+ - RX-)的信號,复 遲減法單元前的信號,(B)為延遲減法單元、中(A)為延 圖4為Killer式樣之(RX+ — rx — )的传的信號。 延遲減法單元前的信號,(B)為延遲減法;\其中(A)為 、圖5為本發明不具基準線飄移之恤^ ,兀後的信號。 法流程圖。 、速乙太網路接收方 圖式編號 22 25 4050 快速乙太網路接收器 延遲減法單元 °° 取樣保持電路 數位類比轉換器 加法器 等化器 切換器 MLT3解碼器 $ η頁Page 10 512608 Brief description of the diagram [Brief description of the diagram] Figure 1 shows the architecture of a conventional fast Ethernet receiver. FIG. 2 is a structure of a fast Ethernet receiver according to the present invention. Figure 3 shows the signals of the IDLE pattern (RX +-RX-), the signals before the complex delay subtraction unit, (B) is the delay subtraction unit, and (A) is the extension. Figure 4 shows the (RX + — rx —) of the Killer pattern. Signal. The signal before the delay subtraction unit (B) is the delay subtraction; \ where (A) is, Figure 5 is the signal after the shirt without reference line drift according to the present invention. Method flow chart. Speed Ethernet Receiver Pattern Number 22 25 4050 Fast Ethernet Receiver Delay Subtraction Unit °° Sample-and-Hold Circuit Digital Analog Converter Adder Equalizer Switcher MLT3 Decoder $ ηPage
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Cited By (2)
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---|---|---|---|---|
US7298173B1 (en) | 2004-10-26 | 2007-11-20 | Marvell International Ltd. | Slew rate control circuit for small computer system interface (SCSI) differential driver |
TWI392267B (en) * | 2005-03-10 | 2013-04-01 | Qualcomm Inc | Methods and apparatus for providing linear erasure codes |
-
2001
- 2001-02-13 TW TW90103200A patent/TW512608B/en not_active IP Right Cessation
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7298173B1 (en) | 2004-10-26 | 2007-11-20 | Marvell International Ltd. | Slew rate control circuit for small computer system interface (SCSI) differential driver |
US7579873B1 (en) | 2004-10-26 | 2009-08-25 | Marvell International Ltd. | Slew rate control circuit for small computer system interface (SCSI) differential driver |
TWI392267B (en) * | 2005-03-10 | 2013-04-01 | Qualcomm Inc | Methods and apparatus for providing linear erasure codes |
US8640009B2 (en) | 2005-03-10 | 2014-01-28 | Qualcomm Incorporated | Methods and apparatus for providing linear erasure codes |
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