TW512608B - Receiver and method for receiving fast ethernet data without baseline wander effect - Google Patents

Abstract

A receiver and method for receiving fast ethernet data without baseline wander effect is disclosed. The receiver receives the data coupled by a transformer. The receiver includes a subtraction unit for receiving the input signal and generating sample signals without DC offset. An equalizer is used for receiving the sample signals and eliminating the inter-symbol interference (ISI) causing by the cable and a slicer is used for transfer the output signal of the equalizer into the signal with 3 levels. Then, a MLT3 decoder is employed for decoding the output signals of the slicer to generate transmission data. Due to that the DC offset of the input signal is eliminated by the subtraction unit, the baseline wander effect is deleted and the peak-to-average power ratio is reduced, so the implement of the equalizer, slicer and MLT3 decoder is easier than prior art.

Description

512608

V. Description of the invention (1) -------- [Explanation of the invention] [Field of the invention] The present invention relates to a Fast Ethernet receiver 'especially to a fast Ethernet without a baseline drift. Internet receiving crying receiving method.习 [Knowledge technology] In 100Mbps fast Ethernet applications, data passes from NRZ (Non-Re turn-to-Zero) to NRZI (Non-Re turn-to-Zero)

Inverse) into MLT3 (Multi-Level Transit 3) code. The MLT3 code is transmitted through a transmitter transformer (transforme AC I coupler) of the transmitter, and the signal is transmitted to the transformer of the receiver via the cable. Since the company ’s 3 code The DC level of the waveform is DC unbalanced, and the transformer will filter the DC component of the transmitted signal 彳 s, causing the DC level of the received signal to follow the pattern of the transmitted signal (pa 11 e rη) Drift, the so-called baseline wander effect. Figure 1 shows the architecture diagram of a general fast Ethernet receiver. As shown in the figure, 'the receiver 100 includes a DC offset compensator ( dc 〇f ^ se seven compensator) 11 0, a force mouth; ^ device (8 (1 (161〇120, first ^ equal device) 1 30, a switch (s 1 i ce r) 1 4 0, —MLT3 decoder 150 (MLT3 decoder) 150, and an NRZ to NRZI converter i6〇. The adder 1 20 adds the input signal RX to the DC offset provided by the DC offset compensator 1 丨 〇, And output the compensated DC offset signal to the equalization cry 1 3 0. 'Before entering the equalization signal Is 1 3 0, first input signal is applied

512608 V. Description of the invention (2) i: an estimate to eliminate the DC caused by the baseline drift phenomenon to avoid that the baseline drift phenomenon will affect the receiver's characteristics. The function of the equalizer 130 is to eliminate the green dnter-Sy.bol I n t er f er ence. F ^ ^ Cut the furnace protrusion 1 M from A > / 1 S 1). The specialized signal is converted to a low-level signal, and then the M50 and the NRZI converter 160 are used to generate the transmitted data solution. However, ordinary fast Ethernet receivers need to provide a shift. The compensator is used to estimate the DC offset. Adding ',' 丨 L ^ adds the complexity of the receiver. [Summary of the invention] It is to NRZI to achieve X3X3 at the same time, early signal, signal extension; one to eliminate the output of electricity (0, +1 signal to meet the above problems, the present invention ^^ n

What π Wu · Γ provides is a fast Ethernet receiver that configures the NRZ conversion line to the specialized arrow and soil I 刖, and uses the characteristics of the NRZ to NRZI converter to eliminate the line ^ MD ^ 7T „The function of Zhuzhuang / self-division baseline drift and conversion from NRZ to NRZI. To achieve the above purpose, the receiver of the present invention is used to receive the input signal, and it will go ^^ by me ^ ^ ^ 4 rounds into the signal The signal which is one sample cycle later is subtracted to generate an equalizer, which is to receive the intersymbol interference signal caused by the delay subtraction unit II • 7-sampling letter I line and change the state of the knife, and to receive the cry , Signal, and switch the output signal to three levels of MLT3 code, -1), and a MLT 3 decoding cry The output signal is decoded. The delay subtraction unit enters 7 tigers, and the fast Ethernet receiver according to the present invention includes: a first sample-and-hold circuit, which is connected to the &

512608

A sampling pulse is input to a second sampling and holding electric sample signal, and according to the first sample, and outputting the second sampling signal and the second sampling signal, the sample is generated without a straight k $ tiger, and is rotated, and the first sampling second is received. The sampling pulse is the first signal; and a subtraction signal, and the sampling signal of the first sampling stream component. The first sampling signal is obtained; the first sampling signal of the holding circuit is used to perform the fetching, and the first sampling signal is subtracted from the second sampling. [Embodiment] The following reference diagram of a fast Ethernet receiver will explain the architecture of the present invention in detail. And Examples. Since the change in the baseline drift is slow, the DC offsets experienced by two adjacent sample values are almost the same. Therefore, after subtracting two adjacent sample values, it can be regarded as a signal without bwdine wandef free. In the present invention, the characteristic of subtraction of two adjacent points hidden behind the tendons implicit in the NRZ to NRZI conversion process is used, and the operation of this part is moved to the equalizer before processing. # Figure 2 shows the architecture of the fast Ethernet receiver of the present invention. As shown in the figure, 'the fast Ethernet receiver 丨 〇 (in a simple subtraction unit (... operation) 20, first equalizer' 30, one :): device 40, and an MLT3 code decoder 50. The receiver 10 moves the function of the NRZ-NRZ I converter at the back end of the conventional receiver (Micau Figure 1) to the front end, and the function of the delay subtraction unit 20 includes the conversion function of NRZ-NRZI. Because the input signals RX + and RX- pass through the delay subtraction unit 20 before entering the equalizer 30, the signals of two points adjacent to each other in time are transmitted by the delay subtraction unit 20.

Page 7 512608 V. Description of the invention (4) Subtracting 'to eliminate the input signal RX + _X— a direct equalizer 30, a switch 4, a calendar receiver and a conventional receiver (refer to the The same, I will not repeat it here. The following only describes the structure and function of the delay subtraction unit 20 in detail. The delay subtraction unit 20 of the receiver 10 of the present invention is used to sample two adjacent samples. One is the output after subtraction, which is the so-called ζ-i operation. Therefore, as shown in FIG. 2, the delay subtraction unit 20 includes a first sample hold (Sampie ° aM hold) unit 21 and a second sample. The holding unit 22, the analog-to-digital converter and the adders 24 and 25. The first sample-and-hold unit receives the incoming signals RX + and RX-, and samples the input signals "RX + and RX-" with an appropriate sampling pulse CK1. The sampled signal RX +, and-are passed to the second sample-and-hold unit 22 and the adders 24 and 25. The second sample-and-hold unit 22 receives the signals RX + 'and RX —, and uses appropriate sampling pulses. CK2 samples the signals RXV and RX- ', and samples the signals and reverses them. No. RX + I and RX-π are passed to the adders 24 and 25. Since the signals RX + " and RX- "go through two sampling operations', the signals RX + " and! ^ —" Will delay the signal RX +, And] ^ —, a sampling period. The signals after adding by the adders 24 and 25 are passed to the analog-to-digital converter 23 for digitization. The digital signals generated by the analog-to-digital converter 23 are passed to the equalizer 3 〇. The frequency of the sampling pulses CK1 and CK2 is higher than the transmission frequency of the fast Ethernet. Figure 3 (A) and Figure 3 (B) are the waveforms of the input signal before and after the delay subtraction unit 20, in which the input signal passes 150 CAT. 5 cable with IDLE MLT 3 waveforms. Figures 4 (A) and 4 (B) are the waveforms before and after the input signal passes through the delay subtraction unit 20, among which the input signal passes through 150 meters CAT · 5

Page 8 512608 V. Description of the invention (5) Ki 1 ler-like MlT3 waveform of the electric bus. From Fig. 3 and Fig. 4, it is possible to clear the confinement until the input signal passes through the delay subtraction unit, and its peak pair is reduced; ^ i: ak: t :: average p〇wer rati〇) is greatly reduced, making subsequent ^ simplified . As shown in FIG. 3 (A), after passing through the delay subtraction unit 20, its peak value is approximately. .6; and as shown in Figure 3 (a), the peak value of the waveform after early U0 is about 0.2. As shown in FIG. 4 (a): if the waveform before the delay delay subtraction unit 20 has a peak value of about "; :::?, It passes through the delay subtraction unit 2. After the waveform, its peak element will be ΪΠΓ signal RX through the delay subtraction order to cancel the "two points of the signal ㈣" before entering the equalizer, and eliminate the DC component. By: two should be eliminated, enter, etc. It is easy to wait. Tlmlng reCDvery and equalization action Figure 5 shows the flowchart of the method of the present invention without a baseline collection. As shown in the figure, the receiving; ^ Step S50 0 0: Start. 3 The following steps : Step S5 0 2: Delayed subtraction step. The step number 'and subtracts the input signal from the input signal's late incoming signal' produces a sampling signal with no DC component.-Sampling and holding period v 5 4 4 · Cancel Inter-symbol interference step. Sampling signal output by the legal unit and eliminating electrical windings; minus 512608 V. Description of the invention (6) Disturbance 0 Step S5 0 6: MLT3 code switching step. This step is to receive the output signal of equalization cry, And the output signal is switched to the three levels of the MLT3 code: Step S5 08: MLT3 decoding step. This step is to receive the signal from the switch and decode the output signal. 11 And the delay subtraction step in step 5 0 2 Middle It includes a first sample-and-hold step that receives the input signal and samples the input 7 input signal according to the first sampling pulse and outputs the first sample signal; a second sample-and-hold step that receives the first sample-and-hold circuit. A first sampling signal, and sampling the first sampling signal according to a second sampling pulse, and outputting the second sampling signal; a subtraction step, receiving the first sampling signal and the second sampling signal, and subtracting the first sampling signal The second sampling signal is removed to generate a sampling signal without a DC component; and an analog digital conversion step is to digitize the sampling signal without a DC component. Of course, if the second sampling and holding step is to generate a reverse second sampling signal Then, the subtraction step can be changed to an addition step, and the first sampling signal is added to the second sampling # number to generate a sampling signal without a DC component. Although the present invention has been described with the embodiment, the scope of the present invention is not limited thereby. As long as they do not depart from the gist of the present invention, those skilled in the art will make various modifications or changes.

Page 10 512608 Brief description of the diagram [Brief description of the diagram] Figure 1 shows the architecture of a conventional fast Ethernet receiver. FIG. 2 is a structure of a fast Ethernet receiver according to the present invention. Figure 3 shows the signals of the IDLE pattern (RX +-RX-), the signals before the complex delay subtraction unit, (B) is the delay subtraction unit, and (A) is the extension. Figure 4 shows the (RX + — rx —) of the Killer pattern. Signal. The signal before the delay subtraction unit (B) is the delay subtraction; \ where (A) is, Figure 5 is the signal after the shirt without reference line drift according to the present invention. Method flow chart. Speed Ethernet Receiver Pattern Number 22 25 4050 Fast Ethernet Receiver Delay Subtraction Unit °° Sample-and-Hold Circuit Digital Analog Converter Adder Equalizer Switcher MLT3 Decoder $ ηPage

Claims (1)

Sixth, the scope of patent application for fast reading without baseline drift is transmitted through the electric I line and is received by the transformer receiver. The receiver includes: a port number, a delay subtraction unit for the receiver. The input signal is subtracted from the input signal to enter the magic tiger, and the sampling signal without the DC component is generated; the signal of the sample holding period is specialized to receive the aforementioned delay minus sign, and eliminate the above caused by the cable. The sample letter from Shima Jigan was written; the output signal of the equalizer was received, and the round field was sent. Bluff switches to the three levels of the MLT3 code; and,-the MLT3 decoder 'receives the aforementioned cut-out signal for decoding. The first sample-and-hold circuit of KJJ: Second ?: Drifting Fast Net "first sample-and-hold circuit, which receives the aforementioned input signal, and samples other turn-in signals according to the sampling pulse, and outputs the first sampling orange number; 7 # A second sample-and-hold circuit receives the first sampling signal of the first sample-and-hold circuit, samples the first sampling signal according to the second sampling pulse, and rotates the second sampling signal; and 〇 a subtraction The device receives the first sampling signal and the second sampling signal #U 'and subtracts the second sampling signal from the first sampling signal to generate the aforementioned sampling signal without a DC component. Page 12 512608 VI. Patent Application Scope 3 · For the fast Ethernet reception without reference line drift in the scope of the patent application, where the aforementioned delay subtraction unit includes ·· a first sample-and-hold circuit, which receives the aforementioned input signal and The signal is sampled in turn, and the first sampling signal is output. A second sample-and-hold circuit receives the first sample-and-hold circuit. A sampling signal 'and sampling the first sampling signal according to a second sampling pulse to generate a second sampling signal in reverse; and σ an adder' receiving the first sampling signal and the second sampling signal 'and Θ said the first sampling signal and the second sampling signal are added to generate the aforementioned sampling signal with no DC component. • If the patent application scope is 2 or 3, fast Ethernet without reference line drift, `` Broadway Received as '' The aforementioned delay subtraction unit further includes an analog digital conversion to 'receives the aforementioned sampling signal without a DC component and digitizes it. • A fast Ethernet receiving method without baseline drift. It receives, transmits, and transmits signals from a cable and passes the input signal of a transformer | Machine. The receiving method includes the following steps: A delay subtraction step, which uses To receive the aforementioned input signal, and subtract the input signal from the round-in signal by delaying a signal of a sample-and-hold period to generate a sampling signal without a DC component; and a step of eliminating inter-symbol interference, receiving the output of the aforementioned delayed subtraction unit Page 13 512608 Supplement 90103200 VI. Apply for the sampling signal of the amended patent scope and eliminate the inter-symbol interference caused by the aforementioned cable; A MLT3 code switching step is to receive the output signal of the aforementioned equalizer and switch the output signal Three levels of MLT3 code; and -MLT3 decoding step is to receive the output signal of the switch and decode the output signal. 6 · As stated in claim 5 of the patent scope of the fast Ethernet reception method without baseline drift, wherein the aforementioned delay subtraction step includes: a first sample-and-hold step, which receives the aforementioned input signal, and Pulse the sampling of the above-mentioned turn-in signal and output the first sampling signal; 々 a first holding step, receiving the first sampling signal of the first sampling-holding circuit, and performing the first sampling signal according to the second sampling pulse Sampling, and outputting a second sampling signal; and a subtraction step, which receives the first sampling signal and the second sampling signal, and subtracts the second sampling signal from the first sampling signal to generate a pre-^^ with no DC component. Of the sampled signal. • As described in claim 5 of the patent scope of the fast B channel receiving method without baseline drift, wherein the aforementioned delay subtraction step includes: a first sampling and holding step of the first network of the first sampling pulse to the aforementioned input signal; The input signal is sampled according to the input signal, and the first sample and the second sample and hold steps are output, and the first sample and hold circuit is received. Page 14 512608 6. The first sampling signal in the scope of patent application, and the first sampling signal is sampled according to the second sampling pulse, and the second sampling number is generated in the reverse direction. The sampling signal and the second sampling signal, and the first sampling signal and the first sampling number are added to generate another sampling signal without a DC component. 8. The method for fast Ethernet reception without baseline drift, as described in item 6 or 7 of the scope of patent application, wherein the aforementioned delay subtraction step further includes an analog-to-digital conversion step, which digitizes the aforementioned sampling signal without a DC component. Page 15