511092511092
五、發明說明（1) 【發明領域】 本發明係有關於一種記憶體之測試修補分析方法，特 別係有關於一種運用合併電路〔merge circui t〕之^己降 體測試修補分析方法。 ° & 【先前技術】 習知記憶體’如動態隨機存取記憶體〔dmm〕、靜態 隨機存取記憶體〔SRAM〕、快閃記憶體〔f iash memory〕、雙倍資料速率動態隨機存取記憶體〔D〇uMe Data Rate DRAM，DDR DRAM〕或含記憶體之系統單晶片 〔soc〕等，係以半導體製程製造之。例如複數個DIJM記 憶體晶片〔由數百至上千之數〕、係以積體電路型態形成於 一晶圓〔wafer〕，如6吋、8吋或1 2吋之晶圓，但隨著電 子元件之微小而複雜化以及製程之精進，記憶體之容量亦 同步擴大，如由習知之4Mb或16Mb DRAM擴展為64Mb、 128Mb 、 256Mb之DRAM ，甚至DDR DRAM 。 當一記憶體之容量愈來愈大時，不可避免地在半導體 製造上產生錯誤的記憶體胞室〔memory ce 11或稱記憶體 位元memory bit〕的機率也愈來愈高，使得同一晶圓之良 品產率降低〔損壞之記憶體數量增加〕，因此，記憶體除 了具有正常所需成列成行之記憶體區域，同時留有備用電 路〔redundancy circuit〕〔或稱備用胞室redundancy cell〕，利用雷射修補之技術改變電路路徑，以取代換置 在正常區域内損壞的記憶體胞室，達到提昇產出良率 〔yield〕之目的。V. Description of the Invention (1) [Field of the Invention] The present invention relates to a test repair analysis method for a memory, and particularly relates to a repair test analysis method using a merge circuit [merge circui t]. ° & [Prior art] Known memory such as dynamic random access memory [dmm], static random access memory [SRAM], flash memory [f iash memory], double data rate dynamic random storage Take memory [DouMe Data Rate DRAM, DDR DRAM] or system single chip [soc] with memory, etc., which are manufactured by semiconductor process. For example, multiple DIJM memory chips (from hundreds to thousands) are formed on a wafer in the form of integrated circuits, such as 6-inch, 8-inch, or 12-inch wafers, but with the The tiny and complicated electronic components and the advancement of the manufacturing process have simultaneously expanded the memory capacity, such as expanding from the conventional 4Mb or 16Mb DRAM to 64Mb, 128Mb, 256Mb DRAM, and even DDR DRAM. As the capacity of a memory becomes larger and larger, the probability of erroneous memory cells (memory ce 11 or memory bit) in semiconductor manufacturing will inevitably increase, making the same wafer The yield of good products is reduced [the number of damaged memory is increased]. Therefore, in addition to the memory area that normally needs to be arranged in rows, there is also a redundant circuit [or redundant cell] The laser patching technology is used to change the circuit path to replace the damaged memory cells in the normal area, so as to improve the yield of the output.
壓熔斷〕修;體製程’其中在測試與〔雷射或高 Repair Anal ·、夂應用到記憶體修補分析〔Memory 之記憶體: = =研以將測試取得不良 =應…代修4有;:;:判:=之= 分析第=，783號「半導體測試之錯誤位址 !圖所示Λ # —種記㈣修補分㈣統，如第 補分析裝置miw半導體測試裝置15。、一位址修 控制單位17。係作為二以;其中測試裝置 置"ο之控制界面；半導體測1 = = =， 151，用以儲存一記憶體 0_匕3有不良儲存區 良儲存區1 5 1之控制^位〗π · <立元、以及控制該不 含有不良緩衝儲存區161 ’位址修補分析裝置160包 至位址修補八& # , 用儲存由不良儲存區1 51傳送 分析= ;:=?”、不良計算單姻，用以 控制單位163爾：子品161内貝料而成為修補位址、以及 位…。3 ’用以控制不良緩衝儲存區a〗與不良計算單 在上述習知之記憶體修補分 良位元資訊係先以控制單位152儲存於j ’該不 後’再以半導體測試裝置150進行下_:個區151 ’之 五、發明說明（3) 必須傳送並儲存於位址修補分析裝置〗6〇之 區161，然而隨著記,1#體奘罟夕卞 良緩衝儲存 裝置ρΛ 裝複雜細緻化，同-記悟： 而要執仃夕道不同之性能測試，若每一 Μ體 :二要如上述般將不良位元〔fail bit〕由半導試 緩衝儲I不•良儲存區151丟到位址修補分析裝置16〇之π試裝 綾二錯存區161，以進行冗長而不恰當的記：良 1:八:二Γ導體測試裝置15 °必須等待位址W分析\析 :二析完成再傳輸資料，將造成測試速率之遲缓裝置 C裝置係花費太多時間在記憶 、、’:同一 【發明目的及概要】 竹LMRA〕。 本發明之主要目的在於提供一 析方法，將同一記情體夕 ’則試修補分 併為-個經合併不良位元之性能併電 ii析，以縮短測試時間，提昇測試效率。方進 統，利Πί:目ΐ在於提供一種記憶體修補分析李 測試不良位元’並傳送至二 性能 複12月之5己憶體之測試修補分析方法，其步驟· 複數次功能性測試至少一 驟· 試後得到不良位元位址之；料f㈣在母一次功能性剛 能性：生:則試之不良位元位址之資料與之前功 將人彳、，〜良位兀位址之合併資料，並加以合併之·爲 隐體疋否犯修補以及若能修補應以傷用電 五、發明說明（4) 路如何修補等資訊。 【發明詳細說明】 :ί2閱圖V/發明將列舉以下之實施例說明: 其包含ί /11， 發明之記憶體修補分析系統中， 測裝置110、一修補分析裝置_、- 二合併電路113 ’ *中測試裝置控 之控制：面作試裝置uo與修補分析裝置m 2體，如動態隨機存取記憶體〔D = 、快閃記憶體〔flas“_=== cDrRate dram： ' 半導體測試裝置n。包含有測試二0 c〕=體， 〔：未…，其具有一探測頭，：=:〕 =體’同時具有-用以儲存記憶體測； 修補分析裝置 測试儲存區111傳送至位址修補分=由 資料，其中該記憶體測t3裝置120之5己憶體測試 對合併，通常分析儲二貝枓係上經合併電路113加以比 ill之容量，而不良叶瞀二H谷置係遠大於測試館存區 該以備用電路如何修補ϋ隐體^修補以及若能修補應 乜補等有用之資訊檔案，且控制單位 -—- 瞧― 五、發明說明（5) 1 2 3係用以控制合士 測試裝置U〇而形成—自/=裝置120可内建置於該半導體 半導體測試裝置110分：：“：=台，或者是可成為與 dePressure fuse] repair; the system process' where the test and [laser or high Repair Anal ·, 夂 applied to the memory repair analysis [Memory of memory: = = research to get the test bad = should be repaired on behalf of 4 have; :;: Judgment: = of = analysis No. =, 783 "Semiconductor test error address! As shown in the picture Λ # —A kind of note repairing system, such as the second analysis device miw semiconductor test device 15." The address repair control unit 17. It is used as the control interface of the test device; the semiconductor test 1 = = =, 151, which is used to store a memory 0_3 3 bad storage area good storage area 1 5 Control of 1 bit π · < Li Yuan, and control of the non-defective buffer storage area 161 'address repair analysis device 160 packets to address repair eight &#, transfer analysis from the defective storage area 1 51 with storage =;: =? ”, Single calculation of bad marriage, used to control the unit 163 Seoul: the sub-item 161 is used as the repair site, and ... 3 'Used to control the bad buffer storage area a] and the bad calculation sheet. In the above-mentioned conventional memory repair, the good bit information is first stored in the control unit 152 in j's time, and then performed by the semiconductor test device 150. : Individual area 151 'Fifth, the description of the invention (3) must be transmitted and stored in the address repair and analysis device 〖60 of area 161, however, with the record, 1 # 体 奘 罟 夕 卞 良 Buffer storage device ρΛ is complicated and detailed Identical, same-mindfulness: To perform different performance tests, if each M body: Second, the fail bit should be stored in the semi-conductor test buffer as described above. I bad storage area 151 Throw it into the address repair analysis device 16 of the π trial installation of the two error storage area 161 to make a long and inappropriate record: good 1: eight: two Γ conductor test device 15 ° must wait for the address W analysis \ analysis: two The analysis and retransmission of data will cause a delay in the test rate. Device C takes too much time to memorize, ': same [invention purpose and summary] Bamboo LMRA]. The main purpose of the present invention is to provide an analysis method, which analyzes the performance of the same memory system and analyzes the performance of a merged bad bit and analyzes it electrically to reduce the test time and improve the test efficiency. Fang Jintong, Li Jilong: The objective is to provide a memory repair analysis method for testing bad bits' and send it to the second performance test of December 5th memory test repair analysis method. Its steps are repeated at least one functional test. · After the test, the bad bit address is obtained; it is expected that the function of the bad bit address in the parent is functional: Health: Then the data of the bad bit address is combined with the previous work, and the good position is merged. Data, and merge it with information about whether the hidden body is repaired or not, and if it can be repaired, the electricity should be used. V. Invention Description (4) How to repair the road. [Detailed description of the invention]: 2 to read the picture V / the invention will list the following embodiment description: it contains / / 11, in the memory repair analysis system of the invention, the test device 110, a repair analysis device _,-two merge circuits 113 '* Control of test device control: Surface test device uo and repair analysis device m 2 body, such as dynamic random access memory [D =, flash memory [flas “_ === cDrRate dram:' Semiconductor test Device n. Contains test 2 0 c] = body, [: not ..., which has a probe,: =:] = body 'also has-used to store memory test; repair analysis device test storage area 111 is transmitted to Address repair points = from the data, where the memory test t3 device 120 5 memory test pair merge, usually analysis of the storage capacity of the second storage system through the merger circuit 113 to ill, and the bad leaves of the second storage It is much larger than the storage area of the test hall. How to use the spare circuit to repair the hidden body ^ repair, and if it can repair the useful information files, etc., and the control unit -------V. Description of the invention (5) 1 2 3 Used to control the Ushi test device U〇- / = Disposed within the device 120 may be built to test semiconductor devices 110 divided semiconductor :: ": = table, or it may be the de
121，用以電二2 = : =試儲存區U1與該分析儲存區 測試資料，其電路之連接區111傳送出之記憶體之 濾之功能，該合併電路113孫第圖所不而具有比對與過 内為較佳。 電路113係以設置於半導體測試裴置110 複數之補分析系統w 試，其係在不同之測;項目之功能性測 預燒（b議_ιη)狀態等〕操作檢測之，通常半㈣測試/ 置110係有同時接觸測試複數個記憶體之 數〕圖所示’以其中一記憶體例舉說明，°=一 項目，性靶測試後侍到之資料係以圖號⑷ 代表「通過」，而"〇"代表「損壞」或「不 :工」 項目測試後發現該記憶體在χ2#γ2列處具有一損壞之位 =’=後將該不良位元之位址〔χ2_γ2〕儲存於該測試儲 存區11 ’之後’在第二項目之性能測試後得到之資料係 以圖號142表示，>在第二項目測試後發現該記憶體在以行 Υ1列處具有一損壞之位元，在將該不良位元之位址 〔Χ1-Υ1〕儲存於該測試儲存區η1之前，先將第一項目性121, used for electric 2 === test storage area U1 and the analysis storage area test data, the filter function of the memory transmitted from the connection area 111 of the circuit, the combined circuit 113 has a better comparison It is better to confront with the inside. The circuit 113 is tested with a supplementary analysis system of a complex number of 110, which is set in a semiconductor test. It is tested in different tests; the functional test of the project is pre-burned (b-state), and it is usually tested by half a test. / Set 110 is the number of multiple memories tested at the same time.] As shown in the figure, 'take one of the memory as an example, ° = one item, the data served after the sexual target test is represented by the figure number ⑷ for "pass", And "" 〇 " represents" damaged "or" no: work ". After testing the item, it is found that the memory has a damaged bit at the χ2 # γ2 column = '= and then stores the address of the bad bit [χ2_γ2]. The data obtained after the performance test of the second item after the test storage area 11 is represented by the drawing number 142. > After the second item test, it was found that the memory has a damaged bit in row 1 Before storing the address [X1-Υ1] of the bad bit in the test storage area η1, first
第9頁 五、發明說明（6) 能測試資料141〔 X2-Y2〕通過合併電路丨13儲存於分析儲 存區1 2 1，之後，在第三項目之性能測試後得到之資料係 以圖號144表示，在第三項目測試後發現該記憶體在^ Y1列以及X4行Y3列處具有損壞之位元，在將該不良位元之 位址〔X卜Yl，X4-Y3〕儲存於該測試儲存區ln之前， 將第二項目性能測試資料142〔χι—n〕通過合併電路ιΐ3 合併儲存於分析儲存區121，利用該 項目性能測試資料141盥篦-t 7 ^ 盔需利用之資料而播/、第一 犯測試資料142，過濾 …而和用之貝枓而構成一個合併第一 1^,1 #143 CXl^Y1 ,χ2^γ2 } , 要三個項目之功能測試，由彳 记隐體…，、而 砝束m萝，^由測忒裝置控制單位130發出一 …釆訊號—驅使第二項目性能測試資料丨 X4 - Y3〕經由該合併電路113與合 一 ， 性能測試資料143〔 XI—Υ1，γ^ν9 1 項目與第二項目之 ―個合併第一、第二及謹= 相比對，進而合併為 〔XH1，Χ2-Υ2，Χ4_Υ3〕二並儲存之^八能測試資料145 以不良計算單位122對該 之：：：存區12i，最後 修補分析，以判別並取得該呓/之曰佳此測試資料145進行 補應以備用電路如何佟 ς體疋否能修補以及若能修 較佳地在每-次功能性測試ί驟中以續之修補製程， 備用電路，以掌握記憶體内位元 问時測試記憶體内之 因此，依本發明之記憶體該 數次功能性測試所得之 j成修補分析方法係將複 雜而高容量記憶體之剛試過一有效資料，在複 雨用到少量之儲存區， 511092 五、發明說明（7) 不需要在每一次功能性測試後執行記憶體修補分析，節省 了半導體測試裝置等待記憶體修補分析之時間浪費，具有 縮短測試時間而提昇測試效率之功效。 故本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範Page 9 V. Description of the invention (6) The test data 141 [X2-Y2] can be stored in the analysis storage area 1 2 1 through the combined circuit 丨 13. After that, the data obtained after the performance test of the third item is shown in the figure 144 indicates that after the third item test, the memory was found to have damaged bits in column Y1 and column X3 and column Y3, and the address of the bad bit [Xbu Yl, X4-Y3] was stored in the Prior to testing the storage area ln, the second item performance test data 142 [χι-n] was merged and stored in the analysis storage area 121 through a merging circuit ι 利用 3, and the item performance test data 141 was used. Broadcast /, the first offender test data 142, filter ... and use it to form a merged first 1 ^, 1 # 143 CXl ^ Y1, χ2 ^ γ2}, a functional test of three items is required. Hidden body ..., and the weight m ^ is sent by the measuring device control unit 130 ... a signal-driving the second project performance test data 丨 X4-Y3] through the merger circuit 113 and unity, performance test data 143 [XI—Υ1, γ ^ ν9 1-one of the first and second projects combined The second and sincere = comparison, and then merged into [XH1, X2-Υ2, X4_Υ3] and stored the ^ eight energy test data 145 in bad calculation unit 122 to this ::: storage area 12i, the final repair analysis, In order to identify and obtain the test data 145, make up the test data. 145 How to prepare the backup circuit, whether it can be repaired, and if it can be repaired, it is better to continue the repair process in each functional test. The backup circuit is used to test the memory in the memory when the memory bit is interrogated. Therefore, the method for repair analysis of j obtained from the functional tests of the memory of the present invention is a new test of a complex and high-capacity memory. After a valid data, a small amount of storage area is used in Fuyu, 511092 V. Description of the invention (7) It is not necessary to perform memory repair analysis after each functional test, saving the semiconductor test device waiting time for memory repair analysis Waste, has the effect of shortening the test time and improving the test efficiency. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall be protected by the present invention. Fan
第11頁 511092 —.......................... _ 圖式簡單說明Page 511092 --............. _ Schematic description
f圖式說明J 第1圖.，美國專利第5,841，783號「半導體測試之笋 統」中，一種記憶體修補a分析 之示意圖，·及 統中，其合併電路 第4圖··，本發明之記憶體之測 功能性測試所得的不良：刀析方法’將多次 【圖號說；】合併之示意圖。凡位址之資料加以比對 11 0半導體測試裝置 111測試儲存區 1 Ί 0 ^ 120修補分析# 112控制單位 η m分析=置 113合併電路 130測試裝置控制單：2不良計算單位123控制單位 :44;項目性能4資料 = ; = 試資料 144第三項 ;、第一項目之性能測試次 145合“：忐夠試㈣ 貝料 150半導體測試匕及第三項目之性能測試資料 16〇修補置152控制單位 $ 12頁 511092 圖式簡單說明 1 6 1不良緩衝儲存區1 6 2不良計算單位 1 6 3 控制單位 170 測試裝置控制單位 X1〜Xm 記憶體位元之成行位址 Y卜Yn 記憶體位元之成列位址 —! “··del 驛f Schematic description J Figure 1. US Pat. No. 5,841,783 "Semiconductor Testing System", a schematic diagram of a memory repair a analysis, and in the system, its combined circuit Figure 4 ... Defective memory test of the invented functional test: the knife analysis method 'will be repeated multiple times [the figure said;] the schematic diagram of the merger. Where the address data is compared 11 0 semiconductor test device 111 test storage area 1 Ί 0 ^ 120 patch analysis # 112 control unit η m analysis = set 113 combined circuit 130 test device control unit: 2 defective calculation unit 123 control unit: 44; project performance 4 data =; = test data 144 third item; performance test number 145 of the first item ": enough test ㈣ 150 semiconductor test dagger and performance test data of the third item 16 152 Control unit $ 12 Page 511092 Simple illustration of the drawing 1 6 1 Defective buffer storage area 1 6 2 Defective calculation unit 1 6 3 Control unit 170 Test device control unit X1 ~ Xm Row location of memory bits Y BU Yn Memory bits The address of the column —! "·· del station
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