TW510022B - High-speed level shifter device with zero threshold voltage components - Google Patents

Abstract

The present invention provides a high-speed level shifter device with zero threshold voltage components. The device includes: an inverter and a shift latch. The inverter is composed of two pairs of N-type transistors and two pairs of P-type transistors, wherein the transistors have relatively thin gate oxide layers. The shift latch includes a pair of crossed-coupled P-type transistors, a pair of N-type transistors and a pair of N-type transistors with zero threshold voltage, wherein the crosses-coupled P-type transistors have relatively thick gate oxide layer, the N-type transistors have relatively thin gate oxide layers, and the N-type transistors with zero threshold voltages have relatively thick gate oxide layers.

Description

510022

FIELD OF THE INVENTION The present invention relates to a level shifter device, in particular to a level-bit device with zero critical voltage metal-oxygen half field effect transistor, which can be applied to ultra deep sub-micron (ultra sub-micr) ) Background of semiconductor technology invention: Based on the rapid progress of integrated circuit technology, the line width of integrated circuits can reach the depth of sub-micron or even ultra-deep sub-micron. When entering the generation with line width less than 0 · 18 microns, various The process conditions are stricter than before. Before the components are reduced, the space for making components is also relatively reduced. Therefore, it is a challenging task to make high-performance components or devices in (ultra-deep) sub-micron technology. The stable production of JFET technology has led to the development of the more important element metal-oxide-semiconductor field-effect transistor (MOSFET). The structure of mfsfet builds a gate on silicon dioxide, located between the drain and source of the semiconductor. . By applying an appropriate voltage between the gate and the semiconductor, the channel current between the source and the drain can be controlled. The flat displacement device uses two different types of metal-oxide half-field-effect transistors, 丄, containing core components and as input / output components. The core component has a lower threshold voltage (thresh〇ld v〇u -1 to .35 volts, during which the thickness of the polar oxide layer is thinner, which is used to increase the

Page 4 510022 V. Description of the invention (2) Saturation current of M0S. The threshold voltage of the input / output element (丨 / 〇) is relatively high, which is between about 0.4 volts and 0.7 volts. The thickness of the gate oxide layer is thicker, which is used to increase the reliability. The level shifter is a bridge that converts the signal from low core voltage to low input / output voltage (1 ^ to I / O voltage). In other words, the level shifter is used to convert the input signal voltage Level to a predetermined signal voltage level, which can usually be used as a buffer. Components of integrated circuits usually have an internal operating voltage, which is different from the voltage at which an external circuit or system operates. The level shifting device receives a variable input signal voltage within a range, and then shifts it to a voltage of another range level, which is generally called a variable input buffer (scalable level buffer ^. Generally speaking, the core The operating voltage of the device is lower than the operating voltage of the input / output device, and the operating voltage of the input / output device decreases much more slowly than the core device operating voltage. Generally, VDDQ is about 5v-3v 'VDD is about 〇 · 9ν-2 · 5ν. For the previous case of the conventional technology, please refer to the related cases such as US patents US 60 1 1 421, US 5 969542, etc. Fig. 1 is not a traditional technology level shifter, which includes a phase inversion The device is composed of NM0S (N1, Ν2) and PM0S (P1, P2), and contains an offset ❿ latch. The offset latch consists of a pair of NM0S (N3, N4) and a light-weight PM0S (P3, P4). The gate of PM0S (P3) is connected to the drain of PM0S (P4). Similarly, the gate of PM0S (P4) is also connected to the drain of PM0SCP3. The source of NM0S pair (N3, N4) is connected to a potential

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At the input terminal, the gate of the transistor N4 is connected to the output of the inverter. The anti-phase stealing receives the voltage level of an input signal through the input terminal (IN), and outputs the level shift signal by a range of # ^ through the bias #flash. Generally, the input low-potential signal is between VDD_vss, and the potential level after being processed by the level shift device is between VDDQ_vss. The operation of the level shifting device described in Fig. 2 is as follows. When a low potential signal (such as vss) is input to the input terminal, the P-type transistor (P1) is turned on and the N-type transistor (N1) is turned off. The IN-bar potential rises to a higher potential VDD, so the N-type transistor (2) is turned on, and the P-type transistor (p2 / is turned off. At this time, the 1-type is turned on because the IN-bar is pulled up) Transistor (N3) 'and the output (OUT) pulls down to VSS, causing the p-type transistor (P4) to turn on, so that the potential of OUT-bar is VDDQ, the P-type transistor (p3) and the N-type transistor The crystal (N4) is turned off, the N-type transistor (0) is turned on, and the jT-type electric body (P5) is turned off. At this time, the output terminal (OUT2) is completely pulled down to a potential of zero or ground. For the same reason, when the input terminal (IN) is converted from VSS to input a higher potential signal to VDD, the N-type transistor (N1) is turned on, and the p-type transistor (ρι) is turned off. VDD is pulled to a lower potential (ground), so the p-type transistor (P2) is turned on and the N-type transistor (N2) is turned off. Because the IN-bar is pulled down, the N-type transistor (N4) is turned on, the N-type transistor (N3) is turned off, and then the P-type transistor (P3) is turned on and the P-type transistor (P4) is turned off. As n-type transistor

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When the body (N4) is turned on, the OUT_bar potential is pulled down to vss, the body (N5) is turned off, and the p-type transistor (p5) is turned on, because the potential of the transistor (0UT2) is VDDQ. Mi® knows that using the above-mentioned level shift circuit can generally lower

Yuan: shift its potential to a higher level. Q: Right ΐϊ !: Operation. The above design has DC leakage current to the input signal. In the design of offset flash, there is no short-circuit current to VDD. In addition, for offset flash, there is no short-circuit current path between one of the transistor (P4, N3) or transistor (P3, N4) is turned on from VDDQ to VSS at the same time. The potential of the signal input from the input terminal is between vss to VDD. With the shrinking trend of semiconductor technology, VDD will become smaller and smaller. Because the transistors (N3, N4) still have the same threshold voltage, the saturation current of the transistor (N4) will become smaller and smaller. As mentioned above, when the transistor (N4) is turned from on to off, when the transistor (P3) is still on, and VDDQ is short-circuited through the transistor (P3, N3), the current always flows, and the UT_bar node must be pulled down to Grounding can completely turn off the p-type transistor (p3). This circuit will fail when _ VDD is low or VDDQ is high. If the saturation current of the transistor (N3) is not greater than the saturation current of the transistor (p3), the signal transmission rate will be very slow and it will take a long time. In deep submicron applications, it can cause severe delays.

Page 7 510022 V. Description of the invention (5) --------- In the field of ultra-deep sub-micron, when the potential of the core component gradually drops to about 1.0 volts, the level shifter will Does not work. The input / output threshold voltage (for example, 3 · 3V MOSFETs) cannot be reduced in proportion to the supply voltage VDD of the core components. In other words, the 3 · 3 volt NMOSs inside the level shifter cannot be turned on. There are two ways to solve the problems in the conventional art, namely to reduce the potential difference (gap) between VDD and 3.3 V NMOSs in the level shift device. The first way is to use the nuclear 々NM0Ss instead of the 33 V gate. 〇 ^ Yi Dexin to a lower threshold voltage, where the core NMOSs threshold voltage is, for example, 0.5 volts; the second method is to increase (pUmp up) the supply voltage of the core components from VDD to 2VDD to get a higher voltage to turn on 3.3 V NMOSs. Although the circuit structure of the first method does not have the shortcomings of the conventional art, it must spend about tens of DC currents to generate the bias voltage (VBI AS), and it needs additional circuit design to turn off (turn off) The DC bias is in the sleep mode; while the circuit structure of the second method operates too slowly when the PVT (process voltage temperature) is not good, and it will cost millions of Hz to use 5-ns time, on the other hand, if the input signal toggles for a long time, it will cause the generated charges (PumP charges) due to _ junction reversed-bias voltage leakage Leakage, which will also cause the effective voltage to return to VDD instead of the initial 2VDD ', thus making the circuit susceptible to external noises.

Page 8 510022 V. Description of the invention (6) -----Another conventional circuit structure of the level f shift device of a metal-oxygen half field effect transistor with zero critical voltage, which uses a cascade Electricity = body to support the south voltage, the transistors (NA1, NA2) are always on, and the gate is connected to a fixed potential VDD, refer to Figure 3. The potentials of the nodes INT1 and INT2 are close to vdd + av. Such a potential will cause the gate oxide layer of N1 or ^ to be electrically broken down. Therefore, in order to improve the stability and operation speed of the circuit, a new level shift device is urgently needed to replace the conventional level shift device. _ Purpose and summary of the invention: The purpose of the present invention is to use the transistor (thick gate oxide layer) and an operating speed to replace the thick gate oxide device of the conventional technology. A pair of zero-threshold metal-oxygen half-field-effects A pair of N-type transistors (thin gate oxide) N-type transistors to enhance the level shift level in Device, which includes an inverter and an offset latch. An inversion transistor and a group of p-type transistors, where the power-on has a relatively thin gate oxide layer, and the electric current of the P-type transistor is positively biased, and the-pole of the N-type transistor is connected to —Electricity = One and the said partial material 1 includes-the corresponding M electricity is = type

Page 9 510022 V. Description of the invention (7) I ^ ^ tt ^ ^ ^ ^! The electric body has a relatively thick gate oxide layer, of which the _-type transistor in one pole connection has relatively thin gate oxide Layer, ϊ 之 ΐ ί a potential is usually grounded, the gates are connected to the reverse phase i respectively. In addition, the N-type transistor with zero critical voltage has a thick interlayer oxide layer, and its closed electrodes are respectively connected to the inverse if terminal. The other two poles are respectively connected to the mutual surface-type electrical and: 'The sum of the zero-critical electro-transistor transistor is connected to the drain of PMOS, and its source is connected to the drain of 肫 ⑽. Detailed description of the invention: Sub-micrograph 5. The present invention is to disclose an electric meter complementary metal-oxide half-field effect transistor, and the detailed description will describe the following translational displacement device, which is applied to ultra-deep circuit structure. Please refer to Figure 4 and Figure 1. Symbols of various types of metal-oxide-semiconductor half-field-effect transistors. Figure 4 does not show the circuit structure of the level-shifting device of the metal-oxide-semiconductor half-field-effect transistor with zero critical voltage according to the present invention. No.) and P-type transistors (P, P0), and includes an offset flash. The offset problem consists of a pair of N-type transistors (N1, N2), a pair of zero-voltage N-type transistors (NAI, NA2), and a mutually coupled p-type transistor (ρ, p2). As for the gate of the P-type transistor (P2) is connected to the drain of the n-type transistor (ναι), the gate of the P-type transistor (Pl) is also connected to the N-type transistor.

510022 V. Description of invention (8) ------(NA2) The drain. The vt of the zero critical voltage metal-oxide half field effect transistor is, for example, 0 volts to protect the N-type transistor (Nι) -type transistor (N2) from high-voltage stress 5 (= reSS), and the N-type transistor (... ^ to An example of the type transistor ^ 2) is: The difference between the present invention and the conventional technology is two points (1) the N-type transistor (Nl, N2) is a thin-gate oxide transistor, and the traditional Thick gate: the oxide transistor is different, its source is connected to a potential which is usually ground, the gate of the N-type transistor (N1, NA1) is connected to the input of the inverter, and the type 1_ crystal ( The gates of N2 and NA2) are connected to the output of the inverter. (2) The present invention adds a pair of zero-critical metal-oxide half-field-effect N-type transistors "^, X NA2", whose drain is connected to the drain of the P-type transistor, and its source is connected to the 1 ^ -type transistor. The "Zhi pole" gate is connected to the input and output terminals of the inverter, which means that the gate of the "N-type transistor (NAI, NA2) is connected to a variable potential signal. In addition In addition, for device reliability, all VDDQs are biased only to p-type transistors with thick gate oxide layers, while P-type transistors and N-type transistors with thin gate oxide layers are only biased by VDD. · The inverter receives a voltage level of an input signal through an input terminal (IN), and outputs a level shift output signal of a predetermined range level through an offset latch. Generally, an input low-potential signal Between VDD-VSS, via

510022 5. Description of the invention (9) Offset device The potential level after the offset processing is approximately between VDDQ_VSS. The signal input terminal of the present invention is only connected to the gates of the transistors (N1, n A1, P, P 0, N, NO), and the output of the inverter is connected to the gates of the n-type transistors (N2, NA2). There is no DC leakage current path for input signals. Because only one of the transistors (P, NO) and transistors (N, P0) will turn on, there is no short-circuit current from VDD to vss. In addition, only one of the transistors (pi, N2) or transistors (P2, N1) is turned on at the same time, so there is no short-circuit current path between VDDq and vss. The operating conditions of the device described in Figure 4 are as follows. When a lower potential signal (such as VSS) is input to the signal input terminal (丨 N), the p-type transistor (p) is turned on and the n-type transistor (N) is turned off. The IN-bar potential is increased to a higher potential VDD, so the N-type transistor (NO) is turned on and the p-type transistor (P0) is turned off. At this time, because

The IN-bar pulls up, so the n-type transistor (N1) is turned on, and the n-type transistor (N2) is turned off. Because the n-type transistor (NA1) is on, the voltage level of LDSR1 will be lower than VDDq minus the threshold voltage, and the N-type transistor (NA 2) is off. Therefore, the potential of I n τ 1 is close to 0. Voltage, causing the p-type transistor (P2) to turn on, and the potential at the LDSR of ουτ-bar becomes VDDQ, so that the P-type transistor (P1) is turned off, then the N-type transistor (N3) is turned on, and the P-type transistor is turned on (P3) is turned off. At this time, the output terminal (0υτ) is completely pulled down to the potential spring to zero or ground. "Conversely" If the signal input terminal (IN) is converted from VSS to a potential signal of one to two, for example, VDD, the N-type transistor (N) is turned on, and the p-type transistor

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Body (P) OFF 'pulls IN-bar from VDD to a lower potential (ground), so the P-type transistor (P0) is turned on and the N-type transistor (N0) is turned off. Because the IN-bar is pulled down, the on-type transistor (] ^ 2) is turned on, and the N-type transistor (N1) is off. Because the N-type transistor (NA1) is on and the n-type transistor (NA2) is off, so The potential of ιΝΤ1 is close to 0 volts. At this time, the voltage of LDSR1 is lower than VDDQ minus the threshold voltage value, causing the p-type transistor (p2) to turn on, and the potential at LDSR1 of OUT-bar becomes VDDQ, making the P-type transistor (P2) is turned off, then the P-type transistor (P3) is turned on, and the N-type transistor (03) is turned off ', so the potential of the output terminal (OUT) is VDDQ. m In addition to the junction current (junct ion) and sub-threshold leakage, the present invention does not cause current loss, nor does it generate DC static current and short-circuit current. Because of the N-type transistor (NAI, NA2), the original transistor with a thicker gate oxide layer will be replaced by a transistor with a thinner gate oxide layer and perform the same function. This thin gate oxide layer has a lower threshold voltage and a higher saturation current. This lower threshold voltage causes the present invention to convert the lower g-bit VDD to VDDQ. The protection of the N-type transistor (NAI, NA2) can prevent the N-type transistor (01, N2) of the thin gate oxide layer from being biased by a high voltage. When VDD = 1.0V, the conventional technique cannot work normally because the N-type transistors (N1, N2) of the polar oxide layer cannot provide a sufficient current.

Page 13 510022 Description of the invention (11) However, the present invention can still operate normally under the same conditions, because the saturation current of the thin gate oxide transistor of the present invention is higher than that of the conventional technology. Therefore, a metal-oxide-semiconductor field-effect transistor with a zero critical voltage is a key element for manufacturing a double-gate oxide layer CMos below 0.1 micron (um). When the sub-threshold leakage of the n-type transistor NA1 (NA2) is equal to the reverse bias current of the junction of the N-type transistor NA1 + N1 (NA2 + N2), Δν is the equilibrium voltage, and the P-type transistor Crystal? 1 (! ≫ 2) When pulled up, turning off the N-type transistor NA1 (NA2) can isolate the parasitic capacitor C1 (C2) from the node (n0 (je) LSDR1 (LSDR), resulting in speed Enhancement. This method does not require no extra process, and it is in the millions. The use of frequency rate only takes about ns time. Figure 5 shows the metal-oxygen half field with zero critical voltage in the present invention. Schematic diagram of the level shift circuit of an effect transistor. The difference between Figure 5 and Figure 4 is that an additional pair of n-type transistors (N3, N3, N3, N2, N2, N2, N2, N2, N2) N4), where the above N-type transistor (N3, N4) gate connection potential VDD 'is used to better protect the n-type transistor (Ni, N2), so that the N-type transistor with a thin gate oxide layer ( Nl, N2) will not be directly biased by high voltage. For logic circuits, it is difficult to estimate the potential of INT1 and INT2 according to the simulation results of the Sp ice model, and the subcriticality of n-type transistors (ναι, ΝΑ2) The current model cannot be accurately estimated either. Therefore, the N can be further protected by adding a pair of N-type transistors (N3, N4). Said transistors (Nl, Ν2). This method does not require an additional process (extra n〇

Page 14 510022 V. Description of the invention (12) process), and the time at the frequency of millions of Hz. Thousands of magic are used together, and it takes about ns. Therefore, the advantages of the present invention are: the level shift device of the present invention = an external process, that is, it can make its operation speed faster than that of a traditional level shift device, and does not DC current will be consumed; in addition, the circuit design of the present invention can even operate on circuits with a design rule of less than 1 micron (um) ° For those skilled in the art, the present invention is illustrated by a better example as above 'But it is not intended to limit the spirit of the invention. Modifications and similar arrangements made without departing from the spirit and scope of the present invention should be included in the scope of the following patents, and such scope should be consistent with the broadest interpretation covering all modifications and similar structures. Therefore, the description of a preferred embodiment of the present invention as described above can be used to identify various changes made without departing from the spirit and scope of the present invention.

510022 Brief description of the drawings The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: Figure 1 is a schematic diagram of various types of metal-oxide half-field effect transistors. FIG. 2 is a schematic diagram of a level shift circuit of the conventional technology. Figure 3 is a schematic diagram of a level shift circuit of a conventional metal-oxide-semiconductor half field-effect transistor with zero critical voltage. FIG. 4 is a schematic diagram of a level shift circuit of a metal-oxide half-field-effect transistor with zero critical voltage according to the present invention. FIG. 5 is a schematic diagram of the level and displacement circuit of the metal-oxide-semiconductor half field-effect transistor with zero critical voltage according to the present invention.

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Claims (1)

1 month and 2 months, rrT, V ^. Two high-speed level ixiH with zero critical voltage element. One is a shlft latch. The offset latch contains ... L 3 BU, X, P, Cross-coupled P-type transistor, complex Φ One of the second transistor is connected to the second positive bias voltage; / 、 Since the first type transistor has a gate oxide layer of the first thickness, its Φ " When the source of N-type transistor is connected to a potential, the operating speed is usually Ί A to increase the level shift device. 型: The body is an N-type transistor with zero critical voltage, gate The input and output ends of the phase splitter's other poles are respectively connected to the pair of bands: 1 transistor, the first pair of N-type transistors are connected, the second thicker than the ya_body has a second thickness Extremely oxidized layer 'The second thickness is greater than the second pair of electricity ::: where the second pair of N-type transistors described above are used to protect 2. ί! Ϊ ί :: metal oxide with zero critical voltage around item 1 Half-field-effect / dd-shift device, where the first positive bias voltage is 3, == metal-oxygen half-field-effect with zero critical voltage around item 1 Wherein said second positive bias 510022 4. A level shifting device comprising a shift latch, including a pair of p-type transistors coupled to each other (cr0ssed — couple), a first pair of ~ type transistors Is a ~ -type transistor with a zero critical voltage, and a second pair of N-type transistors. F is used to increase the operating speed of the level shift device, wherein the gate oxide layer of the second pair of transistors is opposite to the The gate oxide layer of the first pair of transistors is thin, and the source of the second pair of N-type transistors is usually connected to a potential, and the gates are respectively connected to the input terminal and the output terminal of an inverter. 0 5 · —A kind of high-speed level shifting device with a zero critical voltage element. The electric shifter device includes: a shift latch (shi ft latch), the shift latch includes: a pair of cross-coupled (c 〇upU)? Type transistor, in which one of the p-type transistors is connected to a second positive bias voltage; the second pair of 黾 -type 黾 crystals has a gate oxide layer of a first thickness, where the fth and the n-type transistors are The source is usually connected to a potential, and the gate of the second pair of N-type transistors is connected to the input and output ends of an inverter. The first pair of N-type transistors is used to enhance the level shift. The operating speed of the device; and the first pair of N-type transistors are N-type transistors with zero critical voltage. The gates are connected to the input and output terminals of the opposite phase, and the other two poles are coupled to the pair. The transistor, the first pair of N-type transistors are connected, and the second pair Page 18 VI. Patent application scope The N-type transistor has a second thickness over the first thickness, wherein the second pair of the second-thickness and the second-thicker pair of transistors; and Three pairs of N-type transistors, having a second thickness that is thinner than the second thickness; a second electrode, an oxide layer, and the third electrode connected to the first pair of N-type transistors. The source electrode of the transistor is connected to the first pair of :: and the pole 1 and the third pair of N-type transistors called the HI of the transistor, and the third pair of N-type transistors. Connected to the first ^ to protect the first pair of transistors. The third pair of N-type transistors 6. If the level shifting device of the fifth transistor in the patent application scope, the order of voltage Metal-oxygen half-field effect VDD. The positive bias voltage of the above-mentioned brother is 7. If the level shift device of the star transistor of item 5 of the patent application is applied, it has metal-oxygen half-field effect VDDQ which enables the pressure of the second boundary. ΤThe above-mentioned positive bias voltage is 8.-: Two-level displacement device 'This level shifting device includes: partial bias (shi ft lat_ch ), A p-type transistor approved by a couple of people, the first package 3 a pair of mutually-coupled (level-shift device operating speed ΓΓ-type electric two-body) is used to improve the connection-the potential is usually grounded The source of the transistor is connected to the input terminal and the wheel output terminal, and the inter-factory pole 7 is connected to an inverter. The # type f crystal is a system with zero critical voltage. Page 19 510022 ij 6. For the N-type transistor with a patent application range, the gate oxide layer of the second pair of transistors is thicker than the gate oxide layer of the first pair of transistors, and the second pair of N-type transistors The transistor system is used to protect the first pair of transistors and the third pair of N-type transistors. The gate oxide layer of the third pair of transistors is thin compared to the gate oxide layer of the second pair of transistors. A third pair of N-type transistor systems is used to protect the first pair of transistors. Page 20