508773 7 902twf. doc/009 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明q ) 本發明是有關於一種封裝結構，且特別是有關於一種 能夠與JEDEC標準封裝相容，且能夠有效降低製作成本的 泛用微小型無引腳封裝結構（Universal Small Outline Non-lead package，USON package ) 〇 一般的封裝產品大致可以分爲引腳插入型（Pin Through Hole ’ PTH )與表面黏著型（Surface Mount508773 7 902twf. Doc / 009 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention q) The present invention relates to a package structure, and in particular to a package that is compatible with the JEDEC standard package and can Universal Small Outline Non-lead package (USON package) that effectively reduces manufacturing costs. General package products can be roughly divided into pin through hole (PTH) and surface mount type (Surface Mount
Technology，SMT )兩大類。引腳插入型的封裝產品是將元 件的引腳插入已鑽孔的電路板上並進行電性連接，引腳插 入型的封裝產品以DIP( Dual In-line Package )最具代表性。 而表面黏著型的封裝產品則需在電路板之接點塗上錫膏 (solder paste )，以與引腳電性連接。表面黏著型的封裝產 品可區分爲 SOP( Small Outline Package )、QFP( Quad Flat Package )、BGA( Ball Grid Array )三大族群。 請同時參照第1圖與第2圖，其分別繪示爲習知四排 引腳封裝以及雙排引腳封裝之結構示意圖。四排引腳封裝 結構100，其外引腳（Outer lead )102係配置於封裝膠體1〇4 的四個端面上並向外延伸。而雙排引腳封裝結構200，其 外引腳202係配置於封裝膠體204的其中兩個端面上並向 外延伸。習知四排引腳封裝100以及雙排引腳封裝200所 使用的導線架（leadframe )不相同，且針對導線架上不同的 外引腳102、202配置使得四排引腳封裝1〇〇以及雙排引腳 封裝200在後I買進行去澄/剪切（De-junk/Trim，D/T )以及 成型/切割（Forming/Singulation，F/S )的動作時，必須投資 不同的治具與設備。 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 x 2沿公釐） I------------------訂---------線· (請先閱讀背面之注意事項再填寫本頁) ^^J^°2twf.doc/〇〇9 A7 · 五、^'—-Technology, SMT). Pin-in type package products insert the pins of components into a drilled circuit board and make electrical connections. Pin-in type package products are most representative of DIP (Dual In-line Package). For surface-adhesive packaging products, solder paste must be applied to the contacts of the circuit board to electrically connect the pins. Surface-adhesive package products can be divided into three major groups: SOP (Small Outline Package), QFP (Quad Flat Package), and BGA (Ball Grid Array). Please refer to FIG. 1 and FIG. 2 at the same time, which respectively show the structure diagrams of the conventional four-row package and the double-row package. In a four-row pin package structure 100, outer leads 102 are arranged on the four end faces of the package gel 104 and extend outward. In the double-row lead package structure 200, the outer leads 202 are arranged on two end faces of the encapsulant 204 and extend outward. It is known that the lead frames used in the four-row lead package 100 and the two-row lead package 200 are different, and the different outer pins 102 and 202 configurations on the lead frame make the four-row lead package 100 and When the double-row pin package 200 is purchased after the de-junk / Trim (D / T) and forming / cutting (F / S) operations, different fixtures must be invested With equipment. This paper size applies to China National Standard (CNS) A4 specification (2) 0 x 2 mm. I ------------------ Order -------- -Line · (Please read the notes on the back before filling this page) ^^ J ^ ° 2twf.doc / 〇〇9 A7 · Five, ^ '—-
B 白知因應不同的封裝產品，諸如TSOP、sop、SON BCC、QFp、QFN等四排引腳或雙排引腳的封裝 =要針叫不同的封㈣態來投資難設備。不同的封 #型_需要不同的封膠模具（moldlng㈣办）來進行封膠 (moldmg )，在不同模具上的投資耗費很大的成本。 / ^此外，不同的封裝型態需要以不同的治具來進行去渣/ 剪切（D/T )的動作，且需要不同的治具來進行成型/切割 (F/S )的動作。不論是去渣/剪切或是成型/切割，其投資在 治具上的成本與時間十分可觀。 因此，本發明的目的在提出一種封裝結構，其能夠與 JEDEC標準中四排引腳或雙排引腳的封裝相容，且能夠有 效降低製作成本。 經濟部智慧財產局員工消費合作社印製 爲達本發明之上述目的，提出一種封裝結構包括一絕 緣基板、一晶片以及一封裝膠體。其中，絕緣基材上配置 有一圖案化線路，而絕緣基材的端面上具有數個凹面 (concave surface )，且每一凹面上配置有一導體層以形成 一端子（Termmal )。晶片係配置於絕緣基材上，且晶片係 藉由絕緣基板上的圖案化線路與端面上的端子電性連接， 晶片與圖案化線路之間例如係藉由銲線（wire bonding )的 方式進行電性連接。此外，封裝膠體係配置於絕緣基材與 晶片上，以將晶片包覆並固著於絕緣基材上。 本發明之封裝結構中，配置於絕緣基板端面上的端子 例如具有一半圓形的凹入結構。 本發明之封裝結構中，端面上端子的製作例如先於絕 4 本紙張尺度適用中國國家標準(CNS)A4規格⑵G X 297公髮)------- 經濟部智慧財產局員工消費合作社印製 508773 7902twf.d〇c/009 ___B7_ 五、發明說明（/ ) 緣基板上的適當位置鑽孔以形成貫孔（through hole )，並進 行塞孔製程以將導體層塡入貫孔中，之後再將絕緣基板切 割。 本發明之封裝結構中，端子例如係配置於絕緣基板的 四個端面上，藉由絕緣基板上圖案化線路的適當設計 (layout )，可製作出與四排引腳封裝相容之泛用微小型無 引腳封裝結構（USON )。 本發明之封裝結構中，端子例如係配置於絕緣基板的 其中二個端面上，藉由絕緣基板上圖案化線路的適當設計， 可製作出與雙排引腳封裝相容之泛用微小型無引腳封裝結 USON ) 〇 本發明藉由絕緣基板上圖案化線路的設計，在搭配上 絕緣基板端面上端子的適當配置，可輕易的製作出與雙排 引腳封裝以及與四排引腳封裝相容之泛用微小型無引腳封 裝（USON )。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖繪示爲習知四排引腳封裝之結構示意圖； 第2圖繪示爲習知雙排引腳封裝之結構示意圖； 第3圖繪示爲依照本發明一較佳實施例與四排引腳封 裝相容之泛用微小型無引腳封裝結構的下視圖； 第4圖繪示爲依照本發明一較佳實施例與雙排引腳封 ------------ 裝--------訂---------'舊 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 508773 7902twf.doc/009 _B7__ 五、發明說明（¥ ) 裝相容之泛用微小型無引腳封裝結構的下視圖； 第5圖繪示爲適用於四排引腳封裝之絕緣基板結構的 上視圖； 第6圖繪示爲適用於雙排引腳封裝之絕緣基板結構的 上視圖， 第7圖繪示爲依照本發明一較佳實施例泛用微小型無 引腳封裝結構的剖面示意圖；以及 第8圖至第12圖繪示爲依照本發明一較佳實施例泛 用微小型無引腳封裝結構的製作流程示意圖。 圖式之標示說明： 1〇〇 :四排引腳封裝 102、202 :外引腳 104、204 :封裝膠體 200 :雙排引腳封裝 300、400 :泛用微小型無引腳封裝 302、402 :凹面 304、404 :端子 306、406、500、600 :絕緣基材 502 :端子 502a、602a :導體插塞 504 :黏著層 506 :晶片 508 :銲墊 510 :銲線（wire ) 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） --------丨丨丨裝·-------訂·---—---線 (請先閱讀背面之注意事項再填寫本頁) 508773 7902twf.doc/009 ^ __B7______ 五、發明說明（夕） 512 :封裝膠體 5 14、614 =圖案化線路/晶片配置區域 (請先閱讀背面之注意事項再填寫本頁) 較佳實施例 首先請參照第3圖，其繪示爲依照本發明一較佳實施 例與四排引腳封裝相容之泛用微小型無引腳封裝結構的下 視圖。由泛用微小型無引腳封裝300的下視圖可淸楚看出， 其絕緣基板306的四個端面上分別具有多個凹面3〇2，而 每一凹面302上更配置有一導體層以形成多個端子304。 其中，配置於凹面302上之導體層例如爲銅或其他導電性、 附著性良好之材質。 接著請參照第4圖，其繪示爲依照本發明一較佳實施 例與雙排引腳封裝相容之泛用微小型無引腳封裝結構的下 視圖。由泛用微小型無引腳封裝400的下視圖可淸楚看出， 其絕緣基板406的其中兩個端面上分別具有多個凹面402， 而每一凹面402上更配置有一導體層以形成多個端子404。 其中，配置於凹面402上之導體層例如爲銅或其他導電性、 附著性良好之材質。 經濟部智慧財產局員工消費合作社印製 上述第3圖與第4圖係對於本發明較佳實施例中單一 個泛用微小型無引腳封裝結構的外觀作描述。接著請參照 第5圖，其繪示爲適用於四排引腳封裝之絕緣基板結構的 上視圖。絕緣基板500上的適當位置配置有數個導體插塞 502a，這些導體插塞502a可將絕緣基板500分隔成多個圖 案化線路/晶片配置區域514,這些圖案化線路/晶片配置區 域5丨4上例如配置有多個銲墊以及一圖案化線路。其中， 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 508773 A7 B7 7902twf.doc/0〇9 五、發明說明（f) 圖案化線路的一端與圖案化線路/晶片配置區域514上的銲 墊電性連接，圖案化線路的另一端則與導體插塞502a電性 連接。而圖案化線路/晶片配置區域514上的靜塾例如係藉 由銲線製程（wire bonding )與晶片上的銲墊電性連接，故 配置於絕緣基板500上晶片可藉由圖案化線路7晶片配置區 域514上的圖案化線路與端子電性連接。 接著請參照第6圖，其繪示爲適用於雙排引腳封裝之 絕緣基板結構的上視圖。第6圖中所繪示的絕緣基板5〇〇 與第5圖中所繪示的絕緣基板相似’唯一差異之處在 於其導體插塞502a配置的方式不同。在第6圖中’導體插 塞502a僅配置於圖案化線路/晶片配置區域514的其中兩 側邊。 接著請同時參照第5圖、第6圖與第7圖’第7圖繪 示爲依照本發明一較佳實施例泛用微小型無引腳封裝結構 的剖面示意圖。將整塊的絕緣基板500上經過晶片貼附（die attachment )、銲線製程（wire bonding )、封膠（molding )以 及切割（singulation )之後（沿者圖中的虛線切割）’即會將 絕緣基板500上的導體插塞502a切割成端子502。其中， 絕緣基板500上例如配置有一晶片5〇6，而晶片5〇6與絕 緣基板5〇〇之間係藉由一黏著層5〇4，例如銀膠，進行貼 附。此外，晶片5〇6與端子502之間的電性連接係藉由銲 線510將晶片506上的銲墊518與絕緣基板500上圖案化 線路（未繪示）的一端電性連接，即可達成。 請參照第8圖至第12圖，其繪示爲依照本發明〜較 8 ------------裝—--丨！訂--------1-線^ (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） sosrn 7902twf.doc/009 A7 B7 經濟部智慧財產局員工消費合作社印製 發明說明（1) 佳實施例泛用微小型無引腳封裝結構的製作流程示意圖。 首先請參照第8圖，提供一絕緣基板5 0 0，絕緣基板 5〇0中配置有多個導體插塞502a，導體插塞502a的排列方 式例如第5圖或第6圖所繪示，導體插塞502a的形成方式 例如係以傳統之塞孔製程製作於絕緣基板500上。此外， 絕緣基底500的表面上配置有一圖案化線路與多個銲墊（未 繪示），圖案化線路的一端會與銲墊電性連接，而圖案化線 路的另一端則會與導體插塞502a電性連接。 接著請參照第9圖，接著將晶片506分別貼附於絕緣 基板5〇〇上的適當位置，晶片506貼附的方式例如係藉由 一黏著層貼附，而黏著層之材質例如爲銀膠。 接著請參照第10圖，進行一銲線的動作將晶片506 上的銲墊與絕緣基底500的表面上的銲墊電性連接，使得 晶片506可藉由銲線510、圖案化線路而與導體插塞502a 電性連接。由於晶片506與導體插塞502a之間的電性連接 係藉由銲線510完成，銲線製程使得整體封裝在設計上更 具有彈性。 接著請參照第11圖，接著進行一封膠製程，將搭載 有晶片506之絕緣基底500置入一封膠模具（未繪示）中， 並將一封裝膠體512注入模具的模穴中。封裝膠體512會 將晶片506、銲線510包覆並固著於絕緣基板500上，以 達到保護晶片500與銲線510的目的。 最後請參照第12圖，在封膠製程之後進行--切割步 驟，以將各個晶片506切成多個的封裝單元（umt )，經過 先 閱 讀 背 項 再 填 寫 本 頁B Baizhi responds to different packaging products, such as TSOP, sop, SON BCC, QFp, QFN and other four-row pins or double-row pins = Different pins are required to invest in difficult equipment. Different seal #types_ require different seal molds (moldlng) to seal the mold (moldmg). Investment in different molds costs a lot of cost. / ^ In addition, different package types require different jigs to perform slag removal / shear (D / T) operations, and different jigs to perform forming / cutting (F / S) operations. Whether it is slag removal / shearing or forming / cutting, the cost and time invested in the fixture is considerable. Therefore, an object of the present invention is to provide a packaging structure that is compatible with a four-row or double-row package in the JEDEC standard, and can effectively reduce manufacturing costs. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs To achieve the above-mentioned object of the present invention, a packaging structure is proposed including an insulating substrate, a chip, and a packaging gel. Wherein, a patterned circuit is arranged on the insulating substrate, and a plurality of concave surfaces are arranged on the end surface of the insulating substrate, and a conductive layer is arranged on each concave surface to form a terminal (Termmal). The wafer is arranged on an insulating substrate, and the wafer is electrically connected to the terminal on the end surface through the patterned circuit on the insulating substrate. The wafer and the patterned circuit are, for example, wire bonded. Electrical connection. In addition, the encapsulant system is disposed on the insulating substrate and the wafer to cover and fix the wafer on the insulating substrate. In the package structure of the present invention, the terminal arranged on the end surface of the insulating substrate has, for example, a semicircular concave structure. In the package structure of the present invention, for example, the terminal on the end face is made before the absolute 4 paper size is applicable to the Chinese National Standard (CNS) A4 specification ⑵ G X 297 issued by the public) ------- Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Print 508773 7902twf.d〇c / 009 _B7_ V. Description of the invention (/) Drill holes at the appropriate position on the edge substrate to form a through hole, and perform a plugging process to pierce the conductor layer into the through hole. After that, the insulating substrate is cut. In the packaging structure of the present invention, the terminals are arranged on, for example, the four end faces of the insulating substrate, and through proper design of the patterned lines on the insulating substrate, a universal microchip compatible with a four-row pin package can be manufactured. Small leadless package structure (USON). In the packaging structure of the present invention, the terminals are arranged on, for example, two end faces of the insulating substrate. Through proper design of the patterned lines on the insulating substrate, a universal micro-mini (Pin package junction USON) 〇 Through the design of the patterned circuit on the insulating substrate, the present invention can easily produce a dual-row package and a four-row package with the proper configuration of the terminals on the end surface of the insulating substrate. Compatible universal micro-miniature leadless package (USON). In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 shows It is a structural schematic diagram of a conventional four-row pin package; FIG. 2 illustrates a structural schematic diagram of a conventional dual-row pin package; and FIG. 3 illustrates a phase comparison with a four-row pin package according to a preferred embodiment of the present invention. Bottom view of Rongzhi's micro-miniature leadless package structure; Figure 4 shows a dual-row pin package according to a preferred embodiment of the present invention. ------ Order --------- 'Old (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 508773 7902twf.doc / 009 _B7__ V. Description of the invention (¥) The bottom view of the universal micro-pinless package structure compatible with packaging; Figure 5 is shown as applicable to four Top view of an insulated substrate structure for a row-lead package; Figure 6 shows a top view of an insulated substrate structure suitable for a two-row pin package FIG. 7 is a schematic cross-sectional view of a general-purpose micro-miniature leadless package structure according to a preferred embodiment of the present invention; and FIGS. 8 to 12 are general-purpose micro-lead packages according to a preferred embodiment of the present invention. Schematic of the manufacturing process of a small leadless package structure. Description of the drawing: 100: Four-row lead packages 102, 202: Outer leads 104, 204: Packaging gel 200: Double-row lead packages 300, 400: General purpose micro-miniature leadless packages 302, 402 : Concave surface 304, 404: Terminals 306, 406, 500, 600: Insulating substrate 502: Terminals 502a, 602a: Conductor plug 504: Adhesive layer 506: Wafer 508: Pad 510: Wire (wire) This paper standard applies China National Standard (CNS) A4 Specification (2〗 0 X 297 mm) -------- 丨 丨 丨 Installation ------- Order --------- (Please first Read the notes on the back and fill in this page) 508773 7902twf.doc / 009 ^ __B7______ V. Description of the invention (Even) 512: Packaging gel 5 14, 614 = Patterned circuit / chip configuration area (Please read the notes on the back before (Fill in this page) First, please refer to FIG. 3, which is a bottom view of a general-purpose micro-small leadless package structure compatible with a four-row pin package according to a preferred embodiment of the present invention. As can be clearly seen from the bottom view of the universal micro-miniature leadless package 300, the four end surfaces of the insulating substrate 306 have a plurality of concave surfaces 302, and a conductive layer is formed on each concave surface 302 to form Multiple terminals 304. The conductive layer disposed on the concave surface 302 is, for example, copper or other conductive materials with good adhesion. Please refer to FIG. 4, which illustrates a bottom view of a general-purpose micro-miniature leadless package structure compatible with a dual-row pin package according to a preferred embodiment of the present invention. As can be clearly seen from the bottom view of the universal micro-miniature leadless package 400, two end surfaces of the insulating substrate 406 respectively have a plurality of concave surfaces 402, and each concave surface 402 is further provided with a conductive layer to form multiple Terminals 404. The conductive layer disposed on the concave surface 402 is, for example, copper or other conductive materials with good adhesion. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The above-mentioned Figures 3 and 4 describe the appearance of a single universal micro-miniature leadless package structure in the preferred embodiment of the present invention. Please refer to FIG. 5 for a top view of an insulating substrate structure suitable for a four-row lead package. A plurality of conductor plugs 502a are arranged at appropriate positions on the insulating substrate 500. These conductor plugs 502a can separate the insulating substrate 500 into a plurality of patterned circuit / wafer configuration areas 514, and the patterned circuit / wafer configuration areas 5 and 4 For example, a plurality of bonding pads and a patterned circuit are arranged. Among them, 7 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 508773 A7 B7 7902twf.doc / 0〇 V. Description of the invention (f) One end of the patterned circuit and the patterned circuit / chip The pads on the configuration area 514 are electrically connected, and the other end of the patterned line is electrically connected to the conductor plug 502a. The quietness on the patterned circuit / wafer arrangement area 514 is, for example, electrically connected to the pads on the wafer by a wire bonding process. Therefore, the wafer disposed on the insulating substrate 500 can be patterned by the 7 circuit wafer. The patterned lines on the configuration area 514 are electrically connected to the terminals. Please refer to FIG. 6 for a top view of an insulating substrate structure suitable for a dual-row package. The insulating substrate 500 shown in Fig. 6 is similar to the insulating substrate shown in Fig. 5 '. The only difference is the way in which the conductor plugs 502a are arranged. In FIG. 6, the 'conductor plug 502a is disposed only on both sides of the patterned circuit / chip placement area 514. Next, please refer to FIG. 5, FIG. 6 and FIG. 7 at the same time. FIG. 7 is a schematic cross-sectional view of a general-purpose micro-small leadless package structure according to a preferred embodiment of the present invention. After the entire insulating substrate 500 is subjected to die attachment, wire bonding, molding, and singulation (cut along the dotted line in the figure), the insulation will be insulated. The conductor plug 502 a on the substrate 500 is cut into terminals 502. Wherein, a wafer 506 is arranged on the insulating substrate 500, and the wafer 506 and the insulating substrate 500 are attached by an adhesive layer 504, such as silver glue. In addition, the electrical connection between the chip 506 and the terminal 502 is to electrically connect the pad 518 on the chip 506 to one end of a patterned circuit (not shown) on the insulating substrate 500 through a bonding wire 510, Reached. Please refer to FIG. 8 to FIG. 12, which are shown in accordance with the present invention. Order -------- 1-line ^ (Please read the notes on the back before filling out this page} Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs This paper applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) sosrn 7902twf.doc / 009 A7 B7 Printed invention description printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (1) Schematic diagram of the manufacturing process of a general-purpose micro-miniature leadless package structure. First, please refer to Section 8 In the figure, an insulating substrate 500 is provided. A plurality of conductor plugs 502a are arranged in the insulating substrate 500. The arrangement of the conductor plugs 502a is shown in FIG. 5 or FIG. 6, for example. The formation of the conductor plugs 502a The method is, for example, made on the insulating substrate 500 by a conventional plugging process. In addition, a patterned circuit and a plurality of solder pads (not shown) are arranged on the surface of the insulating base 500, and one end of the patterned circuit is electrically connected to the solder pad The other end of the patterned circuit is electrically connected to the conductor plug 502a. Then refer to FIG. 9, and then attach the chip 506 to the appropriate position on the insulating substrate 500, and attach the chip 506. Way such as borrowing An adhesive layer is attached, and the material of the adhesive layer is, for example, silver glue. Next, referring to FIG. 10, perform a bonding wire operation to electrically connect the pads on the wafer 506 with the pads on the surface of the insulating substrate 500. The chip 506 can be electrically connected to the conductor plug 502a through the bonding wire 510 and the patterned circuit. Since the electrical connection between the chip 506 and the conductor plug 502a is completed through the bonding wire 510, the bonding wire process makes the whole The package is more flexible in design. Next, please refer to FIG. 11, and then perform an adhesive process. The insulating substrate 500 carrying the chip 506 is placed in an adhesive mold (not shown), and an encapsulating gel 512 It is injected into the cavity of the mold. The encapsulation gel 512 will cover and fix the wafer 506 and the bonding wire 510 on the insulating substrate 500 to achieve the purpose of protecting the chip 500 and the bonding wire 510. Finally, please refer to FIG. After the glue process, a dicing step is performed to cut each wafer 506 into multiple packaging units (umt). After reading the back item, fill in this page.
I I I 訂 I I 線 本紙張尺度_中國國家標準（CNS)A4 ϋ2]() x 297公髮) ⑽773 ⑽773 經濟部智慧財產局員工消費合作社印製 7902twf·d〇c/009 A7 —____—_B7 五、發明說明（Ϋ ) 切割後所___元在端面讀形_端子5〇2,其 係爲導體插塞5〇2a切割後所所形成。 綜上所述，本發明之封裝結構至少具有下列優點： 1.本發明之#裝結構在製作上，可以省去各種對應 同封裝型態之封膠模具、去渣/剪切治具以及成型/切難具 上的硏發與投資，可以很快速的切入市場。 2 ·本發明之泛用微小型無引腳封裝結構能夠與】E D £ c 標準封裝相谷，且能夠有效降低製作成本。 3·本發明之泛用微小型無引腳封裝結構不具有引腳或 是球（ball )，因此具有很高的組裝良率。 4·本發明之泛用微小型無引腳封裝結構由於不需要使 用導線架，故整體厚度較薄。 5·本發明封裝結構具有很高的設計彈性，僅需將絕緣 基板上的圖案化線路經過適當的設計、變化後，便可輕易 的製作出與雙排引腳封裝以及與四排引腳封裝相容之泛用 微小型無引腳封裝。 雖然本發明已以一較佳實施例揭露如上’然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） --I--I-----裝！ —訂·--- --線 (請先閱讀背面之注意事項再填寫本頁)III Order II Paper Size _China National Standard (CNS) A4 ϋ2] () x 297 public release) ⑽773 ⑽773 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7902twf · d〇c / 009 A7 —____—_ B7 5. Description of the invention (Ϋ) After cutting, the ___ element reads the shape of the terminal 502, which is formed after the conductor plug 502a is cut. In summary, the packaging structure of the present invention has at least the following advantages: 1. The #packing structure of the present invention can be manufactured in such a way that it can eliminate various sealing molds, slag removal / shearing fixtures and moldings corresponding to the same packaging type The development and investment on the cutting tool can quickly enter the market. 2 · The universal micro-small leadless package structure of the present invention can be compared with the standard package of E D £ c, and the production cost can be effectively reduced. 3. The universal micro-miniature leadless package structure of the present invention does not have pins or balls, and therefore has a high assembly yield. 4. The universal micro-miniature leadless package structure of the present invention has a small overall thickness because it does not require a lead frame. 5. The packaging structure of the present invention has high design flexibility, and the patterned lines on the insulating substrate need only be appropriately designed and changed to easily produce a package with a double row of pins and a package with a four row of pins. Compatible universal micro-miniature leadless package. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 specification (21〇 X 297 public love) --I--I ----- installed! —Order · --- --Line (Please read the notes on the back before filling this page)