TW508742B - Method of improving reliability of a dual damascene interconnection - Google Patents

Abstract

A method for improving reliability of a dual damascene interconnection is provided. A damascene opening and a plurality of dummy via holes adjacent to the damascene opening are formed simultaneously within a dielectric layer. The damascene opening connects to an underlying conductor or wire line. A barrier layer is formed in the damascene opening and the dummy via holes. A metal layer is formed on the barrier layer to fill both the damascene opening and the dummy via holes. The dielectric layer has a first coefficient of thermal expansion (CTE) greater than a second CTE of the barrier layer. The metal layer has a third CTE greater than the second CTE.

Description

508742 V. Description of the Invention (1) Field of the Invention The present invention relates to a method of dual damascene interconnection, especially a dual mosaic connection with a dummy contact window (via). Wire method to improve the reliability of copper dual damascene interconnects. Background note Copper dual damascene technology with low dielectric constant material

The formed inter metal dielectric (IMD) W is currently the most popular combination of metal interconnect processes, especially for high-volume I-degree, high-speed logic integrated circuit chip manufacturing and 〇 Deep sub-micro semiconductor processes below 18 microns. This is because copper has low resistance (30% lower than aluminum) and resistance to electromigration, and low dielectric constant materials can help reduce the RC delay between metal wires (R cde 1 ay )effect. Therefore, the copper-metal dual-damascene interconnect technology is becoming increasingly important in integrated circuit manufacturing processes 'and is bound to become the next-generation semiconductor process' interconnect technology. τ Please refer to FIG. 1. FIG. 1 is a partial cross-sectional view of a semiconductor wafer. FIG. ′ shows a typical dual damascene structure 11. As shown in Figure 1, the double structure J 1 1 is formed in a dielectric layer 20, which includes a lower contact window.

508742 V. Description of the invention (2) (v i a) structure 22 and an upper trench structure 23. The lower conductive line 14 is formed in a dielectric layer 12 and an upper copper conductive line 24 is filled in the upper trench structure 23. The upper-layer copper wires 24 and the lower-layer wires 14 can be connected to each other through the dielectric layer 12 and the protective layer 18 between the dielectric layers 20 through a via plug 22a. In order to prevent the copper metal filled in the dual damascene structure 11 from diffusing into the adjacent dielectric layer 20, a conventional method needs to form a barrier layer 25 on the surface of the dual damascene structure. Generally, the barrier layer 25 must have at least the following conditions: (1) good diffusion barrier properties; (2) good adhesion to copper metal and dielectric layers; (3) the resistance value should not be too high (< 1 〇〇〇 # Ω-cm); (4) good step coverage. Common barrier layer materials include titanium, titanium nitride (TiN), nitride button (TaN), and tungsten nitride (WN). , 〇 However, as shown in Figure 2, the conventional double-inlaid copper process often observes the phenomenon that a contact window opens (v i a 〇 p e η) 2 8. The opening of the contact window is mainly caused by (1) barrier broken or (2) contact, bottom via open. The first case mentioned above often occurs when the barrier layer is relatively fragile, while the second case occurs when the barrier layer is made of a tougher material. The former will cause the copper metal filled in the contact window to diffuse directly into the dielectric layer 20 through the cracks in the barrier layer 25, resulting in a leakage situation. The latter μ will cause metal disconnection due to the overhead of the contact window. Both will cause the upper steel

508742 V. Description of the invention (3) The wires 24 and the lower wires 14 cannot be connected, and the component or circuit is invalid. These two phenomena are described above. When the dielectric layer 20 is made of a low dielectric constant material having a high coefficient of thermal expansion (CTE), such as Si LK T1 ^ polymer-type low-dielectric Electrical materials or porous dielectric layers are even more serious.

Taking SiLKT 怍 as the dielectric layer 20 and tantalum nitride (TaN) as the copper metal dual damascene process of the barrier layer 25 as an example, due to the thermal expansion coefficients of Si LK TM, copper metal, and nitride nitride (TaN) 60ppmm / ° C, 17ppmA: and 3ppm / ° c, respectively. Therefore, after the metallized semiconductor wafer 10 undergoes the thermal process again, the thermal stress generated by the Si LK electrical layer 20 will cause thermal expansion. The tantalum nitride barrier layer 25 with a lower account coefficient is broken (^^ to ^ 导致 or causes the bottom of the contact window to become overhead, thereby causing the contact window to open. In addition, the contact window is opened. The vertical contact window (is0-via) It will be even worse. Summary of the invention Therefore, the main object of the present invention is to provide an improved dual-damascene process method to solve the above problems. Another object of the present invention is to provide a dual-damascene using a dummy contact window. The Quick-Line Method is used to improve the reliability of the copper-silver interconnection process.

Page 7 508742 V. Description of the invention (4) According to a preferred embodiment of the present invention, a bottom layer is included on the bottom layer, and the bottom layer includes a bottom layer, and a double insert including a wire groove is formed in the dielectric layer when the bottom layer is conductive. (Trench) structure, the contact window structure reaches the lower layer, and forms a plurality in the dielectric layer simultaneously in the dual damascene structure and a barrier layer; the structure on the barrier layer and the plurality of dummy contact grinding ( chemical mechanica In the double damascene structure, a double damascene is formed at the same time as the plurality of dummy contact windows (Plug). For example, the present invention first provides a semiconductor and a dielectric layer formed on the bottom layer and a line; a double damascene process is performed to Co-embedded structure, wherein the double mosaic structure package and a contact window structure and a line; and the same dummy contact window structure forming the contact window structure; the shape of the plurality of dummy contact window structures is equal to one A metal layer to fill the double mosaic window structure; and a chemical mechanical (polishing, CMP) process for embedding copper wires and a copper contact plug, Forming a dummy plug (d U jjj jjj y ^ in the dielectric layer has a first thermal expansion coefficient expansion coefficient, the metal layer has a second barrier layer has a thermal expansion coefficient of 12 smaller than the first thermal expansion coefficient ,; ^ "1", "2" thermal expansion coefficient. The second thermal expansion coefficient is greater than the advantages of using the present invention include: [n should be generated by thermal expansion of the dielectric layer: the second can be released by helping the dielectric layer to quickly dissipate heat. (Dissi \ 'Wide times, window 7 to

Pate heat), (3) dummy contact

508742 V. Description of the invention (5) The window can relax the elasticity of the yellow light process when the double mosaic structure is defined (the wide pr0cess window and (4) the dummy contact window can increase the strength of the isolated contact window (iso-via). Details of the invention First, please refer to FIG. 3. FIG. 3 is an enlarged top view of a part of a semiconductor wafer 40 that completes a dual-insertion interconnection process according to a preferred embodiment of the present invention. As shown in FIG. 3, the semiconductor wafer 40 includes a substrate. The electrical layer 42 is generally a spin-on (coated) low-k material such as FLARE? SiLKT. However, the present invention is not limited to spin-on- coating, S0C) low dielectric constant materials, other dielectric materials with high thermal expansion coefficient (generally CTE greater than 30 or 40), such as poly (arylene ether) polymer or P ary 1 ene compounds, polyimide polymers, fluorinated polyimide, HSQ or inorganic porous materials, etc., are all suitable for the scope of the present invention. In the present invention In a preferred embodiment, The dielectric layer 42 is composed of Si LK τ, and its thermal expansion coefficient is 60 ppm / ° c, which is about 20 times that of tantalum nitride (its thermal expansion coefficient is 3 ppm / ° C, which is subsequently used as a barrier layer). The dielectric constant of the low-dielectric material constituting the dielectric layer 42 is generally less than 3.0, and the thickness of the dielectric layer 42 is generally about several thousands angstroms (angstroms) to several micrometers (micrometers). ). For the convenience of describing the features of the present invention, other elements on the semiconductor wafer 40 are not shown in FIG.

Page 9 508742 V. Description of the invention (6) In FIG. 3, a double damascene interconnect structure 4 4 has been previously formed in the dielectric layer 4 2 and the double damascene has been filled with a metal 4 7 such as copper.内 连接 结构 4 4. In addition, a barrier layer (not shown in FIG. 3) is also formed in the dual damascene interconnect structure 4 4 before the deposition of the metal 4 7. The dual-mosaic interconnect structure 44 includes a wire channel structure 45 and a contact window structure 46 for communicating with other wires (not shown) below. In a preferred embodiment of the present invention, the dual-damascene interconnect structure 44 is formed using a wire slot-preferred (t r e n c h-f i r s t) dual damascene process. However, in other embodiments, the method of the present invention can also be applied to the formation of a dual-damascene process of other types of copper-metal interconnects, such as a contact window preferential dual-damascene process and self-alignment (361, 31, 2116 (1) dual-damascene process 、 Buried # Inscription stop (buriedetchst ο p) double inlay process, partial-via process or buried etch mask double inlay process. Still referring to Figure 3, double inlay In the surrounding dielectric layer 4 2 of the interconnect structure 4 4, there are a plurality of dummy contact window structures 4 8. The minimum distance between the dummy contact window structure 4 8 and the dual mosaic interconnect structure 4 4 is defined as L!, And The minimum distance between two adjacent dummy contact window structures 48 is defined as L 2. It should be noted that Li and L are optimized depending on the design conditions of the product to achieve the closest arrangement and the smallest electrical interference. This purpose can be achieved by IC design engineers through experience and computer-aided tools such as optimizing simulation programs, so it will not be repeated here. The dummy contact window structure 48 needs to stagger the product's internal wiring pattern during layout. More specifically, False Contact window 48 as long as the structure is not the same connection in the layout

Page 10 508742 Five 'Explanation of the invention (7) The lower wire is sufficient. FIG. 4 is a schematic sectional view of FIG. 3 along the tangent line II. As shown in FIG. 4, since the dummy contact window structure 48 and the contact window structure 46 are simultaneously formed in the dielectric layer 42 and the metallization process is performed at the same time, each dummy contact window structure 48 is filled in. It is filled with the same barrier layer 5 2 and metal 4 7 as those filled in the dual damascene interconnect structure 4 4. By filling the metal 4 7 in the dummy contact window structure 48, the method of the present invention can help the dielectric layer 42 dissipate heat quickly in the subsequent thermal process, and effectively release the heat generated by the thermal expansion of the dielectric layer 42. Of stress. In addition, in addition to solving the thermal expansion problem of the dielectric layer 42, the method of the present invention can relax the yellow light process window when defining the dual damascene structure. Next, please refer to FIG. 5 to FIG. 7. The following describes the preferred embodiment of the present invention by referring to FIG. 5 to FIG. First, as shown in FIG. 5, the surface of the semiconductor wafer ^ 0 includes a bottom layer 62, which can be a silicon substrate or another layer of low dielectric constant material. A silicon nitride layer 64 covers the surface of the bottom layer 62 and a dielectric layer. 70 is formed on the silicon nitride layer 64. A conductive layer = 1 is formed in the bottom layer 62, for example, a metal wiring in the lower layer. The dielectric layer 701 has a high-level structure, including a stop layer 68 between two low dielectric constants and two Gauss; the electrical dimensional material layer 66a, and the low dielectric constant material layers 66a and b, which are generally used. Spin spin-0n coated) technology is formed, which can be the organic low commonly used in Zhang Zhijing &

Page 11 ^ υδ / 42 V. Description of the invention (8) " What is the electric preparation η? For example, FLARETM Cheng Xi from A1 1 ied SignaW 丨 j products 〇h ^ _ 口, D〇w Chemical The company produces SiLKTM, arylene phase, 1 B (poly (arylene ether) P0yyffler) or Parylene materials. People temple and so on. However, the present invention is not limited to the dielectric constants of the spin-coated dielectric material, the dielectric constant material layers 66 and a, and the dielectric constants of the layers 6 6 a and b are less than about 3.0, which is about two thousands of angstroms. In addition, the surface of the low-dielectric-constant material layer 66b is formed with a protective layer 72, such as a silicon nitride layer or a silicon oxide layer, to protect the dielectric layer 700.

Next, as shown in FIG. 6, a wire groove priority Ur *, ench-first) dual damascene process is performed, and the wire groove structure 75 is formed before the low dielectric constant material layer 66b. The formation of the wire groove structure 75 is completed by the conventional steam-light and money-engraving processes', and therefore will not be described again. Next, a photoresist layer 79 is formed over the dielectric layer 70. The photoresist layer 79 includes a contact window pattern opening 7 6 provided in the wire groove structure 75 and a dummy contact window pattern opening 7 8 respectively. In the subsequent engraving process, a contact window structure and a dummy contact window structure are formed in the dielectric layer 70. Next, as shown in FIG. 7, a dry etching process is performed, and at the same time, the dielectric layer 70 is etched through the contact window pattern opening 7 6 and the dummy contact window pattern opening 7 8 in the photoresist layer 7 9 and penetrates the silicon nitride layer 6 4 Until the bottom 6 2. The light P is subsequently removed and the layer 79 is removed. At this time, the dual-damascene structure 74 is completed in the 'dielectric layer 70', including the wire groove structure 75 and the contact window structure 76, and a dummy contact window structure 78 is formed around the dual-damascene structure 74 at the same time. Subsequently, on the surface of the wire groove 75,

Page 12 508742 V. Description of the invention (9) The contact window structure 7 6 ′ surface and the dummy contact window structure 7 8, a barrier layer 82 is formed on the surface.较佳 In a preferred embodiment, the barrier layer 82 is composed of a nitride button (TaN) or a nitride button (TaN) / tantalum (Ta) composite layer having good adhesion properties. However, other materials selected from the group consisting of titanium nitride (TiN), titanium tungsten alloy (TiW alloy), button tungsten alloy (TaW au〇y), or other similar barrier materials are also suitable.于 发明。 In the present invention. The barrier layer 8 2 is at a temperature of about 300 to 400 ° C, preferably 30 (TC environment, using physical! F-phase & physical vapor deposition (PVD) or high-density electropolymerization It is formed by PVD technology, and its thickness is between about 100 and 600 angstroms, preferably between 50,000 and 400 angstroms. In addition, the method for forming the barrier layer 82 can be selected from laser or chemical methods. Vapor deposition (CVD) technology, which is well known to those skilled in the art, will not be described in detail. Next, the dual damascene structure 74, including the wire groove structure 75 and the contact window structure 76, is filled in by electroplating. A copper metal layer such as "electroless copper deposition (ECD) technology"

Operation 'and overlying the protective layer 72. A copper seed layer (not shown) is generally formed before copper metal is plated. The copper seed layer can be formed using pvD technology or other methods known to those skilled in the art. Finally, a chemical mechanical grinding (CMp) process is performed. ^ ^ The copper metal layer 81 is located above the protective layer 72, and the double-mounting structure 7 4 and the dummy contact window structure 7 are left. 8, in the copper metal layer 8!

Page 13 508742 Fifth, the description of the invention (ίο), complete the production of the double mosaic internal wiring of the present invention. Compared with the conventional dual-damascene interconnect method, the method of the present invention helps the dielectric layer 70 to dissipate heat quickly in the subsequent thermal process by filling the metal in the dummy contact window structure, and effectively releases the Stress due to thermal expansion of the dielectric layer 70. Especially when the dielectric layer 70 is made of an organic low-dielectric constant material having a relatively high thermal expansion coefficient, such as SiK, or made of a porous inorganic low-dielectric constant material, the advantages of the method of the present invention are more remarkable. In addition to solving the thermal expansion problem of the dielectric layer 70, the method of the present invention can relax the yellow light process window during the definition of the dual damascene structure and reduce the difficulty of the process. The method of the present invention can effectively solve the contact window opening phenomenon common in the conventional technology. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 14 508742 Brief description of the diagrams Brief description of the diagrams Figures 1 and 2 are cross-sectional diagrams of the conventional dual-mosaic interconnect structure. FIG. 3 is an enlarged top view of a part of a semiconductor wafer that completes a dual damascene interconnect process in a preferred embodiment of the present invention. FIG. 4 is a schematic cross-sectional view taken along the line II ′ of FIG. 3. FIG. 5 to FIG. 7 are schematic views of a method according to a preferred embodiment of the present invention. Explanation of Symbols 10 Semiconductor wafer 11 Double damascene structure 12 Dielectric layer 14 Conductive layer 18 Protective layer 20 Dielectric layer 22 Contact window structure 2 2a Contact plug 23 Wire groove structure 24 Upper copper wire 25 Barrier layer 40 Semiconductor wafer 42 Dielectric layer 44 Double damascene structure 45 Wire slot structure 46 Contact window structure 47 Metal 48 Virtual delta and contact window structure 52 Barrier layer 60 Semiconductor wafer 61 Conductive layer 62 Bottom layer 64 Silicon nitride layer 6 6 a λ b Low dielectric Electrical constant material layer 68 Stop layer 70 Dielectric layer 72 Protective layer 74 Double damascene structure❹

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Claims (1)

508742 VI. Scope of patent application 1. A method for making dual damascene interconnects, the method includes the following steps: providing a semiconductor wafer including a bottom layer and a dielectric layer formed on the bottom layer And the bottom layer includes a lower layer wire, the dielectric layer has a coefficient of thermal expansion (CTE); a double damascene process is performed, and a contact window (via) is sequentially formed in the dielectric layer To access the lower-layer wire and a trench, wherein the contact window and the trench form a double mosaic structure; while forming the contact window, a plurality of dummy structures are formed in the dielectric layer in the area around the contact window; (Dummy) contact window; at least one barrier layer is formed in the dual damascene structure and the plurality of dummy contact windows, and the barrier layer has a second thermal expansion coefficient (CTE); in the barrier layer Forming a metal layer thereon, filling the dual damascene structure and the plurality of dummy contact windows; and performing a chemical mechanical polishi ng, CMP) process to form a double damascene copper wire and a copper contact plug in the double damascene structure, and simultaneously form a dummy plug in each of the plurality of dummy contact windows; wherein the metal layer Has a third coefficient of thermal expansion (CTE), the second coefficient of thermal expansion is smaller than the first coefficient of thermal expansion, the third coefficient of thermal expansion is greater than the second coefficient of thermal expansion, and the dummy plug can be released in a thermal process due to the Stress caused by thermal expansion of the dielectric layer to avoid a contact Page 17 508742 VI. Scope of patent application The via open phenomenon occurred. 2 · The method according to item 1 of the patent application, wherein the dielectric layer is composed of SiLKT. 3. The method according to item 1 of the patent application scope, wherein the first thermal expansion coefficient is greater than 50 p p m / ° C. 4. The method according to item 1 of the patent application range, wherein the second thermal expansion coefficient is less than 10 ppm / ° C. 〇. According to the method of claim 1, wherein the barrier layer is selected from one of the following combinations: nitride button (TaN), titanium nitride (TiN), titanium tungsten alloy (TiW alloy), Tantalum tungsten alloy (TaW alloy), nitride button (TaN) / tantalum (butyl 3) composite layer and nitride button (^ & "/ titanium nitride (1 ^^ 〇 / button (^ 3) composite layer. 6 · The method of claim 5 in which the barrier layer is formed by using a physical vapor deposition (PVD) technique and / or chemical vapor deposition (CVD) ) Technology o 508742 VI. Scope of patent application 8. A method for improving the reliability of a damascene interconnect, the method includes the following steps: providing a semiconductor wafer including a bottom layer and a dielectric layer formed on the bottom layer; and The bottom layer contains a lower-layer wire; at the same time, a mosaic opening structure and a plurality of dummy contact window structures are formed around the mosaic structure in the dielectric layer, wherein the mosaic structure leads to the lower-layer wire; at the same time in the mosaic opening Forming a barrier layer in the structure and the plurality of dummy contact window structures; and forming a metal layer on the barrier layer to fill the mosaic opening structure and the plurality of dummy contact window structures; wherein the dielectric layer has A first coefficient of thermal expansion (CTE), the barrier layer has a second coefficient of thermal expansion, and the second coefficient of thermal expansion is smaller than the first coefficient of thermal expansion. 9. The method of claim 8 in which the dielectric layer is composed of SiLKT. 10. The number of methods as in item 8 of the scope of patent application is greater than 50 ppm / ° C. 1 1. The number of methods according to item 8 of the scope of patent application is less than 10 ppm / ° C. Wherein the first thermal expansion system wherein the second thermal expansion system 〇 Page 19, 508742 6. Application for Patent Scope 1 2. The method according to item 8 of the Patent Scope, wherein the barrier layer is selected from one of the following combinations: tantalum nitride (TaN), titanium nitride (T i N) , Titanium tungsten alloy (TiW alloy), group casting alloy (TaW alloy), nitride group (TaN) / group (Ta) composite layer and tantalum nitride (TaN) / titanium nitride (TiN) / tantalum (Ta) composite Layer 0 parameters Page 20