TW507370B - A twin bit cell flash memory device and its fabricating method - Google Patents
A twin bit cell flash memory device and its fabricating method Download PDFInfo
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Description
507370 五、發明說明(1) 發明之領域 本發明係提供一種雙位元(twin bi t cel 1 )快閃式記 憶體(flash memory dev ices)結構及其製作方法。 背景說明 唯讀記憶體(Read only memory,ROM)元件是一種用 來儲存資料的半導體元件,由複數個記憶單元(memory c e 11)所組成:如今已廣泛應用於電腦的資料儲存與記 憶。一般依資料儲存方式,可將唯讀記憶體分為罩幕式唯 讀記憶體(M a s k R 0 Μ )、可程式化唯讀記憶體 (Programmable ROM,PROM)、可抹除且可程式化唯讀記憶 體(Erasable programmable ROM,EPROM)、可電除且可程 式化唯讀記憶體(Electrically erasable programmable ROM,EEPR0M)等數種。 不同於其他唯讀記憶體使用多晶石夕或金屬之浮動閘極 儲存電荷,氮化物唯讀記憶體(n i t r i d e r e a d ο η 1 y memory,NR〇M)之主要特徵為使用氮化矽之絕緣介電層作 為電荷儲存介質(charge trapping medium)。由於氮化石夕 層具有高度之緻密性,因此可使經由M〇S電晶體隧穿 (tunnellnS)進入至氮化矽層中的熱電子陷於(trap)其 中’進而形成一非均勻之濃度分佈,以加快讀取資料速度507370 V. Description of the invention (1) Field of the invention The present invention provides a double bit (twin bi t cel 1) flash memory dev ices structure and a manufacturing method thereof. Background Description A read only memory (ROM) device is a semiconductor device used to store data. It is composed of multiple memory cells (memory c 11): it is now widely used in computer data storage and memory. Generally, according to the data storage method, the read-only memory can be divided into a mask-type read-only memory (M ask R 0 Μ), a programmable ROM (programmable ROM, PROM), erasable and programmable There are several types of read-only memory (Erasable programmable ROM (EPROM)), electrically erasable and programmable read-only memory (EPRROM). Unlike other read-only memories that use polycrystalline stone or metal floating gates to store charge, nitride read-only memory (nitrideread ο η 1 y memory (NROM)) is mainly characterized by the use of silicon nitride insulating media The electrical layer acts as a charge trapping medium. Due to the high density of the nitride stone layer, the hot electrons entering the silicon nitride layer through MOS transistor tunneling can be trapped therein, thereby forming a non-uniform concentration distribution. To speed up reading data
DU/J/U 五、發明說明(2) " — e -- 並避免漏電流。 綠#二參考圖一至圖四,圖一至圖四為習知製作氮化物唯 I二ϊΓ體的方法示意圖。如圖一所示,習知製作氮化物唯 =圯^體的方法是先提供一包含有Ρ型矽基底(si 1 icon a S e。 2之半導體晶片1 0,接著利用一溫度範圍7 5 (TC〜 ^〇〇°c之氧化製程來形成一 50〜15〇埃(angstr〇m,A )的 ^化,,矽基底1 2表面,用來當作底氧化層1 4。隨後進行 低壓 ^ 相沈積(low pressure vapor deposition, LPCVD)f程、於底氧化層14表面沈積一厚度為20〜150埃 (A )之氮化石夕層16,當作滯留電子層(charge trapping 1 a y e Γ )。袁後再於9 5 0°C之高溫環境中,進行一回火製程 3 0二知以修補氮化石夕層1 6的結構,並通入水蒸氣以進行濕 式氧,而在氮化矽層1 6表面形成一厚度為5 0〜1 5 0埃(A ) 之S氧矽化物(s i 1 i c ο η ο X y〜n i t r i d e )層,作為上氧化層 1 8 °其中’形成於矽基底1 2表面上之底氧化層1 4、氮化矽 層16以及上氧化層18,便合稱為0N0層20。 然後如圖二所示,在_〇層2〇表面形成一光阻層(未顯 不)’並進行一黃光製程以及蝕刻製程,於光阻層中形成 圖案用來定義位元線(b丨t 1 i n e )的位置。接下來利用光阻 層的圖案作為遮罩(mask) 22,進行一乾蝕刻製程以去除 未被遮罩2 2覆蓋之上氧化層1 8以及氮化矽層1 6,並蝕刻部 为之底氧化層14至一預定厚度。隨後進行一 _ (arsenic)DU / J / U 5. Description of the invention (2) " — e-and avoid leakage current. Green # 二 refers to FIGS. 1 to 4, which are schematic diagrams of a conventional method for manufacturing a nitride-only I 2 ϊ Γ body. As shown in Fig. 1, a conventional method for making a nitride-based material is to first provide a semiconductor wafer 10 including a P-type silicon substrate (si 1 icon a Se. 2), and then use a temperature range 7 5 (TC ~ ^ 00 ° C oxidation process to form a 50 ~ 150 angstrom (angstrom), A), the surface of the silicon substrate 12 is used as the bottom oxide layer 14. Then low pressure is performed ^ Low pressure vapor deposition (LPCVD) process. A nitride nitride layer 16 with a thickness of 20 ~ 150 angstroms (A) is deposited on the surface of the bottom oxide layer 14 as a charge trapping 1 aye Γ. In the high temperature environment of 950 ° C, Yuan Hou then performed a tempering process 300 to repair the structure of the nitrided layer 16 and passed water vapor to perform wet oxygen. A layer of silicon oxide (si 1 ic ο η ο X y ~ nitride) with a thickness of 50 to 150 angstroms (A) is formed on the surface of layer 16 as an upper oxide layer 18 ° where 'formed on a silicon substrate 12 The bottom oxide layer 14 on the surface, the silicon nitride layer 16 and the upper oxide layer 18 are collectively referred to as the 0N0 layer 20. Then, as shown in FIG. A photoresist layer (not shown) is formed on the surface, and a yellow light process and an etching process are performed. A pattern is formed in the photoresist layer to define the position of the bit line (b 丨 t 1 ine). Next, the photoresist is used. The pattern of the layer is used as a mask 22, and a dry etching process is performed to remove the oxide layer 18 and silicon nitride layer 16 not covered by the mask 2 2 and the etching layer 14 to a predetermined oxide layer Thickness, followed by an _ (arsenic)
第6頁 五、發明說明(3) 離子佈植製程,佈值離子濃度為2〜4, 10 15/cm2,能量為 5〇Kev’_以於石夕基底12中形成複數個摻雜區,以作為記憶 ••之位元線2 4 ’或者稱為埋藏式沒極(匕u Γ丨e d d r a i η )。然 後將遮罩2 2完全去除。 、 如圖二所示’利用一熱氧化法(thermal oxidation) ^位το線2 4上方表面形成一場氧化層2 6 ,作為各氮化矽層 線=間的離’同時利用該熱氧化製程之溫度活化各位元 、、曰 之換質。最後如圖四所示,於0N0層20表面沉積一 曰曰石夕層或多/曰石夕化金屬層(polys i 1 icide),作為字元線 由於氮化物唯讀記憶體是以該滯留電子層(charge 士ppinglayer)作為電荷儲存介質,因此在進行寫入; —= 熱電子會依射入能量不同而於該滯留電子層中形 sec布曲線’並且谷易發生電子二次入射(electronPage 6 V. Description of the invention (3) Ion implantation process, the cloth ion concentration is 2 ~ 4, 10 15 / cm2, and the energy is 50Kev'_ to form a plurality of doped regions in the Shixi substrate 12, As a memory, the bit line 2 4 ′ is also called a buried type pole (dagger u Γ 丨 eddrai η). Then the mask 2 2 is completely removed. As shown in Figure 2, a thermal oxidation method is used to form a field oxide layer 2 6 on the surface above line 2 4 as the silicon nitride layer line = separation. At the same time, the thermal oxidation process is used. The temperature activates the change of quality of each element. Finally, as shown in FIG. 4, a polysilicon layer or polysilicon layer (polys i 1 pesticide) is deposited on the surface of the 0N0 layer 20 as a word line due to the nitride read-only memory. The charge layer is used as a charge storage medium, so it is being written; — = hot electrons will distribute in the shape of the stagnation electron layer depending on the injected energy, and valleys are susceptible to secondary electron incidence.
= dary injecti〇n)而形成尾狀電子分布⑽ 所1 以及荷廣域分布(wider charge distribution 八右f後貝進行抹除程序時’電洞射入該滯留電子層後 :i、、ι線無法與電子之分布曲線完全重疊,因而會造成 1 ^ :與電子完全結合(recombine),進而造成抹除不: 王或所需抹除時間較長的問題。 發明概述= dary injecti〇n) to form a tail-shaped electron distribution ⑽ 1 1 and the wide charge distribution (wider charge distribution) When the erase process is performed after the hole is injected into the retained electron layer: i ,, ι lines Can not completely overlap with the distribution curve of electrons, so it will cause 1 ^: complete recombine with electrons, which will cause the problem of erasing not: King or the long erasing time required. Summary of the invention
第7頁 507370 五、發明說明(4) 本發枓之主要目的在於提供一種雙位元快閃式記~憶體 元件結構,以增加記憶單元密度(m e m 〇 r y c e 1 1 d e n s i t y ) 並可解決習知氮化物唯讀記憶體抹除不完全的問題。 本發明之另一目的在於提供一種快閃式記憶體元件的 製作方法,以製作一種高積集度之雙位元快閃記憶體元 件,同時可以避免抹除不完全的問題以及增加資料保存 (data retention)的可靠度(reliability)。 在本發明之最佳實施例中,是先於一矽基底表面形成 一閘極氧化層,然後於該閘極氧化層表面形成一多晶鍺化 石夕(polysilicon germanium, S i i_xGe x, x = 0.0 5 〜1.0) 層。隨後進行一離子佈值製程,於該多晶鍺化矽層中形成 至少一絕緣區域,以分隔該多晶鍺化矽層成兩不相連續的 導電區域,形成一雙位元結構。接著於該多晶鍺化矽層表 面形成一介電層,並進行一黃光暨蝕刻製程以蝕刻部份之 該介電層以及該多晶錯化石夕層,形成該浮動閘極。最後於 該浮動閘極上形成一控制閘極。 由於本發明是以一導電層作為滯留電子層,並利用一 氧化區域將其分隔成兩不相電連接之捕捉電子區域5因此 兩區域可分別進行儲存與讀取的動作而形成一雙位元結 構,同時由於該二捕捉電子區域係由多晶鍺化矽之導電層Page 7 507370 V. Description of the invention (4) The main purpose of the present invention is to provide a two-bit flash memory ~ memory element structure to increase the memory cell density (mem 〇ryce 1 1 density) and solve the problem. Know the problem of incomplete erasure of nitride read-only memory. Another object of the present invention is to provide a method for manufacturing a flash memory device, so as to produce a high-integration dual-bit flash memory device, while avoiding the problem of incomplete erasure and increasing data storage ( data retention). In the preferred embodiment of the present invention, a gate oxide layer is formed on the surface of a silicon substrate, and then a polysilicon germanium (Si i_xGe x, x = 0.0 5 to 1.0) layers. Subsequently, an ion distribution process is performed to form at least one insulating region in the polycrystalline silicon germanium layer to separate the polycrystalline silicon germanium layer into two discontinuous conductive regions to form a two-bit structure. Then, a dielectric layer is formed on the surface of the polycrystalline silicon germanide layer, and a yellow light and etching process is performed to etch a part of the dielectric layer and the polycrystalline silicon fossil layer to form the floating gate. Finally, a control gate is formed on the floating gate. Since the present invention uses a conductive layer as the retained electron layer and uses an oxidized region to separate it into two capture electron regions 5 that are not electrically connected, the two regions can be stored and read separately to form a double bit. Structure, because the two electron-trapping regions are made of a polycrystalline silicon germanium conductive layer
507370 五、發明說明(5) 所構成,,所以電子與電洞的結合效率(c 〇 m b i n a t i ο η efficiency)很高,*因此可以避免/抹除不完全的問題以及 增加資料保存(data retention)的可靠度 (reliability)0 發明之詳細說明 請參考圖五至圖八,圖五至圖八為一本發明製作之雙 位元快閃記憶單元的方法示意圖。如圖五所示,本發明之 雙位元快閃記憶單元的製作方法是先提供一包含有P型矽 基底(silicon base)8 2之半導體晶片8 0 ’接者經南溫氧化 (high temperature oxidation)形成 5 0〜15 0埃 (angstrom,A )的氧化矽層於基底82表面,用來當作閘極 氧化層84。隨後進行一通入有矽甲烷(Si iane,si H4)、鍺 烧(germane, GeH 4)和氫氣(hydrogen)且沉積溫度介於450 C〜620C間的化學氣相沈積(chemical vapor deposition,CVD)製程,以於閘極氧化層84表面沈積一厚 度為5 0 0〜1 〇 〇 〇埃(a )之多晶鍺化秒(p〇iySiiic〇rl geTmanium, Si^xGex, X = 0.05〜1·〇)層作為導電層 86。 然後於導電層86表面形成一光阻層88,並於光阻層88 中定義出導電層8 6中之絕緣區域8 7位置的圖案,接著進行 一佈植能量約為20〜80 KeV且離子佈植劑量约為1〜2x1 0 18/cm的離子佈值製程,以將一高濃度氧摻質(〇xygen507370 V. Composition of invention (5), so the combination efficiency of electrons and holes (c 〇mbinati ο η efficiency) is very high, so it can avoid / erase incomplete problems and increase data retention Please refer to FIGS. 5 to 8 for a detailed description of the invention. FIGS. 5 to 8 are schematic diagrams of a method for manufacturing a dual-bit flash memory unit according to the present invention. As shown in FIG. 5, the manufacturing method of the dual-bit flash memory cell of the present invention is to first provide a semiconductor wafer 8 0 ′ including a P-type silicon base 8 2, which is then oxidized by high temperature. A silicon oxide layer of 50 to 150 angstroms (Angstrom, A) is formed on the surface of the substrate 82 and used as the gate oxide layer 84. Subsequently, a chemical vapor deposition (CVD) with Si iane (si H4), germane (GeH 4), and hydrogen gas is deposited at a deposition temperature between 450 C and 620 C. In the manufacturing process, a polycrystalline germanium second having a thickness of 5000-1000 Angstroms (a) is deposited on the surface of the gate oxide layer 84 (pioiSiiicOrl geTmanium, Si ^ xGex, X = 0.05 ~ 1 · 0) layer as the conductive layer 86. Then, a photoresist layer 88 is formed on the surface of the conductive layer 86, and a pattern of the insulating region 87 in the conductive layer 86 is defined in the photoresist layer 88, and then a implantation energy of about 20 to 80 KeV and ions is performed. An implantation process with an implantation dose of about 1 to 2 × 10 0 18 / cm to dope a high concentration of oxygen (〇xygen
507370 _案塗90124575 — W年分瓦-日 修正 _ 五、發明說明(6) dopant)或南派度氮掺質(nitrogen dopant )植入導電層8 6 中。隨後進行一溫度約為950°C〜1150t的高·溫回火製^程 (high temperature annealing),使植入導電層 86中的摻 質與導電層8 6之多晶鍺化石夕反應,形成一由二氧化石夕或氮 矽化合物構成之絕緣區域8 7,以將導電層8 6分隔成至少二 不相鄰接之導電區域。其中該高溫回火製程亦可取代以一 後續形成該記憶體之源極與汲極時的高溫驅入(dr丨v i ng i n )製程,以於形成該源極與汲極的同時來促使植入導電 層8 6中的摻質與導電層8 6之多晶鍺化矽反應,形成絕緣區 域87,進而降低半導體製程的熱預算。 接著如圖六所示,在導電層:8 6表面形成一厚度為5 0〜 1 5 0埃(A )之氧化矽層作為介電層9 〇。隨後於介電層9 〇表 面形成一圖案化之光阻層9 4,以定義出該快閃式記憶體之 浮動閘極(floating gate)95的圖案,且每一浮動閘極95 均包含有二不相鄰接之導電區域^然後利用光阻層9 4的 圖案當作硬罩幕(hard mask),蝕刻部份之介電層90以及 導電層8 6,以形成複數個浮動閘極9 5。隨後進行一砷 (arsenic)離子佈植製程,佈值離子濃度為2〜4, 1 〇 15/cm 2,能量為50Kev,以於矽基底82中形成複數個摻雜區,作 為記憶體之位元線9 6。然後將光阻層9 4完全去除。在本發 明之另一實施例中,介電層9 〇亦可以於沉積多晶鍺化矽導 電層8 6時,便直接形成於多·晶鍺化矽導電層8 6之上,然後 再進行離子佈植製程,以形成絕緣區域8 7。507370 _ Case Tu 90124575 — W years of watt-days Amendment _ V. Description of the invention (6) dopant or nitrogen dopant is implanted into the conductive layer 8 6. A high temperature annealing process with a temperature of about 950 ° C ~ 1150t is subsequently performed, so that the dopants implanted in the conductive layer 86 react with the polycrystalline germanium fossils in the conductive layer 86 to form An insulating region 87 composed of silicon dioxide or nitrogen silicon compound is used to separate the conductive layer 86 into at least two non-adjacent conductive regions. The high temperature tempering process can also replace a high temperature drive (dr 丨 vi ng in) process when the source and drain of the memory are subsequently formed, so as to form the source and drain at the same time to promote planting. The dopants introduced into the conductive layer 86 react with the polycrystalline silicon germanide of the conductive layer 86 to form an insulating region 87, thereby reducing the thermal budget of the semiconductor process. Next, as shown in FIG. 6, a silicon oxide layer having a thickness of 50 to 150 angstroms (A) is formed on the surface of the conductive layer 86 as the dielectric layer 90. A patterned photoresist layer 94 is then formed on the surface of the dielectric layer 90 to define the pattern of the floating gate 95 of the flash memory, and each floating gate 95 includes Two non-adjacent conductive areas ^ and then use the pattern of the photoresist layer 94 as a hard mask, and etch a part of the dielectric layer 90 and the conductive layer 86 to form a plurality of floating gate electrodes 9. 5. Subsequently, an arsenic ion implantation process is performed with a cloth ion concentration of 2 ~ 4, 1015 / cm 2 and an energy of 50 Kev to form a plurality of doped regions in the silicon substrate 82 as the memory bits Yuan line 9 6. The photoresist layer 94 is then completely removed. In another embodiment of the present invention, the dielectric layer 90 may be directly formed on the polycrystalline silicon germanium conductive layer 86 when the polycrystalline silicon germanium conductive layer 86 is deposited, and then performed. Ion implantation process to form the insulating region 8 7.
第10頁 507370 五、發明說明(7) 如圖七所示…接著進行一熱氧化法(t h e r m a 1 oxidation),以於位元線9 6表面上形成一場氧化層9 7,作 為各導電層8 6之間的隔離,而且該熱氧化製程之高溫也會 同時活化各位元線9 6中之摻質。在本發明之第三實施例 中,介電層9 0亦可以於多晶鍺化矽導電層8 6、絕緣區域8 7 以及浮動閘極9 5依序形成後,再藉由形成場氧化層9 7之該 熱氧化製程同時氧化多晶鍺化石夕層8 6表面而形成。此外, 該熱氧化製程亦會於各導電層8 6裸露之側壁表面形成一氧 化層9 9。 最後再於浮動閘極9 5表面沉積一多晶矽層或多晶矽化 金屬層(polysilicide),作為字元線98。其中,字元線98 係橫向排列於半導體晶片8 0表面,並與位元線9 6形成一幾 近垂直之上下重疊排列相對關係,如圖八所示。 請參考圖九,圖九為本發明之雙位元快閃記憶單元 1 0 0的剖面結構示意圖。雙位元快閃記憶單元1 0 0包含有一 堆疊閘極1 0 1、一源極1 0 3以及汲極1 0 5,同時源極1 0 3與汲 極1 0 5間之基底8 2表面有一通道(channel)107。堆疊閘極 101係由一閘極氧化層(gate oxide layer)84、一導電層 8 6、一介電層9 0以及一控制閘極9 1由下至上堆疊於通道 1 0 7表面。控制閘極9 1係為字元線9 8中與浮動閘極9 5上下 重疊之部分。導電層8 6中另包含一絕緣區域8 7,以將導電Page 10 507370 V. Description of the invention (7) As shown in Figure 7 ... Then a thermal oxidation method is performed to form a field oxide layer 9 7 on the surface of the bit line 9 6 as each conductive layer 8 The isolation between 6 and the high temperature of the thermal oxidation process will simultaneously activate the dopants in each element wire 9 6. In the third embodiment of the present invention, the dielectric layer 90 may also be sequentially formed after the polycrystalline silicon germanium conductive layer 86, the insulating region 87, and the floating gate 95 are formed, and then a field oxide layer is formed. The thermal oxidation process of 97 is formed by simultaneously oxidizing the surface of the polycrystalline germanium fossil layer 86. In addition, the thermal oxidation process also forms an oxide layer 99 on the exposed sidewall surfaces of the conductive layers 86. Finally, a polycrystalline silicon layer or polysilicide is deposited on the surface of the floating gate 95 as the word line 98. Among them, the word line 98 is horizontally arranged on the surface of the semiconductor wafer 80, and forms a nearly vertical upper and lower relative relationship with the bit line 96, as shown in FIG. Please refer to FIG. 9, which is a schematic cross-sectional structure diagram of a dual-bit flash memory cell 100 of the present invention. The double-bit flash memory cell 1 0 0 includes a stacked gate 1 0 1, a source 1 0 3 and a drain 1 0 5. At the same time, the substrate 8 2 between the source 1 0 3 and the drain 1 0 5 There is a channel 107. The stacked gate 101 is composed of a gate oxide layer 84, a conductive layer 86, a dielectric layer 90, and a control gate 91, which are stacked on the surface of the channel 107 from bottom to top. The control gate 9 1 is a portion of the character line 98 that overlaps with the floating gate 95. The conductive layer 8 6 further includes an insulating region 8 7 to conduct electricity.
第11頁 _案號 五、發明說明(8) 90124575Page 11 _ Case number V. Description of the invention (8) 90124575
層 8 6分隔成兩不相電連拯 , 構。而各導電層8 6裸露之彳,導電區域H,形成雙位元結 化層99,以避免各導電;^壁表面亦可選擇性地形成一氧 各導電區域g係為一^;386直接與字元線98相接觸。其中 layer)’用來接收並伴留^電子層(charge traPPing 形成一位元(bit)。呆邊射入該導電區域之電子,以分別 s «r Ϊ f ί ί Γ ί雙位.凡快閃記憶單元1 0 0,其中導電層 係由一士、干、,且成為Si卜/〜X = 〇· 05〜1. 0之多晶鍺化 组t。二緣區· 87則係利用-佈植劑量約為1〜 f1〇二二且,植,量約為,2〇〜8〇㈣之氧離子佈值製程 植入尚派度虱払貝於該多晶矽鍺化層中,並藉由一溫度約 為9 5 0C〜1150°C的高溫回火製程(high temperature ^nneal ing)反應而形成。此外,絕緣區域87亦可利用一高 濃度氮摻質(nitrogen dopant)植入該多晶鍺化矽層中, 並藉由一熱製程反應而成。 由於本發明提供之雙位元快閃記憶體之結構,是利用一導 電層作為滯留電子層並於該導電層中形成一絕緣區域,以 將其刀隔成兩不相電連接之捕捉電子區域,所以兩區域可 分別進行儲存與讀取的動作,而形成一雙位元結構。 相較於習知製作之氮化物唯讀記憶體,本發明提供了 一種雙位元快閃記憶體結構·,在不需要縮小製程線寬的條 件下,即可相對增加記憶體元件之積集度,不但可避免習The layers 86 and 6 are separated into two electrically connected structures. Each conductive layer 86 is exposed, and the conductive region H forms a two-bit junction layer 99 to avoid each conductivity. ^ A surface of the wall can also selectively form an oxygen, and each conductive region g is ^; 386 directly The character lines 98 are in contact. The layer) 'is used to receive and accompany the ^ electronic layer (charge traPPing to form a bit. The electrons that are injected into the conductive area are s «r Ϊ f ί Γ Γ double position. Fan Kuai Flash memory cell 1 0 0, in which the conductive layer is composed of a single layer, a dry, and a polycrystalline germanium group t of Si Bu / ~ X = 0.05 ~ 1.0. The two-edge region · 87 is used- The implantation dose is about 1 ~ f1202, and the planting amount is about 20 ~ 80%. The oxygen ion cloth value process is implanted in the polycrystalline silicon germanium layer, and by A high temperature ^ nneal ing reaction is performed at a temperature of about 950 ° C ~ 1150 ° C. In addition, the insulating region 87 can also be implanted into the polycrystal with a high concentration nitrogen dopant. The silicon germanium layer is formed by a thermal process. Because of the structure of the dual-bit flash memory provided by the present invention, a conductive layer is used as a retained electron layer and an insulating region is formed in the conductive layer. To separate its knife into two capture electronic areas that are not electrically connected, so the two areas can be stored and read separately. A double-bit structure is formed. Compared with the conventionally produced nitride read-only memory, the present invention provides a double-bit flash memory structure, which can be used without reducing the process line width. Relatively increasing the accumulation of memory components can not only avoid learning
第12頁 507370 五、發明說明(9) --—---- 知利用光學微影製程以及光阻層定義浮動閘極位置容 易發生誤對準(misalignment)而導致製程良率降低的問 題。另一方面,由多晶鍺化矽構成之導電層可以增加活性 摻質濃度(active dopant concentration),進而曰降低因 多晶空乏效應(poly depletion eff ec t)所導致閘極傳遞 訊號的延遲,同時電子與電洞於該多晶鍺化石夕導電層内的 結合效率(combination efficiency)很高,因此可以避免 抹除不完全的問題以及增加資料保存(data retention)的 可靠度(reliability)。 9 以上所述僅為本發明之較佳實施例,凡依本發明申請 專利範圍所做之均等變化與修飾,皆應屬本發明專利之涵 蓋範圍。Page 12 507370 V. Description of the invention (9) ------- Know the problem of using the optical lithography process and the photoresist layer to define the position of the floating gate, which is prone to misalignment and reduce the yield of the process. On the other hand, a conductive layer composed of polycrystalline silicon germanium can increase the active dopant concentration, thereby reducing the delay of the gate transmission signal caused by poly depletion eff ec t, At the same time, the combination efficiency of electrons and holes in the conductive layer of the polycrystalline germanium fossil is very high, so it can avoid the problem of incomplete erasure and increase the reliability of data retention. 9 The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.
第13頁 507370 _案號90124575_W年彳月(曰 修正_ 圖式簡單說明 _ 圖示之簡單說明 圖一至圖四為習知製作氮化物唯讀記憶體的方法示意 圖。 圖五至圖八為本發明製作雙位元快閃記憶單元的方法 示意圖。 圖九為本發明之雙位元快閃記憶單元的剖面結構示意 圖。 圖示之符號說明 10 半 導 體 晶 片 1:2 矽 基 底 14 底 氧 化 層 16 氮 化 矽 層 18 上 氧 化 層 20 ΟΝΟ層 22 遮 罩 24 位 元 線 26 場 氧 化 層 28 字 元 線 80 半 導 體 晶 片 82 基 底 84 閘 極 氧 化 層 86 導 電 層 /導電區域 87 絕 緣 區 域 88、94 光 阻 層 90 介 電 層 91 控 制 閘 極 95 浮 動 閘 極 96 位 元 線 97 場 氧 化 層 98 字 元 線 100 雙 位 元 快 閃記憶單元 101 堆 疊 閘 極 103 源 極 105 汲 極Page 13 507370 _Case No. 90124575_Year Month (Revised _ Simple Description _ Simple Description of the Figures) Figures 1-4 are schematic diagrams of the conventional method for making nitride read-only memory. Figures 5 to 8 Schematic diagram of the method for making a dual-bit flash memory cell according to the invention. Figure 9 is a schematic cross-sectional structure of the dual-bit flash memory cell according to the present invention. Symbols shown in the figure 10 Semiconductor wafer 1: 2 Silicon substrate 14 Bottom oxide layer 16 Nitrogen Silicon layer 18 Upper oxide layer 20 ONO layer 22 Mask 24 bit line 26 Field oxide layer 28 Word line 80 Semiconductor wafer 82 Substrate 84 Gate oxide layer 86 Conductive layer / Conductive region 87 Insulating region 88, 94 Photoresist layer 90 Dielectric layer 91 Control gate 95 Floating gate 96-bit line 97 Field oxide layer 98 Word line 100 Two-bit flash memory cell 101 Stacked gate 103 Source 105 Drain
第14頁 507370 案號90124575 Μ年气月(曰 修正 圖式簡單說明 107通道 ΙϋΙΙϋΙ 第15頁Page 14 507370 Case No. 90124575 M year gas month (revised simple illustration of the diagram 107 channels ΙϋΙΙϋΙ page 15
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