TW507370B - A twin bit cell flash memory device and its fabricating method - Google Patents

Abstract

The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1-x Gex, x=0.05 to 1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.

Description

507370 V. Description of the invention (1) Field of the invention The present invention provides a double bit (twin bi t cel 1) flash memory dev ices structure and a manufacturing method thereof. Background Description A read only memory (ROM) device is a semiconductor device used to store data. It is composed of multiple memory cells (memory c 11): it is now widely used in computer data storage and memory. Generally, according to the data storage method, the read-only memory can be divided into a mask-type read-only memory (M ask R 0 Μ), a programmable ROM (programmable ROM, PROM), erasable and programmable There are several types of read-only memory (Erasable programmable ROM (EPROM)), electrically erasable and programmable read-only memory (EPRROM). Unlike other read-only memories that use polycrystalline stone or metal floating gates to store charge, nitride read-only memory (nitrideread ο η 1 y memory (NROM)) is mainly characterized by the use of silicon nitride insulating media The electrical layer acts as a charge trapping medium. Due to the high density of the nitride stone layer, the hot electrons entering the silicon nitride layer through MOS transistor tunneling can be trapped therein, thereby forming a non-uniform concentration distribution. To speed up reading data

DU / J / U 5. Description of the invention (2) " — e-and avoid leakage current. Green # 二 refers to FIGS. 1 to 4, which are schematic diagrams of a conventional method for manufacturing a nitride-only I 2 ϊ Γ body. As shown in Fig. 1, a conventional method for making a nitride-based material is to first provide a semiconductor wafer 10 including a P-type silicon substrate (si 1 icon a Se. 2), and then use a temperature range 7 5 (TC ~ ^ 00 ° C oxidation process to form a 50 ~ 150 angstrom (angstrom), A), the surface of the silicon substrate 12 is used as the bottom oxide layer 14. Then low pressure is performed ^ Low pressure vapor deposition (LPCVD) process. A nitride nitride layer 16 with a thickness of 20 ~ 150 angstroms (A) is deposited on the surface of the bottom oxide layer 14 as a charge trapping 1 aye Γ. In the high temperature environment of 950 ° C, Yuan Hou then performed a tempering process 300 to repair the structure of the nitrided layer 16 and passed water vapor to perform wet oxygen. A layer of silicon oxide (si 1 ic ο η ο X y ~ nitride) with a thickness of 50 to 150 angstroms (A) is formed on the surface of layer 16 as an upper oxide layer 18 ° where 'formed on a silicon substrate 12 The bottom oxide layer 14 on the surface, the silicon nitride layer 16 and the upper oxide layer 18 are collectively referred to as the 0N0 layer 20. Then, as shown in FIG. A photoresist layer (not shown) is formed on the surface, and a yellow light process and an etching process are performed. A pattern is formed in the photoresist layer to define the position of the bit line (b 丨 t 1 ine). Next, the photoresist is used. The pattern of the layer is used as a mask 22, and a dry etching process is performed to remove the oxide layer 18 and silicon nitride layer 16 not covered by the mask 2 2 and the etching layer 14 to a predetermined oxide layer Thickness, followed by an _ (arsenic)

Page 6 V. Description of the invention (3) Ion implantation process, the cloth ion concentration is 2 ~ 4, 10 15 / cm2, and the energy is 50Kev'_ to form a plurality of doped regions in the Shixi substrate 12, As a memory, the bit line 2 4 ′ is also called a buried type pole (dagger u Γ 丨 eddrai η). Then the mask 2 2 is completely removed. As shown in Figure 2, a thermal oxidation method is used to form a field oxide layer 2 6 on the surface above line 2 4 as the silicon nitride layer line = separation. At the same time, the thermal oxidation process is used. The temperature activates the change of quality of each element. Finally, as shown in FIG. 4, a polysilicon layer or polysilicon layer (polys i 1 pesticide) is deposited on the surface of the 0N0 layer 20 as a word line due to the nitride read-only memory. The charge layer is used as a charge storage medium, so it is being written; — = hot electrons will distribute in the shape of the stagnation electron layer depending on the injected energy, and valleys are susceptible to secondary electron incidence.

= dary injecti〇n) to form a tail-shaped electron distribution ⑽ 1 1 and the wide charge distribution (wider charge distribution) When the erase process is performed after the hole is injected into the retained electron layer: i ,, ι lines Can not completely overlap with the distribution curve of electrons, so it will cause 1 ^: complete recombine with electrons, which will cause the problem of erasing not: King or the long erasing time required. Summary of the invention

Page 7 507370 V. Description of the invention (4) The main purpose of the present invention is to provide a two-bit flash memory ~ memory element structure to increase the memory cell density (mem 〇ryce 1 1 density) and solve the problem. Know the problem of incomplete erasure of nitride read-only memory. Another object of the present invention is to provide a method for manufacturing a flash memory device, so as to produce a high-integration dual-bit flash memory device, while avoiding the problem of incomplete erasure and increasing data storage ( data retention). In the preferred embodiment of the present invention, a gate oxide layer is formed on the surface of a silicon substrate, and then a polysilicon germanium (Si i_xGe x, x = 0.0 5 to 1.0) layers. Subsequently, an ion distribution process is performed to form at least one insulating region in the polycrystalline silicon germanium layer to separate the polycrystalline silicon germanium layer into two discontinuous conductive regions to form a two-bit structure. Then, a dielectric layer is formed on the surface of the polycrystalline silicon germanide layer, and a yellow light and etching process is performed to etch a part of the dielectric layer and the polycrystalline silicon fossil layer to form the floating gate. Finally, a control gate is formed on the floating gate. Since the present invention uses a conductive layer as the retained electron layer and uses an oxidized region to separate it into two capture electron regions 5 that are not electrically connected, the two regions can be stored and read separately to form a double bit. Structure, because the two electron-trapping regions are made of a polycrystalline silicon germanium conductive layer

507370 V. Composition of invention (5), so the combination efficiency of electrons and holes (c 〇mbinati ο η efficiency) is very high, so it can avoid / erase incomplete problems and increase data retention Please refer to FIGS. 5 to 8 for a detailed description of the invention. FIGS. 5 to 8 are schematic diagrams of a method for manufacturing a dual-bit flash memory unit according to the present invention. As shown in FIG. 5, the manufacturing method of the dual-bit flash memory cell of the present invention is to first provide a semiconductor wafer 8 0 ′ including a P-type silicon base 8 2, which is then oxidized by high temperature. A silicon oxide layer of 50 to 150 angstroms (Angstrom, A) is formed on the surface of the substrate 82 and used as the gate oxide layer 84. Subsequently, a chemical vapor deposition (CVD) with Si iane (si H4), germane (GeH 4), and hydrogen gas is deposited at a deposition temperature between 450 C and 620 C. In the manufacturing process, a polycrystalline germanium second having a thickness of 5000-1000 Angstroms (a) is deposited on the surface of the gate oxide layer 84 (pioiSiiicOrl geTmanium, Si ^ xGex, X = 0.05 ~ 1 · 0) layer as the conductive layer 86. Then, a photoresist layer 88 is formed on the surface of the conductive layer 86, and a pattern of the insulating region 87 in the conductive layer 86 is defined in the photoresist layer 88, and then a implantation energy of about 20 to 80 KeV and ions is performed. An implantation process with an implantation dose of about 1 to 2 × 10 0 18 / cm to dope a high concentration of oxygen (〇xygen

507370 _ Case Tu 90124575 — W years of watt-days Amendment _ V. Description of the invention (6) dopant or nitrogen dopant is implanted into the conductive layer 8 6. A high temperature annealing process with a temperature of about 950 ° C ~ 1150t is subsequently performed, so that the dopants implanted in the conductive layer 86 react with the polycrystalline germanium fossils in the conductive layer 86 to form An insulating region 87 composed of silicon dioxide or nitrogen silicon compound is used to separate the conductive layer 86 into at least two non-adjacent conductive regions. The high temperature tempering process can also replace a high temperature drive (dr 丨 vi ng in) process when the source and drain of the memory are subsequently formed, so as to form the source and drain at the same time to promote planting. The dopants introduced into the conductive layer 86 react with the polycrystalline silicon germanide of the conductive layer 86 to form an insulating region 87, thereby reducing the thermal budget of the semiconductor process. Next, as shown in FIG. 6, a silicon oxide layer having a thickness of 50 to 150 angstroms (A) is formed on the surface of the conductive layer 86 as the dielectric layer 90. A patterned photoresist layer 94 is then formed on the surface of the dielectric layer 90 to define the pattern of the floating gate 95 of the flash memory, and each floating gate 95 includes Two non-adjacent conductive areas ^ and then use the pattern of the photoresist layer 94 as a hard mask, and etch a part of the dielectric layer 90 and the conductive layer 86 to form a plurality of floating gate electrodes 9. 5. Subsequently, an arsenic ion implantation process is performed with a cloth ion concentration of 2 ~ 4, 1015 / cm 2 and an energy of 50 Kev to form a plurality of doped regions in the silicon substrate 82 as the memory bits Yuan line 9 6. The photoresist layer 94 is then completely removed. In another embodiment of the present invention, the dielectric layer 90 may be directly formed on the polycrystalline silicon germanium conductive layer 86 when the polycrystalline silicon germanium conductive layer 86 is deposited, and then performed. Ion implantation process to form the insulating region 8 7.

Page 10 507370 V. Description of the invention (7) As shown in Figure 7 ... Then a thermal oxidation method is performed to form a field oxide layer 9 7 on the surface of the bit line 9 6 as each conductive layer 8 The isolation between 6 and the high temperature of the thermal oxidation process will simultaneously activate the dopants in each element wire 9 6. In the third embodiment of the present invention, the dielectric layer 90 may also be sequentially formed after the polycrystalline silicon germanium conductive layer 86, the insulating region 87, and the floating gate 95 are formed, and then a field oxide layer is formed. The thermal oxidation process of 97 is formed by simultaneously oxidizing the surface of the polycrystalline germanium fossil layer 86. In addition, the thermal oxidation process also forms an oxide layer 99 on the exposed sidewall surfaces of the conductive layers 86. Finally, a polycrystalline silicon layer or polysilicide is deposited on the surface of the floating gate 95 as the word line 98. Among them, the word line 98 is horizontally arranged on the surface of the semiconductor wafer 80, and forms a nearly vertical upper and lower relative relationship with the bit line 96, as shown in FIG. Please refer to FIG. 9, which is a schematic cross-sectional structure diagram of a dual-bit flash memory cell 100 of the present invention. The double-bit flash memory cell 1 0 0 includes a stacked gate 1 0 1, a source 1 0 3 and a drain 1 0 5. At the same time, the substrate 8 2 between the source 1 0 3 and the drain 1 0 5 There is a channel 107. The stacked gate 101 is composed of a gate oxide layer 84, a conductive layer 86, a dielectric layer 90, and a control gate 91, which are stacked on the surface of the channel 107 from bottom to top. The control gate 9 1 is a portion of the character line 98 that overlaps with the floating gate 95. The conductive layer 8 6 further includes an insulating region 8 7 to conduct electricity.

Page 11 _ Case number V. Description of the invention (8) 90124575

The layers 86 and 6 are separated into two electrically connected structures. Each conductive layer 86 is exposed, and the conductive region H forms a two-bit junction layer 99 to avoid each conductivity. ^ A surface of the wall can also selectively form an oxygen, and each conductive region g is ^; 386 directly The character lines 98 are in contact. The layer) 'is used to receive and accompany the ^ electronic layer (charge traPPing to form a bit. The electrons that are injected into the conductive area are s «r Ϊ f ί Γ Γ double position. Fan Kuai Flash memory cell 1 0 0, in which the conductive layer is composed of a single layer, a dry, and a polycrystalline germanium group t of Si Bu / ~ X = 0.05 ~ 1.0. The two-edge region · 87 is used- The implantation dose is about 1 ~ f1202, and the planting amount is about 20 ~ 80%. The oxygen ion cloth value process is implanted in the polycrystalline silicon germanium layer, and by A high temperature ^ nneal ing reaction is performed at a temperature of about 950 ° C ~ 1150 ° C. In addition, the insulating region 87 can also be implanted into the polycrystal with a high concentration nitrogen dopant. The silicon germanium layer is formed by a thermal process. Because of the structure of the dual-bit flash memory provided by the present invention, a conductive layer is used as a retained electron layer and an insulating region is formed in the conductive layer. To separate its knife into two capture electronic areas that are not electrically connected, so the two areas can be stored and read separately. A double-bit structure is formed. Compared with the conventionally produced nitride read-only memory, the present invention provides a double-bit flash memory structure, which can be used without reducing the process line width. Relatively increasing the accumulation of memory components can not only avoid learning

Page 12 507370 V. Description of the invention (9) ------- Know the problem of using the optical lithography process and the photoresist layer to define the position of the floating gate, which is prone to misalignment and reduce the yield of the process. On the other hand, a conductive layer composed of polycrystalline silicon germanium can increase the active dopant concentration, thereby reducing the delay of the gate transmission signal caused by poly depletion eff ec t, At the same time, the combination efficiency of electrons and holes in the conductive layer of the polycrystalline germanium fossil is very high, so it can avoid the problem of incomplete erasure and increase the reliability of data retention. 9 The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 13 507370 _Case No. 90124575_Year Month (Revised _ Simple Description _ Simple Description of the Figures) Figures 1-4 are schematic diagrams of the conventional method for making nitride read-only memory. Figures 5 to 8 Schematic diagram of the method for making a dual-bit flash memory cell according to the invention. Figure 9 is a schematic cross-sectional structure of the dual-bit flash memory cell according to the present invention. Symbols shown in the figure 10 Semiconductor wafer 1: 2 Silicon substrate 14 Bottom oxide layer 16 Nitrogen Silicon layer 18 Upper oxide layer 20 ONO layer 22 Mask 24 bit line 26 Field oxide layer 28 Word line 80 Semiconductor wafer 82 Substrate 84 Gate oxide layer 86 Conductive layer / Conductive region 87 Insulating region 88, 94 Photoresist layer 90 Dielectric layer 91 Control gate 95 Floating gate 96-bit line 97 Field oxide layer 98 Word line 100 Two-bit flash memory cell 101 Stacked gate 103 Source 105 Drain

Page 14 507370 Case No. 90124575 M year gas month (revised simple illustration of the diagram 107 channels ΙϋΙΙϋΙ page 15

Claims (1)

507370 VI. Scope of patent application 1. A method for making twin bit ce 11 flash memory (f 1 ashmemorydevices), the method includes the following steps: providing a silicon substrate; forming a silicon substrate on the surface of the silicon substrate A gate oxide layer; forming a polysi 1 icon germanium layer on the surface of the gate oxide layer; and performing an ion layout process to form at least one insulating region in the polycrystalline silicon germanium layer The polycrystalline silicon germanium layer is separated into two discontinuous conductive regions to form a two-bit structure; a dielectric layer is formed on the surface of the polycrystalline silicon germanium layer; a pattern is formed on the surface of the dielectric layer A floating gate; and a control gate is formed on the floating gate. 2. The method according to item 1 of the scope of patent application, wherein the polycrystalline silicon germanium layer is formed by using a silane (SiH 4), germane (GeH4), and hydrogen gas at a deposition temperature. It is formed by chemical vapor deposition (CVD) between 450 ° C and 62 ° C. 3. If the method in the first item of the patent application is applied, it also includes a temperature of 950 ° C ~ 1150 ° C. High temperature annealing process to diffuse the ions implanted by the ion distribution process to form the insulation region. Page 16 507370 6. Scope of patent application 4. For the method of the first scope of patent application, the chemical composition of the polycrystalline silicon germanium layer is S i 1 _XG ex, x 2 0 · 0 5 ~ 1 · 0 〇 5.-The method according to item 1 of the patent application scope, wherein after forming each of the floating gates, it further includes an ion distribution process and a thermal oxidation process to form the bit line of the dual-bit flash memory. An oxide layer is formed on the surface of the bit line as an isolation between the floating gates. 6. If the method of claim 5 is applied, the thermal oxidation process will also form an oxide layer on the exposed sidewall surface of each of the conductive areas. 7. A method of making a twinbitce 1 1 flash memory device, the method comprising the following steps: providing a broken substrate; forming a gate oxide layer on the surface of the silicon substrate; A polycrystalline germanium fossil (ρ ο 1 ysi 1 ic ο η germanium) layer is formed on the surface of the gate oxide layer; a dielectric layer is formed on the surface of the polycrystalline silicon germanium layer; an ion distribution process is performed on the polycrystalline silicon germanium layer; Forming at least one insulating region in the polycrystalline silicon germanium layer to separate the polycrystalline silicon germanium layer into two discontinuous conductive regions to form a double-bit structure; forming a patterned float on the surface of the dielectric layer Gate (f 1 〇ating Page 17 507370 VI. Patent application scope gate); and forming a control gate electrode on the floating gate electrode 8. The method according to item 7 of the patent application scope, wherein the polycrystalline silicon germanium layer also has the composition S i ^ XG ex, X = 0 · 0 5 to 1 · 0. 9. The method according to item 7 of the patent application, wherein the polycrystalline silicon germanium layer is formed by using a silicon silane (SiH 4), germane (GeH 4), and argon (hydrogen), and It is formed by chemical vapor deposition (CVD) with a deposition temperature between 450 ° C and 620 ° C. 10. The method according to item 7 of the scope of patent application, further comprising a high temperature annealing process (95 ~ TC ~ 115 00 ° C) to diffuse the ions implanted in the ionic distribution process to form The insulation region. 1 1. The method according to item 7 of the patent application, wherein after forming each floating gate, it further comprises an ion distribution process and a thermal oxidation process to form the dual-bit flash memory. The bit line, and an oxide layer is formed on the surface of the bit line as an isolation between the floating gates. 1 2. If the method of item 11 of the patent scope is applied, the thermal oxidation process is also performed at each An oxide layer is formed on the exposed sidewall surface of the conductive region. Page 18 507370 VI. Application scope of patent 1 3 — A method for making twinbitce 1 1 flash memory (f 1 a sh m em ory devices), the method includes the following steps: providing a stone A substrate; a gate oxide layer is formed on the surface of the broken substrate; a polycrystalline germanium fossil (P0lysiliCQn germanium) layer is formed on the surface of the gate oxide layer; an ion distribution process is performed on the polycrystalline germanium Forming at least one insulating region in the silicon layer to separate the polycrystalline silicon germanium layer into two discontinuous conductive regions to form a two-bit structure; forming a patterned floating gate on the polycrystalline silicon germanium layer (Floating ga te); performing an ionic layout process to form a plurality of doping regions' in the silicon substrate as bit lines of the flash memory; performing a thermal oxidation process on the bit lines A field oxide layer is formed on the surface as an isolation between the floating gates; and a control gate is formed on the floating gates. 1 4. The method according to item 丨 3 of the scope of patent application, wherein the chemical composition of the polycrystalline silicon germanium layer is Si hGex, X = 0.05 to 1.0. 15 · The method according to item 3 of the scope of patent application, wherein the polycrystalline silicon germanide layer is formed by using silicon methane (Si i an e, Si Η 4), germane (Ge ， 4) And hydrogen (hydroge η) and the deposition temperature is between 4 5 0 ° C ~ 6 2 (between TC Page 19 Chemical vapor deposition (chemi VII. Vapor deposition, CVD) ^ f ^ 16. If the method of patent application scope ilSOt: high temperature tempering process item method, it also includes a 95 ° C ~ to diffuse the ion cloth value system : high temPerature annealing), the ion implanted in the hall to form the insulation area. 17 · If the scope of patent application is the method of exposing item 13 on each of the conductive areas, an oxide layer is formed on the surface of the sidewall of the thermal oxidation process. Also 1 ·· A flash memory device (twin bi t cel 1), which includes: a semiconductor substrate; a source and a drain Is located in a predetermined area of the semiconductor substrate, and the drain is separated from the source by a predetermined distance; a channel is provided on the surface of the semiconductor substrate between the source and the non-electrode; a first interface An electric layer covering the surface of the channel; a polycrystalline germanium fossil layer is formed and covering the surface of the first dielectric layer; and the polycrystalline silicon germanium layer further includes an insulating region to form the polycrystalline germanium The siliconized layer is separated into two electrically conductive regions that are not electrically connected to form the double bit; a second dielectric layer is formed to cover the surface of the polycrystalline germanium fossil layer; and a gate is formed and covered on the The surface of the second dielectric layer; Page 20 507370 6. Scope of patent application Each of the conductive areas is a trapping electron layer (charge; trapping layer), which is used to receive and retain the electrons that are injected into the conductive area to form a bit (b i t). 19. According to the flash memory billion-item body of claim 18, wherein the semiconductor substrate is a P-type substrate, and the source and drain systems are an N-type doped region. 20. The flash memory of item 18 in the scope of patent application, wherein the semiconductor substrate is an N-type substrate, and the source and drain electrodes are a P-type doped region. 2 1. The flash memory of item 18 in the scope of the patent application, wherein the chemical composition of the polycrystalline germanium fossil layer is S i Bu / e x, X = 0.5 5 to 1.0. 2 2. If the flash memory of item 18 of the patent application scope, the insulating region is implanted into the polycrystalline germanium fossil layer with a high concentration of oxygen dopant (ο X ygend 〇pant), and by The reaction of a thermal process. 2 3. The flash memory according to item 22 of the patent application scope, wherein the high-concentration oxygen dopant is formed by an oxygen ion cloth value process, and the implantation dose is about 1 ~ 2 X1 0 18 / cm 2, the planting energy is about 20 ~ 80 K e V. 2 4. The flash memory according to item 22 of the patent application scope, wherein the thermal process Page 21 507370 6. The scope of patent application is a high-temperature tempering process (temperature 950 ~ 0 1 5 0 ° C) 0 2 5. If the scope of patent application is 18 For flash memory, the insulating region is formed by implanting a high-concentration nitrogen dopant (nitrogendpan) into the polycrystalline germanium fossil layer and reacting through a thermal process. 26. The flash memory of item 18 in the scope of patent application, wherein an exposed oxide layer is formed on the exposed sidewall surface of each of the conductive regions. Page 22