TW507205B - Wafer level memory burn-in testing circuit and method - Google Patents

Abstract

A circuit that only uses four leads to proceed wafer level memory burn-in testing of the memory chip and also can shorten the burn-in time is provided. Because the plural horizontal bit-lines of the memory chip is switched to high electric potential state in the burn-in mode, the plural vertical bit-lines are tested by burn in each whole bit-line. It is different from the conventional way that tests the memory chip cell by cell. The test time according to the present invention therefore greatly increases. Besides, the wafer level testing is also different from the traditional way, testing after packaging.

Description

507205 Case number 89116305 V. Description of the invention (1) Field of invention: t The invention relates to a burn-in circuit of a memory circuit, especially a wafer-level burn-in test that can be performed with only four pins. Circuits that reduce burn-in time. Background of the Invention: In recent years, cameras and mobile large-capacity companies have made it easier and more rigorous to access the memory by performing memory pressure tests by burning out the memory. Or laptop personal computers, several personal electronic assistant secretaries, memory requirements due to sound and video requirements, coupled with the rapid development of the Internet, personal or network and email exchange of sound and video files is more convenient and The ground also promotes the increase in memory capacity requirements. In addition, from frequent, the reliability and stability of the memory is relatively better than the beginning. To determine the reliability of the memory, the first thing is to test the machine. (B Urntest), in order to be able to judge the durability and pressure resistance and its service life in the shortest time. In general, the burn-in test will use a higher electricity than normal use is about 40% or 50% higher. For example, the normal operating voltage is 5 volts. When testing, it is generally 7 to 7. 5 The traditional burn-in test method is used to filter defective products. Usually, the memory chip is packaged and then tested, and a considerable number of packaged wafers are loaded into the burn-in test machine at the same time to reduce the test time. The memory capacity is large or

Page 4 507205 Case No. 89116305 V. Description of the invention (2) It is necessary to perform one memory unit at a time, even if the test time of each memory unit is extremely short, the time taken to test a complete chip is 64 million bits (1 6x 4M bits; 16 I / 0 ports, 2K X and Y addresses each (2Kx 2 kbit = 4 million bits), for example, a burn-in test performed on one memory cell is about It takes about 24 hours to end, in other words, each bit takes 8640 0 seconds / 4 megabits = 2 1 · 6 ms / bits. For the above conventional method, for a single packaged chip, it is difficult to shorten the test time, especially if the memory cell is larger, the situation will worsen. In view of the above problems, the present invention will provide a method to shorten the test time. Method, and it belongs to a method called wafer stage test method. More importantly, the circuit is simple. It only needs to use the circuit of the present invention plus four pins. Purpose and summary of the invention: One object of the present invention is to provide It is different from the traditional burn-in test (bur ni η) test after packaging and testing. Another object of the present invention is to provide a method for testing a whole address line at a time to greatly shorten the test time (the traditional method is to test each memory cell separately). The present invention discloses a wafer stage burn-in test memory cell chip that can be performed with only four pin machines (VCC, VSS, B / I, CLOCK), and

Page 5 丨 'Money- :, _Case No. 89116305_ 丨 Yearly Milk V: Day 1 Amendment. _ 5. Description of the Invention (3) —....... .. '! The chip burn-in test circuit that can reduce the burn-in time includes at least: B / I mode control circuit for switching a plurality of horizontal address lines into a pre-write mode or a horizontal address line decoder control mode; status provided A circuit for providing a first binary bit data to write to a data input terminal of a memory chip, and providing a second binary bit, the second binary bit is used as an address counter Circuit signal input, in conjunction with the address counter circuit. Multiple signal outputs generated by the circuit can provide sufficient control signals for the decoders of the plurality of vertical address lines. Each of the vertical address lines can therefore be unique, and It is turned on sequentially; the chip burn-in test circuit includes a burn-in and data input switching circuit for switching one of the normal data and the burn-in and write data to the chip data input terminal. The B / I mode control circuit mentioned above has a B / I control terminal. When the B / I control terminal is at a high potential, a plurality of horizontal address lines are raised to a high potential to enter the burn-in test stage. In addition, when the B / I control terminal is at a high potential, the burn-in and data input switching circuit is also turned into a burn-in test pattern input state so that the above-mentioned first binary bit data can be written into the memory cell chip. Lean input. Detailed description of the invention ... As stated in the background of the invention, the traditional burn-in test requires that the horizontal address line and the vertical address line (two intersecting address lines control one bit memory cell) take turns and test Therefore, even if the test of each bit unit is extremely short, it is quite feasible for high-capacity memory chips.

Page 6 Case No. 89116305 Fifth, send a ~ 4 ^ O tr concept. The only thing that can reduce the overall time cost is that the terminal phase ^^ ϊ ΐ i is small, and now, because of the large capacity of the machine: burning the test machine, the cost increases rapidly. Keep, because the circuit complex: the method provided by the invention can be greatly :; the original basis "is because of the problem of the crystal 2 method, the control circuit is burned, so only 方向 ΐ direction address η 疋 Λ) in order For testing, you can use one bit f address line: large; this can significantly reduce the time cost, especially for the unit of ^ line: 隹 Λ is more significant. In addition, because the test machine is used: memory cell capacity and% surface (Clock; or timing control pin only available, (VCC) and ground (vss), / this sequence) display = ^ (B / I Control), electricity to achieve the purpose of reducing costs. This is the display of the interpersonal test machine control circuit. For the test method of the present invention, please refer to the circuit in Figure 1. The figure is A, and at least the horizontal square 3 of the block diagram of the At force moon of the white person is included. Memory cell chip 100, chip orientation u 1 address line decoder (X-Add de Coder) U0, chip vertical squarer K-line decoder (Y-Add decoder) 120, vertical address line calculation environment : $ 1, 50, state generator circuit 1 40, clock (CLOCK) 1 70, pre-amp input switching circuit 1 6 〇 and pre-burn control circuit 1 3 〇. ^ Pre-burn control circuit 1 3 〇 It has a B / I terminal to receive whether the burn-in starts. The heart number of B ^ 'When the B / I terminal receives a signal from low potential to high potential, ^ 1 0 0 will start to enter the burn-in mode. When the burn-in control terminal The control right of all horizontal direction address lines of B / I in high power is decoded by horizontal direction address lines 507205 _m 89116305 __ Day 丨 Positive, V. Description of the invention (5) ~ ^^ ~ A The control circuit 130 controls all horizontal address lines to be at a potential. In addition, the burn-in and data input switching circuit} 6 〇 The data input is also transferred from the normal data input to the state generator circuit 丨 40 to provide a burn in pattern. The lowest bit 位 output by the state generator circuit 14 provides the pattern of the memory chip programming at the same time The highest bit ^ ^ of its output also provides the vertical address line counter circuit. The lowest bit signal is used as the input signal of the vertical address line counter circuit 15. The vertical square ^ address line counter circuit 15 The generated signal is combined with the above-mentioned state to generate a state. The highest bit signal supplied by the channel 140 generates a vertical address line solution j to be a 2 0 control signal to perform an address line and an address line. Shows the burn-in and data input switching circuit designed according to the present invention ^ A circuit diagram that includes general data or burn-in test signals written into the memory cell 'includes two transmission gates 1610, 1620, And an inverter 163. The β / 1 terminal is connected to the gate of the NMOS transistor of the transfer gate 1610 via the inverter iH〇, and the B / I terminal is directly connected to the NMOS of the gate i 6 2 0. Gate of crystal 1 6 2 0 are connected to each other in series. The transfer gate 1 6 1 is deficient, and the & j 1 D 1 & input ^ is the general poor material. The port 1 of the transfer gate 1 62 0 is preset | 1 fn η Xi recognizes, α ~ 的 测 Xian ##. The output end of the transmission gate lbl0 and the transmission gate 1620 0. The data input end of the circle 曰 0 0. Therefore,% 莜 士 迓Connected to low potential. Female g B / 1¾ input system has one of the south potential or input position. It allows one of the two relays i6i0 and 162o to output. For example, when the B / I terminal input is high, one input At the data input terminal of chip m, inverse 2: 3: ί = lose_ < then /, there is a general lean signal

507205 ★, 91 · d -M 8911 ^ 6305_ Mou Yueri • Repair 丨 Next · V. Description of the invention (6) .... ‘1 ---- ~~ Probably entered on the data input terminal of chip 1 0 0. FIG. 3 shows a partial schematic diagram of the connection between the burn-in control circuit i 30 and the horizontal decoder unit 1 100 according to the present invention. The horizontal decoder unit 1100 includes three decoder control signals χ 2 × 2, χ 3 to select one water; a circuit of the horizontal address line w 丨 of the direction address line. The NM0S transistor and crystal part of the decoder unit 1 1 0 includes three NMOS transistors mm, Guan 2, and Dragon 3 connected in series with each other, and the PMOS transistor part includes three pM0s transistors MP and MP2 connected in parallel with each other. , MP3. The burn-in control circuit 13 is composed of a NMOS transistor MN0, a PM0S transistor MP0, and a burn-in mode control terminal β / I. The PMOS transistor MP0 is connected to the power supply VCC and the decoder unit. 〇〇 =, the NMOS transistor MN0 is connected with the drain terminal D0 in the horizontal direction to decode into a unit 1 1 0 0 output terminal M 1 and the source terminal S 0 is grounded in parallel with the NMOS transistor of the decoder unit 丨 丨 〇〇 . The above-mentioned burn-in control circuit 130 and the horizontal direction decoder unit are referred to as partial schematic diagrams because only one of the horizontal address ^ is shown in the figure, and the horizontal address line is implemented as one of the present invention. Example (1 4% ^ 丨 t) 2 = 2k in total, that is, 2 048, so the same circuit has a total of 2,048 groups. Secondly, the address line in the horizontal direction needs 2 1 1 states to be able to choose 2 _ horizontal square two address lines', that is, 1 1 control line, in order to generate enough states for the horizontal square ^ = address line (X-Add) decoder 1 丨 〇. In Figure 3, only three decoders are used for control. It is said that the lines X 1, X 2, X 3 are to simplify the circuit for the convenience of explanation. Those skilled in the art should know how to expand the circuit diagram to the actual needs, and therefore represent limiting the scope of the invention. Turn on or off of transistor mn〇 (turn 〇n

507205 ^ βί

^ _Case No. 89Π6305 V. Description of the invention (7) or tur η ffff) is controlled by the B / I terminal, regardless of the input of the decoder control terminals XI, X2, X3, when the B / I terminal is high At this time, the Lei g g electric body M N 0 is turned on, and the output of the NOT gate 1 32 enters the burn-in mode at this time. On the contrary, when the B / I terminal is at a low potential, the transistor MN0 is turned off, and the high or low potential of the word line W1 is determined by the decoder control signals X 1, X 2, X 3, that is, the same as the normal operation ▲ memory . According to the embodiment of the present invention, each word line has a unique transistor; It MN0 and the B / I end and the horizontal decoder unit 1100 are phase-consumed 9 FIG. 4 shows the state generated according to the design of the present invention. The device 1 4 〇 includes two flip-flops i 4 1 〇, 14 2 0, 1 4 3 0 with clock control, a ^ -type counter connected in series, with a clock CLK and a clock inversion (cl 〇ck ^ bar) CKB 'in order to simplify the design of each flip-flop, first use the vcc terminal as the positive and negative: the tiger input man Cil, the flip-flop U10 output Q. Connected to the positive terminal Ci2, the output Q of the positive terminal 1 420. Then connect to the dry input of the ensemble (enter J13, the output Q0 of positive and negative 1 43 0 is used as the address count =: 2. QJ, phase, the clock CLK will rise when the edge of the clock rises. 2 The public and private Q ^ direction potential and CLKii% on the edge of the positive-phase clock CLK ^ Λ Out terminal Q 0 is only changed once when the Q 03¾ potential and the sea margin rises in normal phase

The three-bit scattered state is the 2 state, which is the most: state? The generator 4 0 0 can provide the Z0 test pattern of the material input terminal, and the state generation ^ is provided to the memory support Qo is provided to the vertical address line to be the highest bit output terminal ^ f U〇. Because only at the input terminal of the QQ QQ counter 150, yuegan 〇3 y 〇2 w 〇 ϋ 复 11 (replay " " low potential) changes to 100 or changes from lu, which represents the pseudo potential "0 " On behalf of _ ^ will be 0 0 〇 will not make the address meter 507205 _ Case No. V. Description of the invention (8) 89116305 Amendment

The address line can be changed again at the input terminal Y of 500, so the vertical unit conversion time can be extended, and the voltage can be added slowly to avoid local damage to the memory chip. FIG. 5 shows a schematic diagram of a sequential addressing circuit of a vertical address line designed in accordance with the present invention. The address counter is a schematic diagram of the address counter. The figure shows the address meter helmet ^ • double it 1 5 丨 as the state. Generator 1 The three-digit state of 4 0 is composed of ten positive and negative crying 1510, 1520, 1530, 1540, (1550, 1560, 1570; ^ shown), 1 5 8 0, 1 5 9 0, and 1 6 0 0 Ring counter connected in series. For example, when ^ is high, the timing of the clock needs to be changed once from low to high, and Tian 'moves once. When Y is high, the timing of the clock needs to be changed twice from low to high, and Q 〇 will change once, and so on. . The ring counters i 5 are shared. : For 2 10ί solid 1K state, in addition, since the input 1 of the address counter 1 4 〇 is raised (produced by the highest bit of the state generator 1 40), a total of 2 _ is the current state, the address counter block 1 Nine control lines with 4 0 output γ q, γ γ K-shaped 3, Υ4, (Υ5, Υ6, Υ7; not shown), Υ, and Υ 丨 are used as vertical 2 Υ address line decoders The control signal. Figure 1 shows the B / I signal and CLK, Z. , Zι, γ. , Γ-thin correlation time-lapse map. The γ-wide γ heart $ tiger is only a signal of a more southern bit. 3 This is omitted. Those familiar with related technologies can easily infer. Operation procedure 1 for the burn-in test due to the circuit according to the present invention1. First pull the B / I signal from low to enter the burn-in test mode t 507205 _ Case No. 89116305_ ^ ^ ^ a_ Correction DESCRIPTION OF THE INVENTION (9) 2. Generate a timing signal and couple to the state generator 150. 3. All word lines are turned on by entering the burn-in test mode. 4. The burn-in test mode turns on the transfer gate 1610 to enter the write phase. 5. The buffers of all vertical address lines are closed. 6. The burn-in test mode is connected to the address counter block 150 to enable the counting to generate a plurality of signals to provide the vertical decoder to write the burn-in test data one by one to the input terminal of the vertical address line. 7. The burn-in test mode turns on the timing input path.

8. The timing input is in the state generator 1 40. 9. The status generator 140 sends an increasing signal to the Y address counter. 1 0. The sequence continues to touch the above circuit until all the vertical address lines are burned out. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 12 507205 9L4. 04 f _Case No. 89116305_ Year Month Day__ Schematic illustration of the preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figures: Figure 1 shows Functional block diagram of burn-in function of a memory chip designed according to the method of the present invention. FIG. 2 shows a schematic diagram of a burn-in and data input switching circuit designed according to the present invention. Figure 3 shows a partial schematic diagram of the connection between the burn-in control circuit and the horizontal decoder unit designed according to the present invention. FIG. 4 is a schematic diagram of a state generator designed according to the present invention. The method of the present invention is a functional block diagram of the relationship between a memory cell and a reference memory cell array when a flash memory is read. FIG. 5 shows a schematic diagram of an address counter control circuit for the sequential rotation of vertical address lines according to the present invention. Figure 6 shows the timing diagram of the relevant signals. Chart number comparison table: The chip to be burned-out test memory cell 100 horizontal address line decoder circuit 110 vertical address line decoder circuit 120 burn-in mode control circuit 130 state generator circuit 140 vertical address line counter circuit 150 Burn-in and data input switching circuit 160

Page 13 507205 Xin θ

wM r 22: inch-value? Amendment number 89116305 The diagram briefly explains the horizontal address line decoder control signal xr x2, x3 Clock (CLOCK) 170 ^ ^ 11 1410, 1420, 1430, 1510, 1520, 1530 '1540 , 1580, 1590, 1600 Flip-flop signal input end Flip-flop output terminal

Cil, Ci2, Ci3, Ci4, Ci8 Ci9, CilO Q 01, Q 02, Q 03, Q 04, Q 08, Q 09, Q 010 132, 1630 D0 SO 1100 1610 ^ 1620 output terminal N1 of the horizontal direction decoder unit Inverter reverse source extreme horizontal direction decoder unit transfer gate

Page 14

Claims (1)

^ U / 205 MM 89116305 6. Scope of patent application: A kind of memory burn-in test circuit for Japanese Yen phase. ^ It has a plurality of horizontal address lines and a plurality of crystal input ports for the memory. The wafer burn-in test circuit includes at least S · Directional address line and B / I mode control circuit, used to switch the complex 3 · line into pre-flash mode or by the horizontal address "horizontal address state generator circuit, providing -Γ- device control mode; The data input terminal of the memory cell chip is written; a few feet of material are used; the address generator circuit is used; the state generator # one binary bit is used as the two younger brothers of the address counter circuit. ^ Input at 1 port, the multiple signals generated by the digital circuit and the status produce the crying emperor ° The second binary bit is used to provide sufficient control of the multiple vertical decoders Alas, each of the vertical address lines: can be uniquely and sequentially turned on; and-the burn-in and data input switching circuit is used to switch the input of one of the normal data and the burn-in data The chip data input terminal. 2. If the wafer stage memory burn-in test circuit of item 1 of the patent application scope, wherein the above-mentioned B / I mode control circuit has a B / I control terminal, when the β / When the I control terminal is at a pseudo potential, all of the plurality of horizontal address lines are raised to a high potential to enter the burn-in test phase. 3 · As stated in the patent phase 2 of the wafer phase memory burn-in test circuit, where The above B / I control terminals are connected to the gates of a plurality of transistors, and the output terminal of each NMOS transistor is connected to an inverter input terminal. Page 15 507205 _Case No. 89116305_Rate · I | 4th Amendment · _ 6. Scope of patent application Between each output end of the horizontal address line decoder. 4. If the wafer stage memory burn-in test circuit of item 3 of the patent application is applied, when the above-mentioned B / I control terminal is at a high potential, the plurality of NMOS transistors are turned on so that the inverter output terminal outputs a high potential. When the B / I control terminal is at a low potential, the plurality of NM0S transistors are turned off, so that the plurality of horizontal address lines are controlled by the input signal of the horizontal decoder. 5. For example, the wafer stage memory burn-in test circuit of the first patent application scope, in which the above state generator circuit provides at least two binary bit counters, and the least significant bit (LSB) provides the above-mentioned When programming data, the most significant bit provides a binary bit status of the address counter circuit. 6. If the wafer stage memory burn-in test circuit of item 1 of the patent application scope, the above state generator circuit is provided with at least three binary bit state counters, and the least significant bit (LSB) provides the above-mentioned When programming data, the most significant bit provides a binary bit status of the address counter circuit. 7. If the wafer stage memory burn-in test circuit of item 1 of the patent application scope, wherein the above state generating circuit is a ring counter with clock control. 8. If the wafer stage memory burn-in test circuit 5 of the patent application item 7 is used, the above state generating circuit is a voltage provided by a wafer voltage source. Page 16 507205 _Case No. 89116305 S_Amendment__ Sixth, the scope of patent application „.:” Is used as the input terminal of the ring counter in the state generator circuit. 9 · If the wafer stage memory burn-in test circuit of item 1 of the patent application scope, wherein the above-mentioned address counter circuit is a 2-bit state ring counter to provide sufficient states to the plurality of vertical direction bits The decoder of the address line has enough control signals. 1 (K is the wafer stage memory burn-in test circuit of the first patent application range, in which the above address counter circuit is an η-bit ring counter with clock control to provide 2 states to the plurality of vertical The control signal of the decoder of the direction address line, so the combination of the second binary bit mentioned above can generate a total of 2η + states. 1 1. For example, the wafer stage memory burn-in test of the first scope of the patent application Circuit, wherein the above-mentioned burn-in and data input switching circuit includes at least two transmission gates and an inverter, and the above-mentioned B / I terminal is connected to the NMOS transistor of the first transmission gate via the inverter In addition, the B / I terminal is directly connected to the gate of the NM0S transistor of the second pass gate, wherein the first pass gate and the second pass gate are connected in series with each other, and the first pass gate The input of the transfer gate is a general data signal, the input of the second transfer gate is a burn-in test signal, and the output of the first transfer gate and the output of the second transfer gate are connected to each other and connected to the Chip information The end. Page 17 507205 4 U f, _Case No. 89116305_f (Amendment '_ VI) Patent application scope; 1 2.-A kind of wafer stage memory burn-in test circuit, the wafer stage memory burn-in test circuit has four The external pins include a voltage source terminal, a ground reference potential terminal, a clock generator terminal, and a B / I terminal. The wafer stage memory burn-in test circuit includes: a B / I mode control circuit, which is received by the B / I terminal The signal switches the plurality of horizontal address lines into a pre-flash mode or a horizontal address line decoder control mode; a state generator circuit provides binary bit data for writing into the data input end of the memory; The address counter circuit uses the highest bit signal generated by the state generator circuit as the signal input of the address counter circuit, the plurality of signals generated by the address counter circuit and the highest bit generated by the state generator circuit. The signal is a sufficient control signal for the decoder to provide the plurality of vertical address lines. Therefore, each of the vertical address lines can be unique and serial. Ground is turned on; and the burn-in and data input switching circuit is coupled to the B / I terminal of the B / I mode control circuit, and one of the normal data and the burn-in data is switched by the signal received by the B / I terminal, Input to the data input terminal of the memory chip. 1 3. The wafer stage memory burn-in test circuit according to item 12 of the patent application scope, wherein the B / I mode control circuit has a B / I control terminal. When the B / I control terminal is at a high potential , All of the plurality of horizontal address lines are raised to a high potential to enter the burn-in test stage. Page 18 507205 _Case No. 89116305_ #-^^ 4 Amendment · _ VI. Scope of Patent Application ---............. '::!:.: , ί: ': 1 4 · If the wafer stage memory burn-in test circuit of item 13 of the patent application scope, wherein the above B / I control terminal is connected to the gate of a plurality of NMOS transistors, and each The output terminal of the NM0S transistor is connected between an inverter input terminal and each output terminal of the horizontal address line decoder. 1 5. According to the wafer stage memory burn-in test circuit of the scope of application for patent No. 14, wherein when the above-mentioned B / I control terminal is at a high potential, the plurality of NMOS transistors are turned on and the inverter output terminal is output. High potential. When the B / I control terminal is at low potential, the plurality of NMOS transistors are turned off, so that the plurality of horizontal address lines are controlled by the input signal of the horizontal decoder. 16 If the wafer stage memory burn-in test circuit of item 12 of the patent scope is applied, the above-mentioned state generator circuit is provided with at least three binary bit counters, and the least significant bit (LSB) provides the above-mentioned The data is pre-programmed, and the most significant bit provides a binary bit status of the address counter circuit. 1 7. The wafer stage memory burn-in test circuit according to item 12 of the patent application scope, wherein the above state generating circuit is a ring counter with clock control. 1 8. The wafer stage memory burn-in test circuit according to item 12 of the patent application scope, wherein the above-mentioned address counter circuit is a 2 n-bit state ring counter to provide sufficient states to the plurality of bars The decoder of the vertical address line has sufficient control signals. Page 19, 507205, Case No. 89116305 6. Scope of patent application /-·· '1 9. If the wafer stage memory burn-in test circuit of item 12 of the patent application scope, the above address counter circuit is an η bit A ring counter with a clock control is provided to provide two states of control signals to the decoders of the plurality of vertical address lines. Therefore, combining the binary bits generated by the state generator circuit described above, a total of 2 η + units can be generated. status. 20. If the wafer stage memory burn-in test circuit of item 12 of the patent application scope, the above-mentioned burn-in and data input switching circuit includes at least two transmission gates and an inverter, wherein the above The B / I terminal is connected to the gate of the NM0S transistor of the first pass gate via the inverter, and the B / I terminal is directly connected to the gate of the NM0S transistor of the second pass gate. The two transfer gates are connected in series with the second transfer gate. The input end of the first transfer gate is a general data signal, and the input end of the second transfer gate is a burn-in test signal. The output gates of the two transfer gates and the second transfer gate are connected to each other and to the data input end of the chip. Page 20