TW506113B - Semiconductor device having electrostatic discharge protection function - Google Patents

Abstract

The present invention provides a semiconductor device having electrostatic discharge (ESD) protection function. The invention includes a guard portion and a MOS (metal oxide semiconductor) transistor array formed in the guard portion. In the invention, the MOS transistor array is at least provided with the first MOS transistor and the second transistor. In addition, the first MOS transistor is closer to the guard portion than the second MOS transistor. The channel length of the second MOS transistor is longer than that of the first MOS transistor.

Description

The present invention relates to a semiconductor device with a "protective semiconductor device." In particular, it relates to static electricity. [Conventional Technology] Often, protection is one of the most important fields in integrated circuits. Because static electricity is extremely large, Voltage (may be tens of thousands of volts), so those who are familiar with it will use Electro-static Discharge (Electro-static Discharge) to protect semiconductor devices to prevent semiconductor devices from being damaged by static electricity. ㈣ Refer to Figure 1A, which shows a The circuit layout diagram of the body device 1 with electrostatic discharge protection is known. The semiconductor device includes a guard 11 and a MOS transistor array (M0s is referred to as "rayj") 12, and a MOS transistor array 12 It has a plurality of Mos transistors, which are formed by a plurality of source 121, drain 122 and gate 123. The circuit layout of the gate 123 is as follows: Finger-shaped, so the semiconductor device shown in FIG. 1A is a finger-type. FIG. 1B shows a schematic cross-sectional view of the semiconductor device shown in FIG. 1A along line AA, as shown in FIG. 1B A plurality of N + diffusion areas (N + diffusion areas) and a plurality of p + diffusion areas are formed on the substrate 20, where the N + diffusion areas 21 and 22 serve as the source electrode 12 ′ and the drain electrode 12 shown in FIG. 1A, respectively. 2 'P + diffusion region 2 3 serves as the protection part shown in FIG. 1 a 丨 丨, since the N + diffusion regions 21 and 22 and the substrate 20 will form a first parasitic bipolar junction transistor' (parasitic bipolar junction transistor)

506113 V. Description of the invention (2) parasitic BJT) 24. Therefore, static electricity (such as Human-Body Mode (HBM)) can pass from the P + diffusion region through the base of the first parasitic junction carrier transistor 24. 23 discharges, thereby protecting the transistor array 12. As mentioned above, the above-mentioned protection part 11 is a guard ring. According to the same principle, the N + diffusion regions 22 and 25 and the substrate 20 will form a second parasitic junction carrier transistor 26 (as shown in the figure). (Shown in FIG. 1B), and static electricity can also be diffused from p + by the base of the second parasitic junction junction transistor 26 to discharge 2 3 to ensure compliance with the M 0 S transistor array 12. In addition, the channel length (channeieng) Li is between the N + diffusion regions 21 and the disk 22, and the channel length L2 is between the N + diffusion regions 2 and 25. Basically, the channel length Li is equal to the channel length factory. Theoretically, if more parasitic di 2 carrier junction transistors are formed in a semiconductor device, the electrostatic resistance of the semiconductor device (esd

Robustness), in other words, in finger electrostatic discharge protection half, body devices, because the finger width (finger width) is usually ^

= f (for example, 300 #m), so the electrostatic tolerance 1 of a semiconductor device increases as the number of fingers increases. However, because the distance D2 between the second parasitic double junction junction transistor 26 and the P diffusion region 23 is greater than the distance Di between the first parasitic double junction hand junction transistor 24 and the P diffusion region 23 (as shown in FIG. 1β), =, The first substrate resistance Rsub2 will be greater than the first substrate resistance I. Therefore, during electrical discharge, the base level due to the collapse of the P_N junction will be greater than the base of the first parasitic junction junction transistor 24. The potential of the second parasitic bipolar junction transistor 26 will be turned on first.

Page 5 506113 V. Description of the invention (3) The M0S transistor forming the second parasitic bipolar junction transistor 26 first reaches the second breakdown current :), that is, the M0S transistor array 1 The central part of 2 (shown in Figure 1A) may reach the secondary breakdown current earlier than the other parts (shown in Figure 2). In addition, in theory, the electrostatic tolerance of the human discharge mode is equal to the product of the secondary breakdown current and the equivalent resistance of the human discharge mode (1 · 5k Ω). To sum up, the second transistor that forms the second parasitic double-carrier junction transistor 26 will first reach the limit of the electrostatic tolerance and be destroyed. In other words, the conduction speed of each finger is different, resulting in uniform conduction. Poor performance makes the ESD protection capability of semiconductor devices worse than expected. In order to improve the above-mentioned problems, those skilled in the art can use circuit techniques to improve the conduction uniformity of each finger, for example, in the shape of the first parasitic bipolar junction transistor 24 rib 3 transistor A substrate contact is formed between the second transistor and the second transistor which forms the second bimorph junction transistor 26 (s = trate-Triggered Area) (not shown in the figure). Ran. ^ Circuit techniques will increase the area of the circuit layout, which will further increase the cost 増 above, and improve one of the issues under each product. How to make the uniformity of the circuit without significantly increasing the uniformity of the circuit layout is very important at the present time [Summary of the Invention] A situation where the area of the electrical layout of the object of the present invention can be aimed at the above problems with a small uniformity of the conduction Each of the following five, the description of the invention (4) /, static 2 discharge protection of the semiconductor device V device 'including a' according to the invention with the electrostatic discharge protection of the rich · ^ anti-thickness part and a MOS power circuit In the case of the conductor, the MOS transistor array ::; array. In one of the inventions-第 -MOS 雷-# is formed in the protective part and at least Nonggu electric power body, and a second MOS transistor, there is ~ MOS transistor is also worse than the second one _Transistor of the transistor 3: electricity: body crime is near protection, and in addition, in this hair, the length of the month is another greater than reality V ::: the channel length conductor of the crystal ...: "like in" according to the invention Gu Jing

In the evil way, the electric conductor protects the trout, and in accordance with the present invention, the electrical conductor of the electric edge of the abundance conductor device further includes a first I 2 = closed-pole electrical connection of the first MOS transistor ^ resistance ^ two electrical = —The gate of the MOS transistor is another one of the first resistor and the second resistor that electrically connects the first resistor and the second resistor, ί ^ ΐ i ί " M0S1 " ^-% resistance value is greater than the resistance value of the second resistance . Several ΐϊ:,: In an implementation aspect, the transistor array includes a complex surface transistor S, and some of the gate transistors of the Mos transistor are electrically connected and constitute a first Finger, the gates of some of these MOS transistors are electrically connected to form a second finger, where the '-th finger is closer to the guard than the second finger, and the width of the second finger is greater than the width of the first finger . In addition, the semiconductor device with an electrostatic discharge protection combination according to the present invention includes a first protection portion, a second protection portion, a -th -MOS transistor array formed in the first protection portion, and a formed in the first A second MOS transistor array in the two protection parts. In this aspect, the first pin transistor array

5. Description of the invention on page 7 (5) The column has a plurality of MOS transistors, the second MOS transistor array has a plurality of NMOS transistors, and the channel length of the 2003 transistor of the second NMOS transistor array is greater than The channel length of the NMMOS transistor of the first NMMOS transistor array is as described above. Because the semiconductor device with electrostatic discharge protection according to the present invention is provided with a channel length of not more than 〇s based on the distance from the protective part. Crystals, or MOS transistors are provided to connect to different resistors, fingers of the same width, or to provide channel length / different M0S transistors in different guards. In other words, the present invention only slightly modifies the size of the circuit cloth. Therefore, the conduction uniformity of each finger can be improved without greatly increasing the area of the circuit layout. [Detailed description of the preferred embodiment] Hereinafter, a semiconductor device for electrostatic discharge protection will be described with reference to related drawings and symbols. A device according to a preferred embodiment of the present invention will be described, in which the same components will be the same. ▲ Please refer to FIG. 3A. A semiconductor device 3 with static electricity according to a preferred embodiment of the present invention includes a protective portion 31 and a -M0S transistor array 32, M0s transistor array 32 in the guard 31-M0S transistor 321, a second_transistor m, a third brother 2 = s crystal m 'and the first Hall transistor: than "Sin near protection 31" The third m0s transistor 323 is better than the third = M〇 ^ B 日 体 324 sin near protection 31, the channel length LJ of the second hall transistor 322 is -M0S The channel length of the transistor 321 is Li, and the fourth transistor 506113 is deleted. 5. The description of the invention (6) The channel length 14 of the body 324 is greater than the channel length L3 of the third MOS transistor 323. As shown, the channel length L1, channel length L2, channel length L3, and channel length L4 are the lengths of the first finger 341, the second finger 342, the third finger 343, and the fourth finger 344, respectively, and the first MOS transistor The distance Di between the 321 and the protective portion 31 is equal to the distance D3 between the third MOS transistor 323 and the protective portion 31. The channel length k is equal to the channel length l3; the distance d2 between the second MOS transistor 322 and the protective portion 31 is The distance D4 between the four M0S transistors 324 and the protective portion 31 is equal. On the contrary, the channel length l2 is equal to the channel length l4. In this embodiment, the above-mentioned MOS transistor system is a NMOS transistor, and the gates of the MOS transistors are electrically connected to each other, that is, the fingers are electrically connected. In addition, the gates (or the fingers) of these M0S transistors are grounded. This setup is even gate grounded (Q a ^ e _ Q r 〇 und e d). As mentioned above, the aforementioned guard 3 is a guard ring. In addition, in the semiconductor device 3 with electrostatic discharge protection in the preferred embodiment of the present invention, an isolation portion 33 is formed between the protection portion 31 and the MOS transistor array 32, for example, a shallow trench insulation portion (shallow trench isolation portion (STI). / Next, please refer to FIG. 3B to further explain how the semiconductor device 3 with electrostatic discharge protection according to a preferred embodiment of the present invention discharges static electricity. FIG. 3β shows a schematic cross-sectional view of the semiconductor device in FIG. 3A along line BB. Taking the first MOS transistor 321 and the second MOS transistor 322 as an example, the first parasitic junction junction transistor 44 and the second The parasitic bipolar junction transistor 46 can be used as an electrostatic discharge protection π component. In this embodiment, since the channel length ^ (the distance between the N + diffusion region 41 and the N + diffusion region 42) is smaller than the channel length, (N +

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506113 V. Description of the invention (7) The distance between the scattered region 4 2 and the N + diffusion region 4 5), so that the second parasitic bipolar junction transistor 46 reaches a first breakdown and enters the step. The potential of the snapback breakdown region will be greater than the potential at which the first parasitic bipolar junction transistor 44 reaches a breakdown, in other words, when static electricity flows into the semiconductor device 3, the first parasitic bipolar junction transistor 44 will pass through the second parasitic bipolar junction transistor 46 to discharge static electricity. In addition, as described above, since the distance between the second parasitic double-sided transistor 46 and the P + diffusion region 43 is greater than that of the first parasitic double-sided transistor 46 Electricity: The distance d! Between the body 2 and the P diffusion region 43! Therefore, the second substrate resistance Rsub is "greater than the first substrate resistance Rsum '. Therefore, the potential of the base of the second surface transistor 46 will be greater than! That is, when the electrostatic current two = "find the first parasitic bipolar junction transistor 46 surface transistor" conducted first to release the static :: the second embodiment is connected to the preferred embodiment and the electrostatic discharge lightning protection = * 、 Γ As mentioned above, according to the present invention, each channel length and each substrate resistance pair The influence of the various geniuses is to enable the second parasitic junction transistor to switch on the parasitic element, such as the parasitic element; the double-junction transistor 46 and the first double-junction transistor 44 are simultaneously turned on. The uniformity of the conduction of the S transistor to release static electricity and discharge quietly, that is, k liters each. FIG. 4 shows a circuit layout of another semiconductor device 4 according to the present invention, showing one end of the electrostatic discharge protection finger 341 and the third finger 343. FIG. In this embodiment +, the first to the first-resistor R1 and the second finger are connected to each other, and the other end of the resistor R1 is a resistor R2. It should be noted that in this 506113 V. Description of Invention (8) Implementation For example, the resistance value of the first resistance core and the resistance value of the second resistance & may be equal, or the resistance value of the first resistance ratio may be greater than the resistance value of the second resistance R2, and the first resistance core and the second resistance The function of the resistor r2 is to eliminate the above-mentioned first substrate resistor Rsubl and the first substrate resistor from the base of the first parasitic junction transistor 44 and the base of the second parasitic junction transistor 46. Effect (as shown in Figure 1B). Those who are familiar with the technology should 'Each finger has the same semiconductor structure as the gate of the corresponding MOS transistor, and the length of each finger is the same as the length of the corresponding channel. Please refer to FIG. 5, which shows another preferred embodiment of the present invention. A schematic diagram of the circuit layout of the semiconductor device 5 with electrostatic discharge protection. In this embodiment, the lengths of the fingers are equal, that is, the lengths of the channels are specific, and the width of the fingers ( (finger width) varies depending on the distance from the guard 31. In more detail, since the distance D2 between the second finger 342 and the guard 31 is greater than the distance Di 'between the first finger 341 and the guard 31, the second finger The width Wf2 of 342 is greater than the width Wf of the first finger 341! Similarly, because the distance h between the fourth finger 344 and the guard 31 is greater than the distance d3 between the second finger 3 4 3 and the guard 31, the fourth finger 3 The width Wh of 4 is larger than the width Wf3 of the third finger 343. As described above, the semiconductor device 5 series provides a longer finger width to the MOS transistor region 51 'which is easy to be turned on first, such as the second MOS transistor 322 and the first MOS transistor 322. Four M0S transistor 324 So slow delay such M0S transistors electrically M0S crystal region 51 reaches the secondary crash, such as to be able to make M0S transistor the ON state simultaneously, thus increasing the conduction of each finger of each sentence. Please refer to FIG. 6, which shows a static state according to a preferred embodiment of the present invention.

Page 11 506113 V. Description of the invention (9) Schematic diagram of the circuit layout of the semiconductor device 6 in the present-: protective portion 3; Φ conductor device 6 includes a first protective portion 31a, formed at the portion 31b and point J 7 The first MOS transistor array 32a,-the second guard column 32b. / A second MOS transistor array is connected in the second protection part, and the first protection part 3U and the second protection part 31b adjacent to the transistor array 32a have a plurality of M0s transistors. Crystal, the first MGS transistor array also has a plurality of s transistors, and the channel length L2 of the EEG crystals in the transistor array 32b is greater than the channel length of the M0S transistors in the first MOS transistor array 32a. l. Therefore, when the direction of the electrostatic current is as shown in arrow E, the 1108 transistor in the second transistor column 321) can be turned on at the same time as the M0S transistor in the first transistor transistor array 3 ^, thereby increasing each Finger conduction uniformity. It should be noted that those who are familiar with this technology should understand that the above M0S transistor array may include more M0s transistors, such as / above, or that each of the above semiconductor devices may include more / pointers. , Such as 6 or more. In addition, in the semiconductor device 6, it may include three or more guard portions and a MOS transistor array. " Ldk The above description is exemplary only and not restrictive. Any equivalent modification or variation of the spirit and scope of the present invention shall be included in the scope of the attached patent application. ’Both

Page 12 506113 Schematic description [Schematic description] Figure 1A is a schematic diagram showing the circuit layout of a semiconductor device with electrostatic discharge protection. The channel length of each M0S transistor is equal. FIG. 1B is a schematic view showing a cross-sectional view of the semiconductor device along a line AA 'in FIG. 1A. FIG. 2 is a schematic diagram showing the non-uniform conduction of the MOS transistor array when the semiconductor device shown in FIG. 1A is discharged with static electricity. FIG. 3A is a schematic diagram showing electrostatic discharge according to a preferred embodiment of the present invention. Schematic circuit layout of a protected semiconductor device. Fig. 3B is a schematic view showing a cross-sectional view of the semiconductor device along the line BB 'in Fig. 3A. Fig. 4 is a schematic diagram showing the circuit layout of a semiconductor device with electrostatic discharge protection according to another preferred embodiment of the present invention-> Fig. 5 is a schematic diagram showing another preferred embodiment of the present invention Circuit layout of a semiconductor device with electrostatic discharge protection (> FIG. 6 is a schematic diagram showing a circuit layout of a semiconductor device with an electrostatic discharge protection combination according to a preferred embodiment of the present invention) ] 1 Semiconductor device 11 Protective part 12 M0S transistor array 121 Source

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506113 Schematic illustration 122 Drain 123 Gate 20 Substrate 21 N + diffusion region 22 N + diffusion region 23 P + diffusion region 24 First parasitic junction junction transistor 25 N + diffusion region 26 Second parasitic junction carrier Crystal 3 Semiconductor device with electrostatic discharge protection 31 Guard 31a First guard 31b Second guard 32 MOS transistor array 321 First MOS transistor 322 Second MOS transistor 323 Third MOS transistor 324 Fourth MOS transistor Crystal 32a First M0S transistor array 32b Second MOS transistor array 33 Insulation part 341 First finger 342 Second finger 343 Third finger

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506113 Brief description of the diagram 344 Fourth finger 4 Semiconductor device with electrostatic discharge protection 41 N + diffusion region 42 N + diffusion region 43 P + diffusion region 44 First parasitic junction junction transistor 45 N + diffusion region 46 Second parasitic dual load Sub-junction transistor 5 Semiconductor device with electrostatic discharge protection 51 M0S transistor region that is easy to be turned on first 6 Semiconductor with electrostatic discharge protection combination Di First M0S transistor (or first finger) d2 Second M0S transistor (or Second finger) Db Third M0S transistor (or third finger) V Fourth M0S transistor (or fourth finger) Li Channel length L2 Channel length L3 Channel length l4 Channel length Ri First resistance Second resistance Rsubl First Substrate resistance Rsub2 Second substrate resistance Wfi First finger width

Page 506113

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Claims (1)

506113 VI. Application Patent Scope 1. A semiconductor device with electrostatic discharge protection, comprising: a guard port ion; and a MOS Metal Oxide Semiconductor Transistor Array formed in the guard portion. And has at least a first M0S transistor and a second M0S transistor, wherein the channel length of the first M0S transistor is smaller than the channel length of the second M0S transistor and the first M0S transistor The crystal system is closer to the protection portion than the second MOS transistor. 2. The semiconductor device with electrostatic discharge protection as described in item 1 of the scope of patent application, wherein an isolation portion is formed between the protection portion and the MOS transistor array ° 3. The semiconductor device with electrostatic discharge protection described above, wherein the insulating portion is a shallow trench isolation port (STI) ° 4. The semiconductor device with electrostatic discharge protection as described in item 1 of the scope of patent application, The first MOS transistor and the second MOS transistor are off-state transistors. 5. The semiconductor device with electrostatic discharge protection as described in item 1 of the scope of patent application, wherein the gate of the first MOS transistor is electrically connected to the gate of the second transistor. Section 17 Stomach 506113 6. Application Patent Scope 6. The semiconductor device with electrostatic discharge protection as described in item ί of the patent application, wherein the gate of the first M0S transistor and the gate of the second M0S transistor are Ground. 7. The semiconductor device with electrostatic discharge protection as described in item 1 of the scope of the patent application, further comprising: a first resistor and a second resistor, one end of the first resistor and one end of the second resistor being electrically connected to The gate of the first MOS transistor and the gate of the second MOS transistor, and the other end of the first resistor and the second resistor are grounded. 8. The semiconductor device with electrostatic discharge protection as described in item 7 of the scope of the patent application, wherein the resistance value of the first resistor is greater than the resistance value of the second resistor. 9. The semiconductor device with electrostatic discharge protection as described in item 7 of the scope of patent application, wherein the resistance value of the first resistor is equal to the resistance value of the second resistor. 10. The semiconductor device with electrostatic discharge protection as described in item 1 of the scope of patent application, the MOS transistor array further includes: a third transistor, a channel length of the third transistor and a length of the first transistor Equal channel lengths; and 丄 J The fourth transistor has a channel length equal to that of the fourth transistor, Connected. The gate of the third transistor is electrically connected to the gate of the four transistor 1 1. According to the first Q body device of the scope of the patent application, it further includes: The terminal of the semi-conductive resistor-resistor with electrostatic discharge protection described in Λ is electrically connected to the resistor and the second one respectively. The gate of the MOS transistor, the first-"..." is grounded. The resistance value of the semiconductor with electrostatic discharge protection described in the other end of the resistor and the first resistor is greater than the resistance of the second resistor 1 2 1. The body device with the scope of the patent application, where the first resistance value. 13. The half body device with electrostatic discharge protection as described in the scope of the patent application, with the resistance value of the first resistor equal to the second Resistance 14. A semiconductor device with electrostatic discharge protection, comprising: a protective portion; a MOS transistor array 'formed in the protective portion, and having at least 506113 6. The scope of the patent application includes a first M0S transistor and a second M0S transistor. The channel length of the first M0S transistor is equal to the channel length of the second M0S transistor. The second M0S transistor is close to the protective portion; a first resistor, one end of which is electrically connected to the gate of the first M0S transistor, and the other end of which is connected to ground; and a second resistor whose one end is It is electrically connected to the gate of the second MOS transistor, the other end of the second resistor is grounded, and the resistance value of the first resistor is greater than the resistance value of the second resistor. 15. The semiconductor device with electrostatic discharge protection as described in item 14 of the scope of patent application, wherein an insulation portion is formed between the protection portion and the MOS transistor array. 16. The semiconductor device with electrostatic discharge protection according to item 15 of the scope of the patent application, wherein the insulation portion is a shallow trench insulation portion. 17. The semiconductor device with electrostatic discharge protection as described in item 14 of the scope of patent application, wherein the first M0S transistor and the second M0S transistor are NMOS Transistor. 18. The semiconductor device with electrostatic discharge protection as described in item 14 of the scope of the patent application, wherein the MOS transistor array further has a third transistor and a fourth transistor, and the channel of the third MOS transistor The length is equal to the channel length of the fourth MOS transistor, and the third MOS transistor system is longer than the fourth MOS transistor system. Page 20 506113 VI. Patent application scope ~-The M0S transistor is close to the protection part, and the semiconductor device further includes: a third resistor whose terminal is electrically connected to the gate of the third MOS transistor, the The other end of the third resistor is grounded; and a fourth resistor whose one end is electrically connected to the gate of the fourth MOS transistor, and the other end of the fourth resistor is grounded. — 19. A semiconductor device with electrostatic discharge protection, comprising: a protective portion; and a MOS transistor array formed in the protective portion and having at least a first finger and a second finger. A finger is closer to the protective portion than the second finger, and a width of the first finger (in width) is smaller than a width of the second finger. 20. The semiconductor device with electrostatic discharge protection according to item 9 in the scope of the patent application, wherein an insulation portion is formed between the protection portion and the MOS transistor array. X has a 21. A semiconductor device with electrostatic discharge protection as described in item 20 of the scope of the patent application, wherein the insulating portion is a shallow trench insulating portion. 22. The semiconductor device with electrostatic discharge protection according to item 9 in the scope of the patent application, wherein the first MOS transistor and the second MOS transistor are nmos transistors. # Page 21 506113 6. Patent application scope 23. The semiconductor device with electrostatic discharge protection as described in item 19 of the patent application scope, wherein the first finger is electrically connected to the second finger. 24. The semiconductor device with electrostatic discharge protection as described in item 19 of the scope of patent application, wherein the first finger and the second finger are grounded. 25. A semiconductor device with an electrostatic discharge protection combination, comprising: a first protection portion; a first MOS transistor array formed in the first protection portion and having a plurality of MOS transistors;-a second protection portion , Which is adjacent to the first protection part; and a second MOS transistor array, which is formed in the second protection part and has a plurality of MGS transistors, and one of the MOS transistors in the FMQS € crystal array The channel length is greater than the channel length of the special MOS transistor in the first MOS transistor array. 26. The semiconductor device with an electrostatic discharge protection combination according to item 25 of the scope of the patent application, wherein a first insulation portion is formed between the first protection portion and the first rib transistor array, and the second protection portion A second insulating portion is formed between the second MOS transistor array and the second MOS transistor array. 27. The semiconductor device with an electrostatic discharge protection combination according to item 26 of the scope of the patent application, wherein the first insulation portion and the second insulation portion are shallow trench insulation portions. 506113 VI. Scope of patent application 28. If a patent application is made for a semiconductor device, its t body and the second MOS body. 2 9. If applying for a patent | For a semiconductor device, the gates of its t body are mutually gates of 1 M0S transistor. 30. If for a patent for a semiconductor device, its t body's gate is grounded. The gate is grounded. 丨The MOS transistor in the _M0s transistor array described in item 25 with the electrostatic discharge protection combination is the NM0S transistor & The electrostatic discharge protection combination described in 25 items> The M0S transistors in the -M0S transistor array are connected, and the materials in the multi-transistor array are electrically connected to each other. The Mos electric crystals in the 25th array of the electrostatic discharge protection combination are the electric crystals in the first MoG array, and the second MOS electric circuit.