TW502494B - RF communication system using an RF digital amplifier - Google Patents

Abstract

Band pass amplifiers and methods for driving the same are described. According to one embodiment, a frequency selective network is provided in a feedback loop. An analog-to-digital converter is coupled to the frequency selective network. A switching stage is coupled to the analog-to-digital converter for producing a continuous-time output signal. The switching stage includes at least one resonance circuit configured to resonate at a resonance frequency and thereby generate at least a portion of the continuous-time output signal. A continuous-time feedback path continuously senses and feeds back the continuous-time output signal to the frequency selective network.

Description

502494 A7 B7 V. Description of the invention (1) Background of the invention The present invention relates to radio frequency (R F) communication systems in different aspects. (Please read the notes on the back before filling out this page.) Wireless communications such as cellular phones for voice and data have become quite popular. Currently, several wireless designs are used, including G S M, T D M A, and CDMA. In these designs, CDMA is clearly becoming the standard for the US, European, and Asian markets. Therefore, the efficiency and power consumption of a power linear amplifier used to generate RF signals in a CDM cellular phone or base station are very important. The use of low-efficiency linear amplifiers is harmful for several reasons. These amplifiers consume considerable amounts of energy, which is problematic especially in battery-operated cellular telephones. In base stations, power consumption is also an issue. The heat generated by many inefficient amplifiers in the base station can cause component failures, reducing reliability. The linearity of the power amplifier is also important. In base stations transmitting multiple signals at the same time, amplifiers with poor linearity can cause these signals to inadvertently mix. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs There are several amplifier grades that can be used in RF communication systems, including grade A, grade A B, grade C, grade E, grade F, and grade D (sometimes called digital amplifiers). However, each of these types of amplifiers has significant problems when operating in the R F range. For example, Class A and Class A B amplifiers have very poor efficiency. Although Class C, E, F, and D amplifiers have improved power efficiency compared to Class A and Class A B amplifiers, they are not suitable for linear applications. In addition, Class E amplifiers experience severe overshoot problems at their outputs, limiting their use. Under repeated input signals, the grade F amplifier presents the paper size corresponding to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) -4- 502494-A7 ______B7 V. Description of the invention (2) Good output switching characteristic. However, the problems caused by harmonics can become serious with non-repetitive input signals such as those found in cellular phones or base stations. As a result, Class F amplifiers are difficult to use in R fT linear power amplifier applications. Traditional grade D amplifiers have linear operating characteristics at lower frequencies and usually have high efficiency, but at higher frequencies, there have been several shortcomings in the past. Most seriously, they have switching problems at their output transistors at higher frequencies such as RF. When these transistors are turned on and off quickly, a switching transition involving high levels of current and voltage occurs at the output, causing overshoot and overshoot. FIG. 1 shows an RF band-pass noise spectrum shaping amplifier 100 according to a specific embodiment of the present invention. It is important to note that the inclusion of this novel amplifier configuration in the background note is only to provide background information regarding further improvements to this basic configuration described here. This configuration should not be assumed to be a know-how. In fact, the amplifier 100 represents a novel structure different from the old band-pass structure. The RF amplifier 100 includes a frequency selective network 10 which uses continuous time feedback to apply a modulated RF input to the noise spectrum shaping. The network 102 includes at least one resonator stage having a transfer function designed to pass through a frequency band centered on, for example, 900 MHz. The A / D converter 104 uses the sampling frequency f s (for example, 3 · 6 G Η z in this embodiment) to convert the RF signal formed by the noise spectrum into digital data. The A / D converter 104 includes a single comparator. Alternatively, the A / D converter 104 includes a three-digit quasi-paper standard applicable to the Chinese National Standard (CNS) A4 specification (2 丨 〇 > < 297 mm) (Please read the precautions on the back before filling in this Page), 1T -Φ-. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -5- 502494 A7 B7 V. Description of the invention (3) Switching comparator. (Please read the precautions on the back before filling this page) Gate drive circuit 1 06 takes the pulse train from A / D converter 104 and generates the gate drive for the power output stage of the amplifier 100 Of each of the FETs 108 and 10. The output power stage shown includes three inductors LI, L2, and L3, and capacitor C1. When the counterparts in FETs 108 and 110 are closed, this configuration generates separate resonances at nodes A and B, respectively. Through the feedback path 1 12, continuous time feedback is provided to the frequency selection network 1 2. The output signal of the power stage will be sent to the matching network 1 1 4 and the matching network 1 1 4 will send the output RF signal to the antenna 1 1 6 for transmission. The top and bottom F E T 108 and 110 are driven alternately by the gate signals generated by the gate drive circuit 106 at the output of the A / D converter 104. If the FETs 108 and 110 are driven by switching signals such as square waves, the parasitic gate capacitance of each device will cause serious and unnecessary loss. This loss is related to the frequency of the gate signal, the gate capacitance, and the economy. Ministry of Intellectual Property Bureau employee consumer cooperative printing and input voltage squared is proportional to f cv2 loss. Therefore, the inductor 1 1 8 will be connected in series with each F E T gate to resonate to eliminate f c v 2 loss. As described above, the frequency selection network 10 2 cooperates with the continuous time feedback path 1 12 to provide noise spectrum shaping to the amplifier. The network 10 2 includes one or more resonator stages. Although this will reduce these unnecessary losses, there are other undesirable consequences. First, an undesired and substantially overshoot (or down) voltage is generated at the input of each F E T during the gate signal transition. Second, each paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -6-502494 A7 B7 V. Description of the invention (4) The transition of a gate at each gate is virtually infinite Ground continuous resonance. If the amplifier is only used to generate a regular pattern of 0 and 1 interleaving (frequency and phase modulation applications), this resonance is not a problem because it will cause the required bit pattern (if overshoot / downshift is acceptable). For applications that require aperiodic bit patterns, this resonance interferes with the generation of the required bit patterns. In addition, the use of a fixed timepiece to produce a timepiece for A / D converter 104 (ie, f s) has disadvantages. First, the timing of the resonances at nodes A and B usually needs to match the timing of this time to maximize efficiency. However, in fact, for example, the resonances at nodes A and B tend to vary in frequency due to the response from the matching network 114 and the processing mutation. Second, due to design complexity, it is generally undesirable to have separate timepieces for the A / D converter in this design. As is known, the amplifier configuration of FIG. 1 allows a binary state. With the two-quantization state, there will be a larger number of signal transitions that lead to high drive losses. According to pulse width modulation (pw M) and other modulation techniques, the delay caused by switching and output filter stages must be effectively handled To mitigate the adverse effects of this delay on circuit stability. This is especially true for modulators with fairly high power switching stages, as the delay becomes large relative to the pulse repetition frequency of the loop. The conventional solution to this delay processing will be explained with reference to Figs. 2 and 3. Figure 2 is a block diagram of a typical modulator circuit 200. The logic output of the modulator 2 0 2 will drive the inverting power stage 2 0 4 and the inverting power stage. The paper size applies the Chinese National Standard (CNS) Α4 specification (210 > < 297 mm) (please read the Please note this page and fill in this page) Order Φ .. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives 502494 A7 B7 V. Invention Description (5) (Please read the notes on the back before filling this page) 2 0 4 output meeting Filtered by output filter 2 0 6. The feedback resistor 2 0 8 and the attenuation resistor 2 1 2 are used to introduce negative feedback from the loop output of the modulator 2 0 2. FIG. 3 shows waveforms 3 2 and 3 4 of the second regulator circuit without delay compensation from FIG. 2. As shown, the positive swing of waveform 3 0 (ie, output filter 2 0 6) and the positive swing of waveform 3 0 2 (ie, modulator 202) due to the delay of switching and filter stage introduction. Logic output) is almost in phase. Therefore, in cases where the loop's original design considered negative feedback, the delay would convert it to positive feedback, thus causing the loop to be unstable (not shown). Therefore, a filter capacitor 2 10 is provided in parallel with the feedback resistor 208 for delay compensation. Capacitor 2 10 produces zero in the feedback loop. For high frequencies, the attenuation caused by resistors 208 and 2 1 2 can be bypassed. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Unfortunately, since this type of delay compensation is performed after the delay introduction of the loop, it is difficult to correct all negative delay results related to loop stability. In fact, this type of compensation technology has only limited results. As a result, the delay tolerance and overall performance of today's modulators have been limited. One solution is to use a feedback signal directly from the logic output of the modulator (that is, before the delay is introduced) combined with the output of the power stage and / or output filter. Unfortunately, although the output of the modulator (302) has similar characteristics to the filter output (304), due to the non-linear nature of the power stage, useful content of the frequency range of the modulator loop There will be significant differences. This will make it difficult to achieve high-fidelity operation when giving back these signals. Based on the above, there is a need for a band-pass amplifier that overcomes the different problems described above. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -8- 502494 A7 B7 V. Description of the invention (6) Invention description (please read the precautions on the back and fill in this purchase first) In one aspect, a band-pass amplifier with a frequency-selective network in the feedback loop is provided. The analog-to-digital converter is coupled to the frequency-selective network. The switching stage is coupled to the analog-to-digital converter to generate a continuous-time output signal. The switching stage includes At least one resonance circuit which resonates at a resonance frequency and generates at least a part of a continuous-time output signal. The continuous-time feedback path will sense and feedback the continuous-time output signal to a frequency selection network. It is also provided for a band-pass amplifier. Switching stage. The switching stage includes first and second switching switches in a half-bridge configuration. Both the first and second switching switches have parasitic capacitances associated with them. The switching stage includes multiple inductors. The second resonant circuit consists of parasitic capacitances. And inductor formation, the two resonance circuits are staggered resonance at the resonance frequency. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In another aspect, since these inductors need to reduce the fcv 2 loss at the FET gate, the present invention provides a gate drive circuit to control the gate signal technology to overcome the problems of overshoot and resonance. That is, the gate drive The leading and trailing edges of the gate pulses generated by the circuit will be temporarily brought to the logic level, brought back to the original logic level, and then brought back to the desired level when the signal level of the FET gate is settled. To the required logic level. In general, the present invention uses control logic and inductors to charge the logic state of the gate capacitor. Therefore, the present invention provides a switch for switching a switch from a first logic state to a second logic state. Method and device for the state. The switch has a gate terminal, and the gate terminal has a gate capacitor and a resistance associated therewith. According to different embodiments, the Chinese paper standard (CNS) A4 applies to this paper scale. (210X297 mm) -9 -502494 A7 __B7_ V. Description of the invention (7) (Please read the precautions on the back before filling out this page). This resistor can be the input resistance of the switch in series and parallel with the outside. Any combination of resistors. The gate terminal also has a series inductance coupled to it. When the switch is in the first logic state, a pulse corresponding to the second logic is applied to the inductor. The pulse has a first level associated with it Energy, which is high enough to overcome the attenuation caused by the resistance (thus allowing the gate terminal to reach the signal level corresponding to the second logic state, thereby switching the switch to the second logic state), and low enough to slow down the inductance due to inductance And the gate capacitor oscillation (so that the gate terminal is settled at the signal level before the switching switch then transitions to the first logic state). According to another aspect of the invention, one of the output switching stages of the amplifier design is used or More resonance to generate the A / D converter timing signal for the amplifier. According to an embodiment, in a case where the output stage includes two switching devices, the resonance nodes related to the two devices are used in a staggered manner to generate a timepiece message.

Prfe sparse. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Therefore, the present invention provides an electronic device including a sampling circuit and at least one switching device. Each switching device has a resonant circuit associated with its output. The resonance circuit and at least one switching device have at least one resonance oscillation associated therewith. The electronic device further includes a timepiece generating circuit which generates at least a portion of at least one resonance oscillation to generate a timepiece signal for the sampling circuit. According to another aspect of the present invention, there is provided an amplifier structure in which multi-level switching can be activated. That is, the amplifier structure described herein exhibits more than two quantized states. This is achieved in part through parallel signal paths, each of which has its own sampling circuit. The multi-quantization state includes a state where no signal is output, so as to avoid the unnecessary switching loss mentioned above. Applicable to China National Standard (CNS) A4 specification (210X297 mm) according to I paper size -10- 502494 A7 B7 V. Description of the invention (8) In specific embodiments, the timepiece signal for different sampling circuits will develop independently, causing other Multiple advantages. (Please read the precautions on the back before filling this page) Therefore, the present invention provides an electronic device including at least two sampling circuits and at least two switching stages connected in parallel. Each switching stage is coupled to one of the sampling circuits. The sampling circuit and switching stage enable the electronic device to exhibit more than two quantization states. The electronic device further includes a timepiece generating circuit for generating an independent timepiece signal for each sampling circuit. According to another aspect of the present invention, a feedback technique for a regulator circuit that overcomes the above-mentioned difficulties is disclosed. The feedback technology described here uses the output of the low-voltage modulator to compensate for the delay caused by subsequent power and filter stages. At the same time, even if the signal content is different as described above, a high level of fidelity can still be obtained. By filtering the output of the modulator stage so that its frequency components outside the useful loop frequency range are transmitted to the feedback path, and its frequency components within the useful loop range are attenuated , The invention can achieve this result. Therefore, the stability of the loop will be improved by feedback from some parts of the modulator output, and the fidelity of the output frequency of the loop will not be adversely affected by the unwanted output components of the modulator in this range. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The attenuation and transmission frequency of the feedback filter of the present invention will vary depending on the type of modulator. For example, for baseband modulators, filters such as high-pass filters attenuate frequencies in the baseband and transmit higher frequencies. For a band-pass modulator, the feedback filter may behave like a notch filter, attenuating frequencies in the relevant frequency band. Similarly, the filter behaves like a band-pass filter to a band-elimination modulator, and to a low-pass filter to a high-pass modulator. 11-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 502494 A7 B7 V. Description of the invention (9) (Please read the precautions on the back before filling this page) The delay of 2 50 0 ns is allowed Adding the feedback technology described herein to the modulator circuit without the improvement of the present invention shows that the delay tolerance is increased to more than 500 ns. This means that according to the present invention, even if very large power devices have disturbing delays, these power devices can still be used in low voltage modulators. For example, certain embodiments of the present invention are capable of delivering power greater than 1,000 W (> lhp!) To a load of 40 hm with very high fidelity. For a load of 10hm (for example, an industrial monitor), this is equivalent to more than 5 hp! This is a significant improvement over the currently available high-fidelity modulator circuits and is sufficient for Many fairly high power industrial applications. Accordingly, the present invention provides a modulator circuit having an associated band-pass frequency range and including a switching stage having an associated first delay. The modulator circuit also includes a modulator stage with a feedback input. The output of the modulator stage is coupled to the input of the switching stage. The first feedback path is coupled between the output of the switching stage and the modulator stage. A notch filter corresponding to the band-pass frequency range is coupled between the output of the modulator stage and the feedback input of the modulator stage to compensate for the first delay. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. With reference to the rest of the manual and the drawings, you can further understand the nature and advantages of the present invention. Brief description of the figure Figure 1 is a simplified diagram of a noise spectrum shaping amplifier. Figure 2 is a simplified block diagram of the modulator circuit. FIG. 3 shows the second waveform of the modulator circuit from FIG. 2. This paper size applies to Chinese National Standard (CNS) A4 (210 X; 297 mm) -12- 502494 Printed by Annex I (A) of the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, No. 90105026, Profit Application Application Order Description Revised page A7 was presented in May ----- "Fill in Figure 4 is a block diagram of a cellular phone designed according to a specific embodiment of the present invention. FIG. 5 is a circuit diagram of a digital r f power amplifier designed according to a specific embodiment of the present invention. FIG. 6 is a schematic diagram of a digital R JP power amplifier designed according to another embodiment of the present invention. Fig. 7 contains Figs. 7A, 7B, and 7C, which are more detailed diagrams of the output stages of an RF amplifier designed according to a particular embodiment of the present invention. Figure 8a is a waveform sequence illustrating a specific embodiment of the invention. Fig. 8b is a simplified diagram of a possible implementation of a gate driving circuit for the present invention. Fig. 9a is a simplified diagram of another specific embodiment of the present invention. Fig. 9b is a timing diagram illustrating the operation of the embodiment of Fig. 9a. Fig. 9c is a simplified diagram of a possible implementation of the gate driving circuit for the embodiment of Fig. 9a. Fig. 10 shows a clock generation circuit designed according to a specific embodiment of the present invention. Figure 11 shows the second noise spectrum shaping amplifier. Figure 12 is a block diagram of a modulator circuit designed in accordance with a particular embodiment of the invention. Figure 13 is a block diagram of a modulator circuit designed in accordance with a more specific embodiment of the invention. Figure 14 is a block diagram of a modulator circuit designed in accordance with yet a more specific embodiment of the invention. This paper size applies to China National Standard (CNS) A4 specification (210X297). 5. Description of invention (1〇) BJuly (please read the precautions on the back before filling this page) -13- 502494 A7 B7 5. Invention Explanation (11) FIG. 15 is a block diagram of a modulator circuit designed according to yet a more specific embodiment of the invention. (Please read the notes on the back before filling out this page) Figure 16 is a block diagram of a general embodiment of a modulator circuit designed according to the invention. Figure 17 is a block diagram of a bandpass amplifier designed in accordance with a particular embodiment of the invention. Comparison table of main components 1 0 0 RF bandpass noise spectrum shaping amplifier 1 0 2 Frequency selection network 1 0 4 A / D converter 1 0 6 Gate driver circuit 1 0 8 Field effect transistor 1 1 0 Field effect Transistor 1 1 2 Feedback path 1 1 4 Matching network 1 1 6 Antenna 1 1 8 Inductor 2 0 0 Modulator loop 2 0 2 Modulator 2 0 4 Inverting power stage 2 0 6 Output filter 2 0 8 Feedback resistor 2 10 Capacitor printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210X297 mm) -14- 502494 A7 B7 V. Description of the invention (12) 2 1 2 Attenuation resistor 4 1 0 Cellular phone 4 1 2 Radio frequency 4 1 4 Modulation and demodulation zone 4 1 6 Controller 1 ¾ 4 1 8 Dual multiplexer 4 2 0 Antenna 4 3 0 IF to RF mixer its frequency converter 4 3 2 Matching network 4 3 4 Power amplifier 4 3 6 Matching network 4 4 〇 Matching network 4 4 2 LNA amplifier 4 4 4 Matching network 4 4 6 RF to IF mixed ifcs frequency converter 5 5 〇C frequency network (Please read the precautions on the back before filling out this page) Order the 552 analog to digital converter printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 5 4 output stage 556 feedback loop 558 digital signal 600 RF bandpass noise spectrum shaping amplifier 602 frequency selection network 604a A / D converter 604b A / D converter This paper size applies to China National Standard (CNS) A4 specification (210X297 (Mm) -15- 502494 A7 B7 V. Description of the invention (13) 6 0 6 a Gate driver circuit 606b Gate driver circuit (please read the precautions on the back before filling this page) 608a Field effect transistor 608b Field effect Transistor 610a Field Effect Transistor 610b Field Effect Transistor 611 Resonator Circuit 611a Resonator Circuit 6 12 Feedback Path 6 1 3 Adder 614 Matching Network 6 16 Antenna 902 Floating Switch 9 0 4 Switch 1002 Comparator 1004 Compare 1006 Ring oscillator 1008 Multiplexer Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperative 1100 RF amplifier 1102 Frequency selection network 1104a A / D converter 1104b A / D converter 1106a Pole drive circuit 1106b Gate drive circuit This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) -16- 502494 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (14) Effect transistor 1108b Field effect transistor 1110a Field effect transistor 1110b Field effect transistor 1111 Resonator circuit 1111a Resonator circuit 1112 Feedback path 1113 Adder 1114 Matching network 1116 Antenna 1200 Modulator circuit 1202 Modulator stage 1204 Switch Stage 1206 output filter 1208 feedback filter 1210 total joint 1300 baseband frequency band modulator circuit 1302 modulator 1304 switching stage 1306 output filter 1308 filter capacitor 1310 series resistor 1312 resistor 1314 resistor (please first Read the notes on the reverse side and fill in this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) -17- 502494 A7 B7 V. Description of invention (15) Printed by the Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 1 4 〇 0 fundamental frequency band modulator circuit 1 4 〇 2 modulator 1 4 〇 4 switching stage 1 4 〇6 Output filter 1 4 0 8 Filter capacitor 1 4 1 0 Series resistor 1 4 1 2 Resistor 1 4 1 4 Resistor 1 4 1 6 Capacitor 1 5 0 〇 Modulator circuit 1 5 0 2 S Tianm transformer 1 5 〇4 switching stage 1 5 〇6 output filter 1 5 〇8 filter capacitor 1 5 1 0 series resistor 1 5 1 2 resistor 1 5 1 4 resistor 1 5 1 6 capacitor 1 5 2 0 Resistor 1 5 2 2 Capacitor 1 6 〇〇 Mita delta cycle converter circuit 1 6 0 2 Modulator 1 6 〇 4 Switching stage 1 6 0 6 Output filter stage (Please read the precautions on the back first (Fill in this page again) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -18- 502494 A7 B7 V. Description of the invention (16) 1 6 0 8 4-port network 1610 gain control (please read first Note on the back, please fill out this page again) 1700 RF Band Pass Noise Spectrum Shaping Amplifier 1702 Frequency Select Network 1704 A / D Converter 1706 Gate Driver Circuit 1708 Field Effect Transistor 1710 Field Effect Transistor 17 1 2 Feedback path 1714 Matching network 1716 Antenna 1718 Feedback path 1720 The specific embodiment of the notch filter is described in detail with reference to Figure 4 printed by the Intellectual Property Bureau of the Ministry of Economic Affairs 8 Industrial Cooperative Cooperative, which shows a cellular phone 4 1 designed according to the present invention. Simplified block diagram. Cellular phone 4 1 0 includes RF area 412, modulation and demodulation area 414, including DSP, RAM, user interface, baseband circuits to generate baseband signals, and other standard circuits used in cellular phones Controller area 4 1 6 、 Duplexer or T / R switch 4 1 8 (The duplexer switch is used for the cellular phone that sends and receives at the same time, and the T / R switch is used for the interleaved sending and receiving. Cell phone), and antenna 4 2 0. During transmission, the baseband circuit in the controller 416 is responsible for generating the baseband signal. The baseband I paper size is suitable for Guanjia County (CNS) A4 specification (21Gx297 public attack) -19-502494 A7 B7 V. Description of the invention (17 ) (Please read the notes on the back before filling out this page) The signal is typically a bit string representing the information to be sent. Then, the baseband signal is modulated with an IF modulation signal in the box 4 1 4 and then provided to the R F area 4 1 2. Since the functions of the modulation and demodulation area 4 1 4, the controller 416, the duplexer / T / R switch 418 and the antenna 420 are well known in this technology, they will not be described in detail here. RF area 412 contains IF to RF mixer 430, matching network (MN) 4 3 2. Power amplifier (PA) 434 to amplify RF signals, and another matching network (MN) 436, mixer 4 3 0 is used to generate an RF signal by using a modulated signal received from the controller 4 1 6 via the modulator 4 1 4 (for example, 9 0 0 MHz). During transmission, the amplifier 434 will generate an RF signal and provide it to the antenna 4 2 0 via the matching network 4 3 6 and the duplexer / T / R switch 4 1 8. On the receiving side, RF zone 4 1 2 contains matching network 440, LNA amplifier 442, another matching network 444, r F to IF mixer 4 4 6 and matching network 4 4 0 is used to receive antenna 4 RF signal received at 20 (for example, 980 Μ Η z) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the RF to IF mixer will mix the RF signal into the IF range, and then provide it to Demodulator in block 4 1 4. The demodulator 4 1 4 will demodulate the transmitted baseband information and provide it to the controller 4 1 6. Since mixer circuits 430 and 446, LNA 442, and matching networks 432, 440, and 444 are all known, they will not be described in detail here. Referring to Fig. 5, there is shown a digital RF power amplifier 4 3 4 designed in accordance with a particular embodiment of the present invention. According to different specific embodiments, the Chinese National Standard (CNS) A4 specification (21 ×: 297 mm) can be applied according to the paper size. -20-502494 A7 B7 V. Description of the invention (18) According to 1989 7 The technology disclosed in US Patent No. 5,7 7 7, 5 1 2 issued on the 7th of July, "METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING", designed the amplifier 4 3 4. The amplifier 4 3 4 includes a frequency selective network 5 5 0 with a high Q 値 at the required transmission frequency, an analog to digital converter (A / D) 552, an output stage 554, and a feedback circuit 556, a feedback circuit 5 5 6 series. Provide continuous time feedback signal from output stage 5 54 to frequency selective network 5 50. The A / D converter 5 5 2 samples the output of the frequency selective network 5 5 0 and generates a digital signal 558 that is provided to the output stage 5 5 4. In one embodiment, the A / D converter 552 is a comparator, which samples at a frequency of 3.6 GHz to be applied to an application that requires a transmission frequency of 900 MHz. In other possible embodiments, for the transmission of a 900 MHz signal, the sampling frequency (f s) ranges from a minimum of 1.8 GHz to 3.6 GHz or higher. According to one such possible embodiment, the A / D converter 5 5 2 is an untimed comparator (that is, is ~) connected in series with the delay line, which basically operates like a Schmitt trigger. Generally speaking, the sampling frequency (Fs) is preferably at least twice the required transmission frequency. One possible implementation of the output stage 5 5 4 includes two transistors T 1 and D 2, inductors LI, L 2 and L 3, capacitors Cl, C 2 and C 3. And the pre-driver D. The pre-driver D is used to buffer the signal 5 5 8 and provide the signal 5 5 8 and its complementary power supply transistor T 1 and the gate of the transistor T 2 respectively. The drain of T 1 is coupled to V cc, and the source is coupled to node A. Capacitor C 1 is typically located at the source of transistor T 1 and this paper is again compatible with China National Standard (CNS) A4 (210X297 mm) (Please read the back (Please fill in this page again)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -21-502494 Α7 Β7 V. Description of the invention (19) (Please read the precautions on the back before filling this page) Parasitic capacitor between the drains. The drain of T 2 is coupled to node B, and the source is coupled to ground. Capacitor C 2 is typically a parasitic capacitor between the source and the drain of transistor T 2. Inductor L 1 is coupled between node A and node B, and inductors L 2 and L 3 are coupled between capacitor C 3 and node A, respectively. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs During operation, the digital signal 5 5 8 generated by the A / D converter 552 will switch between high and low based on the information being sent. Since the signal 5 5 8 and its complement are provided to the gates of the transistors T 1 and T 2 respectively, one transistor is always disconnected and the other is closed depending on the state of the signal 5 5 8. For example, when the signal 5 5 8 goes low, T 1 is closed and T 2 is open. When this occurs, the source node A will resonate due to the formation of a resonance circuit in the output stage 5 54. This resonant circuit is formed by c 1, three inductors LI, L2, and L3, and node B which is pulled to ground via T2. The driver circuit 5 5 4 thus implemented contains two separate resonances at nodes A and B. Depending on the state of the signal 5 5 8, one node resonates and the other node is clamped. In one embodiment, the resonance is transformed into a resonance at a sampling frequency of 3 · 6 G Η z. This can be achieved by appropriately selecting the inductors LI, L2, and L3, and 电容器 of the capacitors Cl, C2, and 03. According to a particular embodiment, C 3 is selected to pass the R F frequency. The output of the switching stage 5 5 4 is provided to the matching network 4 3 6, which is used as a band-pass sprinkler operating in the transmission band. Since in the above embodiment, the antenna 420 is transmitted at 900 MHz, the "tracking" function of the matching network 4 36 needs to conform to this frequency. In the actual paper size, the Chinese National Standard (CNS) A4 specification (210X297 mm) -22-502494 A7 B7 V. Description of the invention (20) (Please read the precautions on the back before filling this page) In the example, This is achieved by selecting L1, L2, and L3, and C3, so that the resonant circuit has a conversion function of approximately 900MHz into the matching network 4 3 6 so that T 1 and T 2 The resulting output bit pattern has an energy component located at 900 MHz. In other words, the matching network 4 3 6 must provide sufficient gain to ensure that the bit pattern has an ohmic level (typically 50 ohms) for the antenna with sufficient energy at 900 MHz. In another embodiment, the matching network 4 3 6 uses wiring on a chip containing a power amplifier 4 3 4 and other passive components to generate a matching network to provide the best power conversion to the antenna 4 2 0 and the antenna's ohms値 is converted into an impedance that can obtain the required power level from a given supply voltage. This will require a fairly high Q 値 filter with a fairly narrow bandwidth. In yet another embodiment, the power amplifier 4 3 4 is designed to have a bridged output. In applications where the antenna 4 2 0 has a single-ended output, a balanced-unbalanced converter or a passive LC mixer can be used. Fig. 6 shows another RF band pass designed by the present invention and the technology described in the above-mentioned U.S. Patent No. 5,777,512, which is printed by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and a printed spectrum shaping amplifier 600. As will be explained, the RF amplifier 600 is configured to perform multi-level switching. The RF amplifier 600 includes a frequency-selective network 602, which uses continuous time feedback to apply a modulated R F input to a noise spectrum shaping. According to a particular embodiment, the network 600 includes at least one resonator stage having a transfer function designed to pass a frequency band centered at 900 MHz. The two A / D converters 6 0 4 a and 6 0 4 b will use the rated sampling frequency. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -23- 502494

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (21) The rate f S (ie, fsi and fs 2), using an independently generated timepiece signal, will pass through the noise signal that is shaped by the noise spectrum. In a specific embodiment, the nominal sampling frequency f sm3 _ 6eHZ. According to the embodiment, the A / D converters 604a and 6o4b include two comparators for implementing three-level switching. The squeegee driving circuit 6 0 6 a and 6 0 6 b will obtain the pulse train from the A / D converters 60 4 a and 6 0 4 b, respectively, and generate a pair of transistors for the transistor (ie, FET 608a and 6). 〇3 or 1?] 2 丁 6 0 8 b and 6 1 〇 b) gate drive. Each pair of transistors has two resonances due to the resonator circuits 6 1 1 and 6 1 a respectively. That is, the power stages including F E T 6 0 8 and 6 1 Q have respective resonances at nodes a and B, and the stages including FETs 608a and 610a have respective resonances at nodes A 'and B'. The continuous time feedback is provided to the frequency selection network 6 0 2 via the feedback path 6 1 2 and the adder. The output signal of the power stage will be sent to the matching network 6 1 4 and the matching network 6 1 4 will send the output RF signal to the antenna 6 1 6 for transmission. Having two comparators for converters 604a and 604b will allow digital signals to have three quantization states, that is, three-level switching, rather than two-level switching. For example, depending on the two-level quantization state of the amplifier 4 3 4, there may be many signal transitions that cause high drive losses. In contrast, according to the three states, when there is no signal output to avoid this unnecessary switching loss, the state of "0" can be selected. Figure 7 includes Figures 7A, 7B, and 7C, which are detailed diagrams showing switching levels, according to a specific implementation of the present invention. National Standard (CNS) A4 Specification (210x297 mm) ---------% II (Please read the notes on the back before filling this page) Order • Γ.  -24- 502494 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (22 〇 1 1 example, which can be used by the RF amplifier of Figure 6). However, it should be understood that it does not depart from the scope of invention The switching stage of Figure 7 below and the switching stage of the amplifier 1 I of Figures 5 and 6 can be used in different amplifier types. That is, the ^ -V of the present invention. 1 1 The configuration of the switching stage is applicable outside the RF range. Many applications. Read first. 1 1 Although the present invention is described by using a cellular phone application, it should be understood on the back 1 that the invention can be implemented with a wide range of connotations and other embodiments. Note that the RF of the invention The amplifier can be used in a cellular telephone base station or any other application that requires an efficient RF amplifier. 1 The digital amplifier of the present invention • The I amplifier can also be used such as 1 • 8 G Η Z or 3 • 0 G Η Z or higher frequency page 1 1 RF transmission. In this itb embodiment, a higher transmission rate can be achieved by increasing the sampling rate (f S) according to the above ratio 1 1. Transistors T 1 and 1 IT 2 can also be a & different type of device, including Μ ESF Ε 丁 定 I Η BT CM 〇S, or N Μ 〇S and can be made by some different processes 1 1 I and materials (including G a AS, S i Ge or standard silicon) is made 〇 Because 1 1 Therefore, you can understand that the embodiment provided here is only an example, the true scope of the invention 1 | The positive scope and spirit should be determined by the scope of the patent claim 0 # 1 According to a specific embodiment The gate driving circuit 10 6 of the noise spectrum shaping amplifier of FIG. 1 operates in accordance with the principles of the present invention. Referring to FIG. 8 a shows the rising and falling edges of the gate signal for one of the 1 1 FETs. At this point, the gate signal 8 0 2 is a gate driving circuit 1 0 6 and the signal 1 I Drfe · Wl 8 0 4 is located at the gate of the FET. 0 The signal 8 0 4 shown is used for either or both of the 1 1 IFET 10 8 and 1 1 0. One of them is basically 1 1 The complement of the other 0 is used for the gate drive circuit 1 0 6 One possible implementation system 1 1 is shown in Figure 8b 〇 But it should be understood that it does not depart from the scope of the invention 1 1 1 This paper scale applies to China National Standard (CNS) A4 Specification (210X297mm) -25- 502494 A7 B7 V. Description of Invention (23) In this embodiment and other embodiments described herein, a variety of driving circuits can be used. (Please read the notes on the back before filling this page) According to an embodiment, just enough energy is introduced into the resonance at the gate of the FET, so that the signal at the gate 8 0 4 will be at the required input logic bit quasi. The width of the initial pulse used for each logic transition in the gate signal 802 determines this energy and is controlled by the gate drive circuit 106. That is, the gate driving circuit 106 is used to receive the pulse train 8 0 6 from the A / D converter 104 (for example, it can be a comparator) and generate a gate signal. Each positive and negative transition of the pulse train of the D converter 104 corresponds to the corresponding transition sequence shown in Fig. 8a. Therefore, for the transition from the logic “0” to the logic “1” of the signal 8 0 6, the gate driving circuit 10 6 will generate in the signal 8 0 2 and cause the signal 8 0 4 to be at the beginning of the width W 1 of the logic 1 pulse. Then, before the next transition of the signal 8 0 · at a later point, the signal 8 2 is brought to a high level again (ie, the third transition). At this point, a similar sequence of transitions takes place to bring the transition to logic "0". As you can see, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, this will not only prevent resonance from oscillating, but also solve the problem of overshoot / downshoot. Since some resistors are connected in series with the input of each FET, the width W of each initial transition pulse in the signal 802 needs to be wide enough to overcome the attenuation factor introduced by this resistor. Otherwise, the level of signal 804 will never reach the required logic level. On the other hand, it is also desirable that the width W is not too wide to avoid significant overshoot or oscillation. Therefore, according to a specific embodiment of the present invention, adaptive feedback control can be provided, which will supervise the signal 8 0 4 ^ Paper size applies Chinese National Standard (CNS) A4 specification (210X29? Mm) ~ -26-502494 A7 B7 5 Explanation of the invention (24) To the extent that the required logic level is reached or overcome, and use this information to adjust the timing of the transition pulse of the signal 8 0 2 through the gate drive circuit 1 06. (Please read the note on the back first Please fill in this page again) According to another specific embodiment, the adaptive loop includes at least one comparator for measuring whether the signal level at the gate of the FET is too high or too low, and using a DAC to adjust the gate driving circuit 1 〇 The bias current of the one or more delay lines adjusts the timing of the transition pulse of the signal 802 to correct the excess or deficiency. According to different embodiments, states 2a and 2b can be achieved by closing the driving circuit. Inductor current will be provided for transitions 2a, 2b, 3a and printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3b. This means that the timing of the third transition in signal 8 0 2 for each transition of signal 8 0 6 (for example, transitions 3 a and 3 b) is not critical to the success of the technology. That is, since the gate inductor naturally pushes the gate voltage to the desired state and the parasitic diode from the drain to the source of each pole driving device will temporarily clamp the gate driving voltage (also That is, the signal 802), so the gate voltages of the FETs 108 and 110 naturally transition to a desired state. That is, when the energy in the gate resonance of the circuit decays, the gate voltage naturally decays to the required level. In other words, the timing of the third transition of the signal 8 02 (for example, transitions 3 a and 3 b) need not be a key parameter. It should also be noted that the pulse width in the signal 802 need not be controlled so that the gate signal 804 will settle to the required logic level without oscillation. That is, an embodiment that allows a small amount of excess and resonance oscillations can be considered. Although these embodiments are not as optimal as the above-mentioned embodiments, the Chinese paper standard (CNS) A4 specification (210X297 mm) can still be applied from the paper size. -27- 502494 A7 B7 V. Description of the invention (25 ) The technology of the invention is profitable. For example, resonance oscillations can be limited to only a few (to some extent) periods. Another specific embodiment of the invention is shown in Fig. 9a. The simplified diagram shown shows the general applicability of the technology. The operation of the circuit of Fig. 9a will be explained with reference to Fig. 9b. In this embodiment, a floating changeover switch 902 and an inductor L 1 are used to switch the gate capacitance C g of the changeover switch 904 to a desired level. The driving signal is represented by another capacitor C1, and the energy will be exchanged between the two capacitors without overshoot. According to a specific embodiment of a circuit manufactured using CMOS technology, a back-to-back nMOS and pMOS device as shown in FIG. 9C may be used to implement a floating changeover switch 902. According to this embodiment, simply by closing, and then opening the switch 902 at an appropriate time, the required logic level can be obtained at the node B. As shown in Figure 9b, when the switch 9 0 2 is closed at t 1, the voltage at node A, that is, 3 volts, will begin to decay and pass the inductor L 1 to reduce the voltage at node B (that is, , The voltage across the gate capacitance C g). Then, at an appropriate time t 2, the switch 9 0 2 is turned off again to ensure that the node B reaches the required level. The appropriate time t 2 when the switch 9 0 2 is turned off is the time when the nodes A and B reach the staggered peaks. The ratio of c g and C 1 will affect the signal swing of nodes A and B. Also as described above, similar techniques can be used to adaptively determine the ratio of C 1 to C g and the initial charge of C 1. In addition, use a toggle switch that connects Node B to high or low (for example, 3 or 0 volts) at the appropriate time to "truncate the top" of the voltage level of Node B. For example, this technology can be used to attenuate and switch. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page. J-Order-Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative -28- 502494 A7 _ B7 V. Attenuation effect of series resistance related to invention description (26) 9 0 2. In addition, by appropriately shifting individual 値 of C 1 and C g, the switching can be overcome The resistive attenuation introduced by the switch 9 0 2. That is, C 1 can be made sufficiently larger than C g to shift the amplitude of the resonance, thereby overcoming the attenuation caused by the switching switch 9 0 2. Although the invention is disclosed with reference to a specific embodiment However, it should be understood that the techniques described herein can be applied to a wider range of applications than some of the applications described here. For example, Figure 1 shows a bandpass embodiment of the present invention, for example, for the hive Amplifiers in conventional telephone technology. However, the present invention is obviously applicable to other types of amplifiers, for example, baseband audio amplifiers. Therefore, the scope of the present invention should not be limited to the embodiments described herein. Instead, it should be determined by the scope of the patent application. A specific embodiment of the present invention will now be described with reference to Figs. 1 and 10. That is, the circuit of Fig. 10 is used with the amplifier of Fig. 1 to implement the timepiece described herein Implementation of generation technology. According to a specific embodiment of the invention, a timepiece (ie, fs) for A / D converter 104 is generated from at least one resonance at nodes A and B. According to a more specific embodiment, is is provided in part by the resonance at node A and part is provided by the resonance at node B. Figure 10 shows one implementation that can accomplish this. Comparator 1 0 2 will apply the voltage at node A (Ie, V a) compared to the voltage of the positive power supply (preferably ground) which is less than the power output stage. When node A resonates above and below ground at 3 · 6 GHz, it generates 3 · 6 G 产生z timepiece. Similarly, the comparator 1004 compares the voltage at the node B (that is, V β) with the voltage above the ground (or negative trajectory), preferably with a positive power source, so that when When Node B resonates, the paper size of the production paper applies to the Chinese National Standard (CNS) Α4. (210 × 297 mm) (Please read the notes on the back before filling this page) Order printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 29 · 502494 A7 B7 V. Invention Description (27) (Please read the notes on the back before (Fill in this page) is a 3 · 6GHz timepiece. The multiplier 1 008 selects between its inputs in response to the control signal generated by the control logic (not shown). According to a specific embodiment, the control logic is determined by the comparator The decision of 104. In this way, the multiplier 1008 generates a time signal fs. When the circuit is first disconnected, the time signal can be started by generating a pulse that causes one of the resonances to proceed. According to an embodiment, this can be done by a multiplier 1008 that selects the ring oscillator 1006. One of the favorable results of the timepiece generation technology is that the timepiece is generated at least in part by the resonances at nodes A and B. Therefore, when these resonances move up and down (for example, due to reflection and processing variation), the The comparator timepiece moves up and down in a corresponding manner. That is, the gate edges generated by the A / D converter 104 and the gate driving circuit 106 will more closely match the timing of the output stage resonances than when the A / D timepiece generated independently is used. This will allow the switching edges to align better with resonance for increased efficiency. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In addition, the pattern-dependent chattering on the A / D converter timepiece caused by the resonance moving up and down will effectively scramble the sampling ratio and disturb the sampling frequency dependent tone into random noise. To eliminate unwanted harmonics related to the sampling frequency in the output power spectrum. In fact, according to the present invention, the "high frequency vibration" of A / D converter timepieces has nothing to do with how the timepieces are generated (for example, has nothing to do with self-timing) and is intentionally introduced in a controlled manner to disrupt Noise tones at the sampling frequency. Referring again to Fig. 10 and according to a more specific embodiment of the invention, a ring oscillator 1 0 6 may also be included in the timepiece generating circuit as an added timepiece signal source. Because the attenuation resistance related to the output resonance circuit may be high enough for this paper size to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) -30- 502494 A 7 B7 V. Description of the invention (28) (Please read the first Note that you need to fill in this page again) This causes the resonance oscillations to decay sufficiently that they no longer touch the comparators 1 0 2 and 1 0 4 and the timepiece (hence the gate signal) is locked, so this point is needed. Therefore, after generating some pulses from one of the resonance nodes (possibly determined from the attenuation resistance associated with the resonance circuit of the output stage), the multiplexer 1008 is controlled to select the input from the ring oscillator as the timepiece signal until the other Resonance at one node begins. According to a specific embodiment, the ring oscillator is started and stopped in synchronization with the resonance oscillation, so that the handover between the timepiece sources is smooth. Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. According to certain embodiments, the technology described here is used to enhance the multi-level switching invention described in the corresponding application of the above reference to provide self-generated timepieces to multiple independent timepieces. Each A / D converter in the A / D converter. A specific embodiment of this embodiment will now be described with reference to FIG. 11. FIG. 11 shows an RF bandpass noise spectrum shaping amplifier 1 1OO, which is also based on US Patent No. 5,777, which is incorporated herein by reference. 5 The technical design disclosed in 12. The R F amplifier 1 1 0 0 includes a frequency selective network 1 102, which uses continuous time feedback to apply a modulated r f input to a noise spectrum integer. According to a specific embodiment, the network 1 102 includes at least one resonator, which is a transfer function designed to pass a frequency band centered at 900 MHz. A A / D conversion benefit 1 1 〇 4 a and 1 1 〇 4 b will use the rated sampling frequency f S (ie f S 1 and f S 2), using the independently generated timepiece signal, will pass the noise spectrum frequency The integer RF signal is converted into digital data. According to a specific embodiment, the sampling frequency is 3 · 6 G Η z. According to an embodiment, the A / D converters 1104a and 1104b include the Chinese paper standard (CNS) A4 specification (210X297 mm) for this paper size -31 · 502494 A7 B7 V. Description of the invention (29) Implement a two-level quasi-switching two comparator. The gate drive circuits 1 1 〇6 a and 1 1 〇6 b will obtain the pulse train from A / (please read the precautions on the back before filling in this page) D converter 1 1 〇4 a and 1 1 〇4 b And generate gate drivers for their transistor pairs, namely FETs 1108a and 1110a or FETs 1108b and 1110b. Each pair of transistors has two resonances respectively due to the resonance circuits 1 1 1 1 and 1 1 1 1 a. That is, the power levels including FETs 1108 and 1110 have respective resonances at nodes A and B, and the levels including F E T 1 1 0 8 a and 1 1 1 0 a have respective resonances at nodes A 'and B. The continuous time feedback will pass through the feedback path 1 1 1 2 and the adder 1 1 1 3, and the fen is used to end the carrier frequency network 1 1 02. The output signal of the power stage will be sent to the matching network 1 1 1 4, and the matching network 1 1 1 4 will send the output RF signal to the antenna 1 1 1 6 for transmission. In another embodiment, the adder 1 1 1 3 is part of the matching network 1 1 1 4. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed two comparators for A / D converters 1104a and 1104b to allow digital data to have a three-quantity state, that is, three-level switching, not two-level . According to the binary state, there may be many signal transitions that cause high drive losses. In contrast, according to the three states, when there is no signal output to avoid this unnecessary switching loss, the state of "0" can be selected. The timepieces for the individual comparators 1 10 4 a and 1 104 b can be generated by independent light sources. According to a particular embodiment of the invention, the timepiece signal is generated independently according to the technology of the invention. That is, according to a specific embodiment of the invention, at least some resonances at the nodes A, B, A ', and B' will be generated to use the Chinese paper standard (CNS) A4 specification (210X297 mm) for this paper size -32- 502494 A7 B7 V. Description of the invention (30) (Please read the notes on the back before filling this page) At the time of A / D converter 1 1 04a and 1 1 〇4b (ie, fs 1 and fs 2) . According to a more specific embodiment, fs 1 is partly provided by resonance at node A and part is provided by resonance at node B, while fs 2 is partly provided by resonance at node A 'and partly by node b' The resonance provided here. Fig. 10 shows the implementation of one of the unfinished f 1 and f 2 generations. However, it will be appreciated that these timepiece signals can be generated in other ways. In addition to the randomization of switching frequency-dependent noise, there are other noise advantages due to the independent nature of the two-hour clock. This is related to the fact that the average timepiece frequencies f s 1 and f s 2 differ by some fairly constant amount, which is basically the smallest repeated sampling rate encountered by the amplifier. That is, the difference between i s 1 and f s 2 results in an "effective" sampling frequency that is much higher than f s 1 or f s 2. As a result, any undesired tones or "radiators" in the output noise spectrum will be shifted out of the useful band due to the very high "effective" sampling frequency. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to a specific embodiment, the difference between f s 1 and f s 2 is deliberately introduced and controlled to obtain the advantages of this effect. According to a more specific embodiment in which the timepieces f s 1 and is s 2 are generated from stable independent sources rather than resonance nodes, the difference between f s 1 and f s 2 can be controlled to achieve this advantage. Even in the case where f s 1 and f s 2 are derived from a single source, the differences will still be introduced to gain advantages and remain within the scope of the invention. Although the invention is specifically described with reference to specific embodiments of the invention, those skilled in the art should understand that the form and details of the disclosed embodiments may vary without departing from the spirit or scope of the invention. For example, only one of nodes A and B combined with the ring oscillator to generate the actual timepiece signal. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public envy) -33- 502494 A7 B7 V. Invention Note (31) (Please read the notes on the back before filling out this page). Since the gate pulses applied to the input of the power stage may not match the timing of other resonances, this embodiment may be less needed. However, this embodiment is clearly within the scope of the present invention. It should also be noted that although reference is made here to bandpass (for example, RF) implementations to illustrate the invention, the invention can also be applied to other amplifier configurations, such as baseband audio amplifiers. Therefore, the scope of the invention should be determined by the scope of the patent application. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 12 is a block diagram of a modulator circuit 1 2 0 0 according to a specific embodiment of the invention. The modulator stage 1 2 0 2 can be any of a wide range of modulators, including pulse width modulators, or such as disclosed in US Patent No. 5,7 7 7,5 1 2 Oversampling mixed signal modulator. According to a particular embodiment, the modulator stage 1 2 0 2 comprises a plurality of filters connected in parallel and / or in series. The switching stage 1 2 0 4 receives a control signal from the output of the modulator 1 2 0 2. The switching level 1 2 0 4 can be any of a variety of switching switch configurations and power levels. The switching stage 1 2 0 4 can also be inverted or non-inverted. For the inverting switching stage, the inverter is inserted into the modulator output feedback path before the feedback filter 1 2 0 8. The output filter 1 206 may also be implemented according to any of a variety of techniques suitable for the content of the desired output signal in a particular application. As in previous designs, negative feedback can be provided from the output of the switching stage 1 2 0 4 and / or the output filter 1 2 0 6 to the modulator 1 2 0 2 via the summation joint. To illustrate this, it is assumed that the connector 1 2 1 0 is ideal, and therefore, an added feedback circuit is not shown. However, it will be understood that a true circuit element such as a resistor must be used to implement the header 1 2 1 0. Because this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) • 34- 502494 A7 B7 V. Description of the invention (32) (Please read the precautions on the back before filling this page) This will be referenced below Figures 4 to 6 illustrate a particular embodiment of the invention showing some real embodiments of the joint joint 1210. The frequency content of the feedback from the switching stage and output filter is within and outside the frequency range of the useful loop. Unlike the old design, the modulator circuit 1 2 0 0 also uses the feedback from the output of the modulator 1 2 0 2 through the feedback filter 1 2 0 8 to further improve the loop stability. However, in order to avoid the unfavorable results of the output fidelity discussed in the background of the invention, this feedback is filtered by the filter 128, so that most of its frequency content is outside the useful modulator loop frequency range. As a result, stability is increased without loss of fidelity. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 13 is a block diagram of a baseband modulator circuit 1 300 according to a more specific embodiment of the invention. The modulator 1 3 0 2, the switching stage 1 3 0 4, and the output filter 1 3 0 6 actually operate in a manner similar to the corresponding loop element described above with reference to FIG. 12. The feedback is provided from the output of the switching stage 1 3 0 4 to the feedback input of the modulator 1 3 0 2 via a divider network including resistors 1 3 1 2 and 1 3 1 4. The feedback is also provided to the feedback input of the modulator 1 3 0 2 from its logic output via the filter capacitor 1 3 0 8 and the series resistor 1 3 1 0. The capacitor 1 3 0 8 is selected to attenuate the content of the logical output signal in the useful baseband range, and pass the higher frequency to the feedback path to combine with the attenuated switching level signal. With this configuration, the delay tolerance can be significantly increased. However, because the filtered logic signal of the modulator is not ideal, the Chinese paper standard (CNS) A4 (210 × 297) is used in this paper size. &Quot; 502494 A7 B7__ V. Description of the invention (33) (Please read the back first (Please note this page and fill in this page again) The combination of the filter and the feedback path of the ideal combiner, so the real circuit components (ie, capacitor 1308 and resistor 1310) will be introduced into the extra pole and zero-to-loop transfer function . Considering the logic output of the modulator 1 3 0 2 as ground and observing the capacitor 1 3 0 8 switches the output of the stage by low-pass filtering to add delay to the loop. This can be seen from the network analysis perspective. This delay represents a limit on the performance gain that can be caused by using a filtered modulator output as a feedback. Therefore, other embodiments of the invention will be described below, which enhance the loop of FIG. 13 to illustrate this limitation. Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 14 is a block diagram of a baseband modulator circuit 1400 designed according to yet another more specific embodiment of the invention. The modulator 1402, the switching stage 1 4 0 4 and the output filter 1 4 0 6 actually operate in a manner similar to the corresponding loop element described above with reference to FIG. 12. According to the corresponding component of the circuit 1 3 0 0, the feedback is provided from the output of the switching stage 1 4 0 4 to the modulator 1 4 0 2 via a divider network including resistors 1 4 1 2 and 1 4 1 4 Feedback input. The feedback is also provided to the feedback input of the modulator 1 402 from its logic output via the filter capacitor 14 0 8 and the series resistor 1 4 1 0. Capacitor 1 408 is selected to attenuate the content of the logic output signal in the useful baseband range and pass the higher frequencies to the feedback path to combine with the attenuated switching level signal. An additional capacitor 1416 is provided from the output of the switching stage 1 4 0 4 to node 1, which will cancel the pole of the feedback path of the capacitor 1408 leading into the switching stage. By looking at the logic output of the modulator 140 2 as ground again and analyzing the feedback path from the output of the switching stage 1 4 04, this point can be understood from the network analysis perspective. If the ratio of the resistors 1 4 1 2 and 1 4 1 4 is in accordance with the Chinese paper standard (CNS) A4 (210X297 mm) -36- 502494 A7 B7 V. Description of the invention (34) Example equal to capacitor 1 4 1 The ratio of 6 to 1 408, then the attenuation of the switching stage output seen at node] _ is the same as that seen at node 2, that is, the voltage levels should be the same. Since the voltages at nodes 1 and 2 are equal, no current flows through resistor 1 4 1 0. Therefore, resistor 1 4 1 0 can be considered as an open circuit, and capacitor 1 4 can be effectively removed from the switching stage feedback path. 0 8 and its corresponding pole. This will make the modulator circuit quite stable and allow delay. Figure 15 is a block diagram of a modulator circuit 1500 designed in accordance with yet a more specific embodiment of the invention. The modulator 1 502, the switching stage 1504, and the output filter 1 5 0 6 actually operate in a manner similar to the corresponding loop element described above with reference to FIG. 12. The resistors 1510, 1512 and 1514 and the capacitors 1508 and 1516 actually operate in a manner similar to the corresponding loop elements described above with reference to FIG. 14. In fact, the embodiment of FIG. 15 includes all the circuits of FIG. 14 plus the feedback path from the output filter 15 0 6 to the modulator stage 1 50 2. The added feedback path is a resistor 1 5 2 0 implementation. Capacitor 1 5 2 2 also contains the poles in the new feedback path introduced from the output of filter 1 5 0 6 to node 1 capacitor 1522, using cancellation capacitors 1508 and 1516. As described in the above embodiment with reference to FIG. 14, if the ratio of the resistor 15 2 0 to the resistor 1 5 1 2 of the parallel resistor 1 5 1 2 is the same as the capacitor 1 5 1 6 of the parallel capacitor 1 5 0 The ratio of 8 to the capacitor 1 5 2 2 means that no current flows into the resistor 1 5 1 0. Therefore, the capacitor 1 5 0 8 ° can be effectively removed from any feedback path. This paper standard applies to China National Standard (CNS) A4 Specifications (210X297 mm) (Please read the notes on the back before filling this page) Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-37- 502494 A7 B7 V. Description of the invention (milk) Please fill in this page again for details) Fig. 16 is a block diagram of a general embodiment of a modulator circuit 1660 designed according to the invention. It replaces the feedback filter and signal mixing circuit of the previously described embodiment with a 4-port network 1 6 0 8, a modulator stage 1 6 0 2, a switching stage 1 6 0 4, and an output filter stage 1 6 0 6 will connect to the 4-port network 1 6 0 8. The network 1608 will obtain the logic output signal of the modulator and attenuate its frequency content within the useful range of the modulator circuit 1600. It also combines the resulting signal with the switching and feedback output of the filter stage to serve as the feedback of the modulator stage 160. Depending on the technology used to implement the modulator circuit 160, the network 16 can be implemented in different ways. In addition, for modulators with amplitude-dependent stability (for example, oversampling and pulse width modulators), it may be necessary to control the amount of modulator feedback related to power and / or filter stage feedback To maintain the best stability point. Therefore, an optional gain control 16 10 is provided before the feedback filter (including the 4-port network 16 0 8) to allow the logic output signal of the modulator to match the gain of the power output. According to a specific embodiment, a digital-to-analog converter (DAC) with variable output amplitude is used for gain control 161 0. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Although the invention has been shown and explained with reference to specific embodiments of the invention, those skilled in the art should understand that the disclosed implementation does not depart from the spirit and scope of the invention. The form and details of the examples can be changed. For example, the specific embodiments described above with reference to FIGS. 13 and 14 show the use of analog components (for example, resistors and capacitors) at the output of filters and modulators, combined with the resulting filtered feedback signals and signals from The feedback path of the output of the switching stage. However, it should be understood that, for example, the use of several paper sizes at the modulator level applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -38- 502494 A7 B7 V. Description of the invention (36) (please first Read the notes on the back and fill in this page) In the case of digital technology implementation, the circuits and technologies used to filter and combine feedback signals can be digital. Similarly, feedback can be implemented through mixed signal modulators, mixed signal circuits, and technologies, such as the signal of the actual ground terminal of a hybrid operational amplifier. It should also be understood that whether the degree of change in the attenuation of the components of the modulator output in the range is appropriate depends on the content of the modulator and the degree of power output in the useful frequency range of the modulator loop, and the tolerable output of the loop Degree of deterioration. That is, it is not necessary to completely reject the frequency components in the output of the modulator stage in the useful loop frequency range in order to maintain reasonable fidelity and stay within the scope of the invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 17 shows the RF bandpass noise spectrum frequency shaping amplifier designed according to the present invention and the technology disclosed in US Patent No. 5,7 7 7,5 1 2. 7 0 0. By way of example, this amplifier can be used in, for example, radiotelephones, pagers, network devices, and so on. The r F amplifier 1700 includes a frequency selective network 1702. The frequency selective network 1702 uses continuous time feedback to apply the modulated R F input to a noise spectral frequency integer. According to a particular embodiment, the network 170 includes at least one resonator stage having a transfer function designed to pass through a frequency band centered at 900 MHz. Of course, it should be understood that the bandpass frequency range of the noise spectral frequency integer amplifier designed according to the invention will range from 1.  Any one of a plurality of frequencies such as 8 G Η ζ, 2.4 GHz, etc. is centered, and the present invention is not limited to any specific range or range group. The A / D converter 1 7 0 4 will use the sampling frequency fs to convert the RF signal that has undergone noise spectrum shaping into digital data. According to the specific implementation, this paper standard applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -39-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 502494 A7 B7 V. Description of the Invention (37) For example, the sampling frequency fs is 3 · 6 G Η z. According to an embodiment, the A / D converter 170 4 includes a comparator. The gate drive circuit 17 0 6 will take the pulse train from the A / D converter 17 0 4 and generate a power output stage for each of the amplifier 1 7 0 — gates of FET 1 7 0 8 and 1 7 1 0 Extremely driven. The output power level shown includes the electric idlers LI, L2, and L3, and the capacitor C1. When the corresponding one of the FETs 1708 and 1710 is closed, this configuration generates two separate resonances at nodes A and B, respectively. Through the feedback path 1 7 1 2, continuous time feedback is provided to the frequency selection network 1 7 2. The output signal of the power level will be sent to the matching network 1 7 1 4 and the matching network 1 7 1 4 will send the output RF signal to the antenna 1 7 1 6 for transmission. As will be understood and in accordance with the present invention, the feedback path 1 7 1 2 may originate within the matching network 1 7 1 4. The loop type of the amplifier 1700 is typically optimally operated with a loop delay equal to 1 / f s (ie, 1/3 · 6GHz). In order to compensate for any increase and unwanted delay related to the output power level, the amplifier 17 0 0 includes another feedback path 1718 to the frequency selective network 1 7 2. The frequency selective network 1702 includes The notch filter at the same center point 1 7 2 0. The source of the feedback is shown as the output of the A / D converter 704. However, it will be understood that there are several other points between this node and the input to the power stage from the feedback source. Therefore, the scope of the invention should not be limited to the embodiments shown. Rather, as with all embodiments described herein, the scope of the present invention should be construed in terms of the scope of the following patent applications. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page), 11 -40-502494 A7 B7 V. Description of invention (38) The application explains the present invention, but it is obvious that the invention can be implemented in various contents and other embodiments. For example, the RF amplifier of the present invention can be used in a cellular telephone base station or any other application requiring an efficient RF amplifier. The digital amplifier of the present invention can also be used such as 1, 8GHz or 3. RF transmission at 0 GHz or higher. In these embodiments, by increasing the sampling frequency (f s) according to the above ratio, a higher transmission rate can be achieved. It will also be understood that the use of the amplifier configuration and output switching stage of the present invention is not limited to RF applications. Transistors T1 and T2 can also be some different types of devices, including MESFET, HBT, CMOS, or NMOS, and can be made of different processes and materials (including GaAs, SiGe, or standard silicon). Therefore, it can be understood that the embodiments provided herein are merely examples, and the true scope and spirit of the invention should be determined by the scope of patent application. (Please read the notes on the back before filling out this page) Order Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 41-

Claims (1)

502494 A8 B8 C8 D8 f 丨 Year 7: Repairing printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. Scope of patent application. Annex II (A): No. 90105026 Patent Application. Chinese Application for Patent Scope Amendment. Month correction 1 · A band-pass amplifier including: a frequency-selective network in a feedback loop; an analog-to-digital converter coupled to a frequency-selective network; a switching stage coupled to an analog-to-digital converter for continuous time output The signal, the switching stage includes at least one resonance circuit, the at least one resonance circuit resonates at a resonance frequency, thereby generating at least part of a continuous-time output signal; and a continuous-time feedback path for continuously sensing the continuous-time output signal to and continuously The time output signal is fed back to the frequency selection network. 2 . For example, the band-pass amplifier of the first patent application range, wherein the switching stage includes first and second switching switches in a half-bridge configuration, and the first and second switching switches have parasitic capacitance associated with them, and the switching stage includes multiple inductors. Device, the at least one resonance circuit includes a total of two parasitic capacitors and inductors.  The vibrating circuit and the two resonance circuits resonate alternately at a resonance frequency. 3. If the band-pass amplifier of item 2 of the patent application, both of the resonance circuits have resonance nodes associated with them, and both resonance circuits resonate at the resonance frequency. 4. The band-pass amplifier according to item 3 of the patent application, wherein one of the resonance nodes is located at the source terminal of the first switch and the other resonance node is located at the drain terminal of the second switch. This paper is also applicable to China National Standard (CNS) 8-4 specification (210X297 mm)-nn I n ^ n I ~ (Please read the precautions on the back before filling this page) 502494 A8 B8 C8 D8 ---------% 1- (Please read the notes on the back before filling this page) 5. For example, the band-pass amplifier of the first scope of the patent application, wherein the analog-to-digital converter includes two comparators for implementing three-level quasi-switching, and the middle switching stage includes the first and second switching switches of the first half-bridge configuration, And the second half-bridge is provided with third and fourth switching switches, and the first and second half-bridges are provided with two resonance circuits associated therewith. The two resonance circuits resonate at a resonance frequency. 6 · A radio frequency communication system, including a band-pass amplifier, the band-pass amplifier includes = a frequency-selective network in the feedback loop; an analog log-to-digital converter coupled to the frequency-selective network; a switching stage coupled to an analog log-to-digital conversion Device for generating continuous-time output signals. The switching stage includes at least one resonance circuit. At least one resonance circuit resonates at a resonance frequency to generate at least a portion of the continuous-time output signal; and a continuous-time feedback path for continuously The continuous time output signal is sensed and fed back to the frequency selection network. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 • If the RF communication system under item 6 of the patent application, the system includes a handheld honeycomb communication device. 8 . For example, the RF communication system under the scope of patent application No. 6 includes a cellular base station transceiver. .   9 _ The band-pass amplifier of item 1 of the patent application, wherein the operating frequency band is in the radio frequency band. 10 · Bandpass amplifier according to item 1 of the patent application / wherein the operating frequency band is centered at 900 MHz. Gu Jia Guan Zhuan Zhuan (CNS) Α4 · (210X297 mm) of this paper: 502494 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 _ _ VI. Patent Application Scope 1 1 Bandpass amplifier of term 10, where the resonance frequency is 1 · 8 G Η Z. 1 2. For example, the band-pass amplifier with the scope of patent application No. 10, wherein the resonance frequency is 3.6 GHz. 1 3. For example, the band-pass amplifier of the first patent application range, wherein the operating frequency band is centered on the first frequency. 1 4 · The band-pass amplifier according to item 13 of the patent application, wherein the resonance frequency is twice the first frequency. 1 5 · The band-pass amplifier according to item 13 of the patent application, wherein the resonance frequency is four times the first frequency. 1 6. For example, the band-pass amplifier of the first patent application range, wherein the analog-to-digital converter is a sampling analog-to-digital converter. 1 7 · The band-pass amplifier according to item 1 of the patent application, in which the analog-to-digital converter is an untimed comparator. 1 8.  -A switching stage for a band-pass amplifier, including first and second switching switches in a half-bridge configuration. Both the first and second switching switches have parasitic capacitance associated with them. The switching stage includes multiple inductors and parasitic capacitances. And the inductor form a two-resonance circuit, and the two-resonance circuit resonates alternately at a resonance frequency. 1 9. If you want to switch the level of item 18 of the patent scope, The two resonance circuits each have a resonance node associated with them, and the two resonance circuits both resonate at a resonance frequency. 2 ◦ • If the switching level of item 19 in the scope of patent application, one of the resonance nodes is located at the source terminal of the first switch, and the other resonance node text & Zhang scale is applicable to China National Standard (CNS) A4 specifications ( 210X297 mm) ^: " (Please read the precautions on the back before filling out this page) 502494 A8 B8 C8 D8 々 The scope of patent application is at the drain end of the second switch. 2 1 · The switching stage of item 18 in the scope of patent application, wherein the band-pass amplifier has an operating frequency band centered at 900 MHz and its resonance frequency system 1. 8GHz. 2 2 · The switching stage according to item 18 of the scope of patent application, in which the band-pass amplifier has an operating frequency band centered at 900 MHz and its resonance frequency system 3. 6GHz. 2 3 · The switching stage of the 18th scope of the patent application, wherein the band-pass amplifier has an operating frequency band centered on the first frequency and the resonance frequency therein is twice the first frequency. 2 4 · The switching stage according to item 18 of the patent application scope, wherein the band-pass amplifier has an operating frequency band centered on the first frequency and the resonance frequency therein is four times the first frequency. 2 5 · A switching method for switching a switch from a first logic state to a second logic state. The switch includes a gate terminal, and the gate terminal has a gate capacitor and a resistance associated with the gate terminal. The gate terminal also has a coupling to the gate terminal. The method includes: when the switch is in the first logic state, applying a pulse corresponding to the second logic state to the inductor, the pulse has a first level energy associated therewith, and the first level energy is high enough to overcome The attenuation caused by the resistance allows the gate terminal to reach the signal level corresponding to the second logic state, thereby switching the switch to the second logic state, and the energy of the first level is also low enough to slow down the inductance due to the inductance and the gate capacitance. Oscillates, so that the gate terminal will settle to the signal level before the transfer switch subsequently transitions to the first logic state. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)-(Please read the precautions on the back before filling this page). · 丨 丨 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 502494 Wisdom of the Ministry of Economic Affairs Printed by A8, B8, C8, D8, Consumer Cooperatives of the Property Bureau. 6. Patent application scope. 26. For the method of patent application No. 25, where the first quasi-energy makes the gate extremely stable at the signal level without overshooting the signal. Level. 2 7 · The method according to item 25 of the scope of patent application, wherein the first quasi-energy makes the brake pole settled at the signal level following the damped oscillation, and the S-subtracted oscillation is the overshoot signal level. 2 8 · The method according to item 25 of the scope of patent application, which also includes applying an increased transition to the inductor after the pulse and before the subsequent transition. 2 9 · The method according to item 25 of the patent application range, wherein the first energy level corresponds to the pulse width. 30. The method of item 29 in the scope of patent application also includes the use of an adaptive feedback loop at the supervising gate to adjust the pulse width. 3 1. For example, the method of claim 25 in the patent application range, wherein switching the switch from the first logic state to the second logic state includes performing a low-to-high transition. 3 2. For example, the method of claim 25 in the patent application scope, wherein switching the switch from the first logic state to the second logic state includes performing a high-to-low transition. 3 3. For example, the method of claim 25 in the scope of patent application, wherein the resistance includes the resistance of the switch. 3 4 · The method according to item 25 of the patent application scope, wherein the resistance includes a combination of the input resistance of the switch and the external series resistance. 3 5. For example, the method of claim 25 in the patent application scope, wherein the resistance includes a combination of the input resistance of the switch and the external parallel resistance. · 3 6.  —A kind of RF amplifier, including the Chinese paper (CNS) A4 specification (210X297 mm) applicable to this paper with reduced switching transients -5------------ (Please read · # Note on the back then fill in this page), 1T 502494 A8 B8 C8 D8 6. Electronic device with patent application sensitivity, the electronic device includes: (Please read the notes on the back before filling this page) Switch, including the gate terminal The gate terminal has its associated gate capacitance and resistance, and the gate terminal also has a series inductance coupled to it. The switch can be operated to switch between the first logic state and the second logic state; and the switch control circuit, when the switch is switched In the first logic state, a pulse corresponding to the second logic state is applied to the inductor. The pulse has a first level energy associated with it. The first level energy is high enough to overcome the attenuation caused by the resistance and allow the gate extreme to correspond to The signal level of the second logic state, whereby the switch is switched to the second logic state, and the energy of the first level is also low enough to slow down the inductance and The gate capacitor oscillates so that the gate terminal is settled at the signal level before the switch is subsequently switched to the first logic state. 3 7. For example, the RF amplifier of the patent application No. 36, wherein the switching control circuit can be operated to control the first level energy, so that the gate terminal is settled at the signal level without overshooting the signal level. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 8. For example, the RF amplifier of item 36 of the patent application, wherein the switching control circuit can be operated to control the first level of energy, so that the gate extreme is settled at the signal level following the decaying oscillation. The decaying oscillation is an overshoot signal. Level. 3 9. For example, the RF amplifier of item 36 of the patent application range, wherein the switching control circuit is operable to apply an increased transition to the inductance after the pulse and before the subsequent transition. 4 ◦ If the RF amplifier of the patent application No. 36, in which the switching control circuit can be operated to control the pulse-related pulse width -6- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ) 502494 Α8 Β8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Apply for patents and control the first energy level. 4 1 · If the RF amplifier in the scope of patent application No. 40, it also includes an adaptive feedback loop for supervising the gate end and generating a feedback signal, and the control circuit is switched. . Feedback signal to adjust pulse width. 4 2. For example, the RF amplifier of item 36 of the patent application, wherein the electronic control circuit includes a transistor pair for generating a pulse. 4 3 · If the RF amplifier of item 42 of the patent application scope, in which the electronic device is manufactured by CM S technology. 4 4 · The RF amplifier of item 43 in the scope of patent application, in which the device pair is a half-bridge configuration. 4 5 · The RF amplifier of item 36 in the scope of patent application, wherein the switch and the control circuit are used for baseband operation. 4 6 · The RF amplifier according to item 45 of the patent application range, wherein the frequency range of the fundamental frequency band includes the audio frequency band. 4 7 · If the RF amplifier of item 36 of the patent application scope, wherein the switch and the switch control circuit are used for band-pass operation. 4 8. For example, the RF amplifier of item 47 of the patent scope, wherein the band-pass frequency range includes the radio frequency band. 4 9. For example, the RF amplifier of item 36 of the patent application scope, wherein the electronic device includes an audio amplifier. .  5 〇 If the patent application scope of the 36th RF amplifier. The electronic device includes a wireless communication device. 5 1 · The RF amplifier according to item 36 of the patent application, wherein the electronic device includes a line driver for digital subscriber lines. ----------- (Please read the notes on the back before filling out this page), 1T This paper size is applicable to China National Standard (CNS) A4 specifications (210 × 297 mm) 502494 A8 B8 C8 D8 々, Patent application range 5 2 · The RF amplifier of item 36 in the patent application range, wherein the electronic device includes a motor driver. 5 3 · If the RF amplifier of item 36 of the patent application scope, the resistance includes the input resistance of the switch. 5 4 · If the RF amplifier of item 36 of the patent application scope, the resistance includes the combination of the input resistance of the switch and the external series resistance. 5 5. For example, the RF amplifier with the scope of patent application No. 36, wherein the resistance includes the combination of the input resistance of the switch and the external parallel resistance. 5 6.  A processor for oversampling, noise spectrum shaping, and mixed signals, including: at least one integrator stage in the feedback loop, at least one integrator stage having an input; discrete time sampling stages in the feedback loop, Coupled to at least one integrator stage, the discrete sampling stage is used to sample the analog signal at the sampling frequency only at discrete time intervals; the switching stage in the feedback loop is coupled to the sampling stage, the switching stage has inputs and outputs; and continuous time feedback Path from the output of the switching stage to the input of at least one integrator stage; wherein the switching stage includes a switching switch and a switching control circuit as described in the 36th patent application. 5 7 · A switching method for switching a first switch from a first logic state to a second logic state. The first switch includes a gate terminal, and the gate terminal has a gate capacitor and a resistance associated with the gate terminal. Coupling paper size applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) 77 ^: ~ (Please read the precautions on the back before filling this page), 1T 502494 A8 B8 C8 D8 々, the series inductance applied to the patent application scope, the method includes: when the first switch is in the first logic state, closing the series connection with the gate terminal and the series inductance of the first switch The second switch is used for a period of time to transfer the first energy from the source coupled to the second switch to the gate capacitor. The period of time will be controlled so that the first energy is sufficient to overcome the attenuation caused by the resistance and allow the gate extreme to correspond At the signal level of the second logic state, thereby switching the first switch to the second logic state, the first energy is also low enough to To reduce the inductor and the oscillating guide electrode due to the gate capacitance. 5 8 · The method according to item 57 of the scope of patent application, wherein the first energy makes the gate extreme settle at the signal level without overshooting the signal level. 5 9. For example, the method according to item 57 of the patent application range, wherein the first energy makes the gate extreme settled at the signal level following the damped oscillation, and the damped oscillation is the overshoot signal level. 60. The method of item 57 in the scope of patent application also includes the use of an adaptive feedback loop at the supervising gate to adjust for a period of time. 6 1 · The method according to item 57 of the patent application scope, wherein switching the first switch from the first logic state to the second logic state includes performing a low-to-high transition. 6 2. For example, the method of claim 57 in the patent application range, wherein switching the first switch from the first logic state to the second logic state includes performing a high-to-low transition. 6 3 · The method according to item 57 of the patent application scope, wherein the resistance includes the resistance of the first switch. 6 4 · If you apply for the method of item 5 of the patent scope, the paper size of the resistor package is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _9 (Please read the precautions on the back before filling this page), 1T Printed by the Employees 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 502494 A8 B8 C8 D8 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The scope of the patent application includes the combination of the input resistance of the first switch and the external series resistance. 6 5 · The method according to item 57 of the scope of patent application, wherein the resistor includes a combination of an input resistance of the first switch and an external parallel resistance. 6 6 · — An RF amplifier, including an electronic device with reduced sensitivity to switching transients, the electronic device includes: a first switch, including the smell terminal, the smell terminal has a gate capacitor and resistance associated with it, and the gate terminal also has With a series inductor coupled to it, the switch can be operated to switch between the first logic state and the second logic state; the second switch is connected in series with the gate terminal and the series inductance of the first switch, and when the switch is in the first In a logic state, the second switch can be operated to close for a period of time, thereby transmitting the first energy from the source coupled to the second switch to the gate capacitor. The period of time will be controlled so that the first energy is sufficient to overcome the resistance The attenuation caused and the gate extremes are allowed to reach the signal level corresponding to the second logic state, so that the first switch is switched to the second logic state, and the first energy is also low enough to mitigate the cause due to the inductance and gate capacitance Of oscillation. 6 7. For example, the RF amplifier of the patent application No. 66, in which the second switch can be operated to control for a period of time, so that the gate extreme is set at the signal level without overshooting the signal level. ·.  6 8. For example, the RF amplifier under the scope of patent application No. 66. Among them, the second switch can be operated to control for a period of time, so that the gate extreme is stabilized at the signal level following the attenuation oscillation, and the attenuation oscillation is an overshoot signal level. This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) _ 1〇_ (Please read the precautions on the back before filling this page), 1T- 502494 Α8 Β8 C8 D8 々, patent application scope 6 9 · If the RF amplifier in the patent application No. 66 includes an adaptive feedback loop for monitoring the gate end and generating a feedback signal, the feedback signal is used to adjust the time together with the second switch. 70. The RF amplifier according to item 66 of the patent application, wherein the electronic device is manufactured using C MOS technology. 7 1 _ The RF amplifier according to item 6 of the patent application scope, wherein the floating switch includes back-to-back n MOS and ρ MOS devices. 7 2 · The RF amplifier according to item 66 of the patent application, wherein the first and second switching on relationships are used for fundamental frequency band operation. 7 3 · The RF amplifier according to item 72 of the patent application range, wherein the frequency range of the fundamental frequency band includes the audio frequency band. 7 4. For example, the RF amplifier with the scope of patent application No. 66, wherein the first and second switching on relationships are used for band-pass operation. 7 5 · The RF amplifier according to item 74 of the patent application, wherein the band-pass frequency range includes the radio frequency band. 76. The RF amplifier according to item 6 of the patent application, wherein the electronic device includes an audio amplifier. 7 7 · The RF amplifier according to item 6 of the patent application, wherein the electronic device includes a wireless communication device. 7 8. For example, the RF amplifier of the patent application No. 66, wherein the electronic device includes a line driver for digital subscriber lines. 7 9 · The RF amplifier according to item 6 of the patent application, wherein the electronic device includes a motor driver. 8 0 · If you apply for RF amplifier No. 6 in the scope of patent application, the paper size is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page) Order # Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 502494 A8 B8 C8 D8 6. The scope of the patent application includes the input resistance of the first switch. 8 1 · If you apply for the RF amplifier of item 6 of the patent scope, (Please read the precautions on the back before filling this page) The resistance includes the combination of the input resistance of the first switch and the external series resistance. 0 2If you apply for a patent The RF amplifier of the range item 6, wherein the resistance includes a combination of an input resistance of the first switch and an external parallel resistance. 8 3.  A radio frequency amplifier comprising an electronic device, the electronic device comprising a sampling circuit and at least one switching device having an output terminal, each switching device has a resonance circuit associated with its output terminal, and the resonance circuit and at least one switching device have associated with it The electronic device further includes a timepiece generating circuit, and the timepiece generating circuit generates a timepiece signal for the sampling circuit at least in part by at least one resonance oscillation. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 4. For example, the RF amplifier of the 83rd aspect of the patent application, wherein at least one resonance oscillation includes first and second resonance oscillations, and at least one switching device includes first and second switching devices as output stages of the electronic device, the first and The second resonance oscillation is related to the first and second switching switches respectively, and the timepiece signal is generated at least in part by the first and second resonance oscillations by the timepiece generating circuit. 8 5 · If the RF amplifier of item 84 of the patent application scope also includes a ring oscillator, the ring oscillator has a ring oscillation associated with it, the timepiece signal is generated by the timepiece generating circuit through the first and second resonance oscillations and ring oscillation . 8 6 · If the RF amplifier in the scope of patent application No. 85, also includes a multiplexed circuit for the first and second resonance oscillations and the ring -12- This paper size applies Chinese National Standard (CNS) A4 Specifications (210X297 mm) 502494 A8 B8 C8 D8 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Choose the first, second, and third timepiece signals of the patent application scope. 8 7. For example, the RF amplifier of item 86 of the patent scope, wherein the multiplexing circuit is used to select the third signal selection after selecting one of the first and second signal selections. 8 8. For example, the RF amplifier of the 87th item of the patent application scope, which follows the first and second resonance oscillations of a predetermined number of cycles, and selects the third signal selection after selecting the first and second signal selection. 8 9. For example, the RF amplifier of item 87 of the patent application, wherein the ring oscillator starts and stops synchronously with one of the first and second resonance oscillations. 9 〇. For example, the RF amplifier in the patent application No. 84 includes a multiplexing circuit for selecting between at least first and second timepiece signal selections corresponding to the first and second resonance oscillations, respectively. 9 1. For example, the RF amplifier of the scope of patent application No. 85, wherein the ring oscillation is used when the electronic device is initially supplied with power to start at least one of the first and second resonance oscillations. 9 2. For example, the RF amplifier of the 83rd aspect of the patent application, wherein a switching device has a reference voltage associated with it, the timepiece generating circuit includes at least one comparison circuit, and the at least one comparison circuit is used to compare each switching device with at least one switching device. With regard to the resonance oscillation and the corresponding reference voltage, the timepiece signal is generated at least in part by it. 9 3. For example, the RF amplifier of item 92 of the patent application, wherein the reference voltage includes a power supply voltage for at least one switching device. '9 4 · If you apply for the RF amplifier of item 92 of the patent scope, which (please read the precautions on the back before filling this page) The size of the paper is applicable to China National Standard (CNS) A4 (210X297 mm) -13 -502494 A8 B8 C8 D8 VI. Patent reference range includes ground. (Please read the notes on the back before filling out this page) 9 5. For example, if the RF amplifier of item 84 of the patent application scope, wherein the first switching device has a first power voltage associated with it, and the second switching device has a second power voltage associated with it, the timepiece generating circuit includes a first comparison circuit and a first Two comparison circuits. The first comparison circuit is used to compare the first resonance oscillation with the first power supply voltage. The second comparison circuit is used to compare the second resonance oscillation with the second power supply voltage, and the timepiece signal is generated at least in part by it. 9 6 · The RF amplifier according to item 83 of the scope of patent application, wherein the resonance circuit associated with each switching device includes at least one inductor and at least one capacitor, and at least one resonance oscillation depends on it. 9 7. For example, the RF amplifier of item 83 of the patent scope also includes a high-frequency vibration circuit for vibrating the timepiece signal at a high frequency before being applied to the sampling circuit. 9 8 · The RF amplifier according to item 83 of the patent application scope, wherein the sampling circuit and at least one switching device are used for baseband operation. 9 9 _ The RF amplifier of item 98 in the patent application range, wherein the frequency range of the fundamental frequency band includes the audio frequency band. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 ◦ 0. For example, the RF amplifier of item 83 in the patent application scope, wherein the sampling circuit and at least one switching device are used for band-pass operation. 1 0 1 · The RF amplifier of item 10 · 0 in the patent application range, wherein the band-pass frequency range includes a radio frequency band. 1 0 2. For example, the RF amplifier of the 83rd aspect of the patent application, wherein the electronic device includes an audio amplifier. ‘1 0 3. For the RF amplifier with the scope of patent application No. 83, the paper size of this paper applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 502494 A8 B8 C8 D8 6. Electronic devices in the scope of patent application include wireless communication devices . 104. The RF amplifier according to item 83 of the patent application scope, wherein the electronic device includes a line driver for a digital subscriber line. 105. The RF amplifier of item 83 in the scope of patent application, wherein the electronic device includes a motor driver. 1 0 6. For example, the RF amplifier of claim 84, wherein the electronic device includes oversampling, noise spectrum shaping, and mixed signal processor, including: at least one resonator stage in the feedback loop, and at least one resonator stage has an input ; A discrete time sampling stage in the feedback loop is coupled to at least one resonator stage, the discrete sampling stage is used to sample the analog signal at the sampling frequency only at discrete time intervals; the switching stage in the feedback loop is coupled to the sampling stage, The switching stage has inputs and outputs; and a continuous time feedback path from the output of the switching stage to the input of at least one resonator stage; wherein the switching stage includes an output stage, the discrete sampling stage includes a sampling circuit, and a sampling frequency thereof corresponds to a timepiece signal . 107.  — A radio frequency amplifier, including electronic devices, The electronic device includes at least two sampling circuits and at least two switching stages connected in parallel. Each switching is coupled to one of the sampling circuits. The sampling circuit and switching stages enable the electronic device to present more than two quantized states. The electronic device includes a timepiece. A generating circuit for generating a separate timepiece signal for each sampling circuit. This paper size applies to China National Standard (CNS) A4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page), 1T Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-15- 502494 A8 B8 C8 D8 ^ Patent application scope 1 08 · If the RF amplifier of the patent application scope item 107, (please read the precautions on the back before filling this page) At least two sampling circuits include the first and second sampling circuits and at least The two switching stages include first and second switching stages corresponding to the first and second sampling circuits, respectively. The first and second sampling circuits and the first and second switching stages enable the electronic device to present a 3 quantization state. 1 0 9 · If the RF amplifier of the scope of patent application No. 107, wherein each switching stage has at least one resonance oscillation associated with it, the timepiece generating circuit at least partially from at least one resonance oscillation associated with the corresponding switching stage To generate independent timepiece signals. 1 1 0. For example, the RF amplifier of the scope of patent application No. 109, wherein at least one resonance oscillation for each switching stage includes first and second resonance oscillations, at least in part by corresponding first and second resonance oscillations, Each independent timepiece signal is generated by the timepiece generating circuit. 1 1 1. For example, the RF amplifier with the scope of patent application No. 110 is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and includes a ring oscillator corresponding to each independent timepiece signal. Each ring oscillator has a ring oscillation associated with it. Each independent timepiece signal is generated by the timepiece generating circuit through corresponding first and second resonance oscillations and corresponding ring oscillations. 1 1 2. For example, the RF amplifier of item 11 of the patent scope also includes a multiplexed circuit corresponding to each independent timepiece signal. It is used for the first and second resonance oscillations and the ring oscillation first, respectively. , Second and third signal selection. 1 1 3. For example, the RF amplifier with the scope of patent application No. 112, in which the multiplexing circuit for each independent timepiece signal is used to select the first -16- This paper size applies Chinese National Standard (CNS) A4 specification (210X297) (Centi) 502494 A8 B8 C8 D8 6. After applying for one of the scope of patent application and the second signal selection, select the third signal selection. 1 1 4 · If you apply for the RF amplifier of item 113 of the patent scope, (please read the precautions on the back before filling out this page), which respectively follow the first and second resonance oscillations of a predetermined number of cycles, and then select After the first and second signal selections, select the third signal selection. 1 1 5 · If the RF amplifier in the scope of patent application No. 113, each ring oscillation will start and stop synchronously with one of the corresponding first and second resonance oscillations. 1 1 6 The radio frequency amplifier according to item 11 of the patent application scope, wherein when the electronic device is initially supplied with power to start at least one of the first and second resonance oscillations, a ring oscillation is used. 1 1 7. For example, the RF amplifier under the scope of patent application No. 110 includes a multiplexing circuit corresponding to each independent timepiece signal for selecting at least first and second timepieces corresponding to the first and second resonance oscillations, respectively. Signal selection. 1 1 8. For example, the RF amplifier with the scope of patent application No. 109 is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, where each switching stage has the first and second power supply voltages associated with it, and the timepiece generating circuit includes a corresponding timepiece. At least one of the signals is compared.  It is used to compare at least one resonance oscillation related to the corresponding switching stage and the corresponding power supply voltage, and the independent timepiece signal is generated at least in part by it. 1 1 9. For example, the RF amplifier under the scope of patent application No. 10 · 9 also includes a resonance circuit related to each switching stage. The resonance circuit includes at least one inductor and at least one capacitor for at least one resonance oscillation system of each switching stage. It depends. ‘1 2 0. For example, the RF amplifier with the scope of patent application No. 109, -17- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 502494 ABCD κ, the scope of patent application also includes high-frequency vibration circuit for Before applying to the corresponding sampling circuit, each independent timepiece signal vibrates at a high frequency. 1 2 1. For example, the RF amplifier with the scope of patent application No. 107, wherein the sampling circuit and the switching stage are used for the fundamental frequency band operation. 1 2 2. For example, the RF amplifier with the scope of patent application No. 121, wherein the frequency range of the fundamental frequency band includes the audio frequency band. 1 2 3. For example, the RF amplifier with the scope of patent application No. 107, wherein the sampling circuit and the switching stage are used for band-pass operation. 1 2 4. For example, the RF amplifier with the scope of patent application No. 123, wherein the band-pass frequency range includes the radio frequency band. 1 2 5. For example, the RF amplifier of the scope of patent application No. 107, wherein the electronic device includes an audio amplifier. 1 2 6. For example, the RF amplifier with the scope of patent application No. 107, wherein the electronic device includes a wireless communication device. 1 2 7. For example, the RF amplifier with the scope of patent application No. 107, wherein the electronic device includes a line driver for a digital subscriber line. 1 2 8. For example, the RF amplifier with the scope of patent application No. 107, wherein the electronic device includes a motor driver. 1 2 9. For example, the RF amplifier with the scope of patent application No. 108, wherein the electronic device includes oversampling, noise spectrum shaping, and mixed signal processor, including: at least one resonator stage in the feedback loop, and Input; * The first and second sampling circuits in the feedback loop are coupled to at least one paper size. Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling in this Page), 1T Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives -18-502494 A8 B8 C8 D8 VI. Patent application scope Resonator stage, the first and second sampling circuits are used for the first and The second sampling frequency samples at least one analog signal; (Please read the precautions on the back before filling this page) The first and second switching stages in the feedback loop are coupled to the first and second sampling circuits, each switching stage Both have inputs and outputs; and at least one continuous-time feedback path from the output of the switching stage to the input of at least one resonator stage; wherein the first and second The sampling frequency corresponding to a separate signal timepiece. 1 3 0 · —A method for generating a timepiece. In an electronic device, it includes at least two sampling circuits and at least two switching stages connected in parallel. Each switching stage is coupled to one of the sampling circuits. The sampling circuit and the switching stage enable the electronic device to Presenting more than two quantized states, the method generates an independent timepiece signal for each sampling circuit, including controlling the difference between the frequencies associated with the independent timepiece signal. 1 3 1 • —A modulator circuit with associated band-pass frequency range, including: Switching stage with input and output, the switching stage has the first delay associated with it; the Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperative, prints the tuning Transformer stage with output and feedback input, the output of the modulator stage is coupled to the input of the switching stage; the first feedback path is coupled between the output of the switching stage and the regulator stage •, and.   A notch filter, corresponding to the band-pass frequency range and coupled between the output of the modulator stage and the feedback input of the modulator stage, is used to compensate for the first delay. 1 3 2 · If you apply for the modulator circuit of item No. 131, the bandpass frequency range includes the radio frequency range. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 502494 Α8 Β8 C8 D8 VI. Patent application scope 1 3 3 · If the patent application scope of the modulator circuit No. 132, the band pass frequency The range is centered at 900 μZ. (Please read the precautions on the back before filling this page) 1 3 4 · If you apply for the modulator circuit of item 132 of the patent scope, the bandpass frequency range is 1.  8 G Η z is the center. 1 3 5. For example, the modulator circuit of item 132 of the patent application range, in which the band-pass frequency range is centered at 2 · 4 G ζ ζ. 1 3 6. For example, the modulator circuit of the patent application No. 131, wherein the notch filter uses analog technology to generate a feedback signal. 1 3 7. For example, the modulator circuit of the patent application No. 131, wherein the notch filter uses digital technology to generate a feedback signal. 1 3 8. For example, the modulator circuit of the patent application No. 131, wherein the notch filter uses a hybrid signal technology to generate a feedback signal. 1 3 9. For example, the modulator circuit of the patent application No. 131, wherein the notch filter is directly coupled to the output of the modulator stage. 1 4 0 · If the modulator circuit of the patent application item No. 131, the notch filter is coupled to the output of the modulator stage through the inverting loop element. 0 Printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 · The modulator circuit of item 131 in the scope of patent application, wherein the first feedback path is coupled to the modulator stage via the feedback input. 1 4 2 · The modulator circuit of item 1 3 · 1 in the scope of patent application, wherein the first feedback path is coupled to the modulator stage at a point other than the feedback input. 0 1 4 3 ·-An RF amplifier including Relevant modulator circuit of the band-pass frequency range, the modulator circuit includes: This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) -20- 502494 A8 B8 C8 D8 Switching stage with input and output, the switching stage has a first delay associated with it; s-week variable gain stage, with output and feedback input, the output of the modulator stage is coupled to the input of the switching stage; the first feedback path is coupled to the switch Between the output of the stage and the modulator stage; and a notch filter corresponding to the band-pass frequency range and affinity between the output of the modulator stage and the feedback input of the modulator stage, for compensating the first delay 0 1 4 4 · A wireless communication device including a modulator circuit having an associated band-pass frequency range. The modulator circuit includes: a switching stage having inputs and outputs, and the switching stage having Its associated first delay; a modulator stage having an output and a feedback input, the output of the modulator stage is coupled to the input of the switching stage; a first feedback path coupled between the output of the switching stage and the modulator stage; The notch filter corresponds to the band-pass frequency range and is coupled between the output of the modulator stage and the feedback input of the modulator stage to compensate for the first delay. 1 4 5. For example, in the case of the modulator circuit of the patent application No. 1 3 _1, the first feedback path starts from the matching network coupled to the output of the switching stage. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). (Please read the precautions on the back before filling out this page) · Binding · Order Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs