TW502429B - Method of fabricating an ESD protection device - Google Patents

Abstract

A method of fabricating an ESD protection device is disclosed. A trench having an inverted triangle cross-sectional profile is formed in a substrate. The trench is formed incorporated with a conventional STI process by using one mask. After that, an isolation layer is filled into the trench and a doped (S/D) region is formed on either side of the trench. The ESD device according to the present invention shows reduced punch through voltage and device dimension.

Description

502429 V. Description of the invention (i) Field of the invention The present invention provides a method for manufacturing an electrostatic discharge (ESD) protection element, particularly a method for simultaneously manufacturing a shallow trench isolation (ST I) layer and an electrostatic discharge protection element. Background: As semiconductor integrated circuits and components continue to shrink in size, in the manufacturing technology of deep submicron complementary metal-oxide-semiconductor (CMOS) 'not only the channel length needs to be shortened, The gate oxide layer needs to be thinner, the junction depth becomes shallower, and at the same time the dopant concentration of the well (wei 1) needs to be increased. However, the above process often makes integrated circuit products more vulnerable to damage from electrostatic discharge (ESD). When an electrostatic discharge occurs, it usually generates a transient high voltage and damages the gate oxide layer in the CMOS transistor or the surface channel near the lightly doped region. Therefore, an ESD protection circuit is usually added to the wafer. These electrostatic discharge protection circuits will not work under normal operating conditions, but when an electrostatic discharge occurs, they will conduct to release ESD current to protect the gastric X: body circuit from ESD damage. & Please refer to FIGS. 1 to 3, which are schematic diagrams of a conventional method for manufacturing an M D protection circuit. Please refer to FIG. 1 on a semiconductor wafer i 〇

502429 V. Description of the invention (2) 'Includes a substrate 12 and performs a traditional yellow light and etching technique on the surface of the substrate 12 to form a width of about 0.5 to 0.8 m / m and a depth of about 4 〇〇〇ange (A) of the shallow trench (shal low trench) 14, and then a chemical vapor phase = deposition process, the semiconductor wafer, an insulating layer i 6 is deposited on the surface, usually made of silicon nitride or silicon dioxide The structure covers the surface of the substrate 2 to fill the shallow trenches 1 4. Referring to FIG. 1 ', a chemical mechanical polish (CMP) process or a rebate process may be performed next to planarize the semiconductor wafer surface. Referring to FIG. 3, a pad oxide layer 18 is formed on the surface of the substrate 2 and a gate structure 20 is formed on the pad oxide layer 8. The gate structure 20 is usually composed of doped polycrystalline silicon. Subsequently, an ion distribution system is performed to form a source electrode 26 and an electrode 28 on both sides of the gate structure 20, and a depletion region (depleti nregi ο η) 3 0 below the shallow trench 14. 'Form an M 0 S structure as an ESD protection element. The above M0S structure is located between an output / input pad (1 / 〇pads) and an inner circuit, in which the gate 20 and the source 26 are connected together and electrically connected to the output / input Buffer pad, and the drain 28 is electrically connected to a source pin. Therefore, when an ESD voltage is introduced from the output / input buffer pad, the rapidly rising ESD voltage will be coupled with the gate 20, so that the M0S structure is opened, and the ESD current is discharged from the output / input buffer pad to the v D power pin. To protect the internal circuit from ESD current damage.

502429

When making an ESD protection circuit, the chip area (ch ip area) needs to be considered, otherwise it will violate the principle of minimizing the chip size. However, the traditional ESD protection elements generally have the disadvantage of occupying a large area. In addition, the ESD protection elements made by the conventional technology also have the unfavorable factors of excessively high punch through vo It age, resulting in a decrease in ESD protection performance. Therefore, at present, the industry generally needs an ESD protection device with a simpler process, a lower penetration voltage, and a smaller size. SUMMARY OF THE INVENTION The main object of the present invention is to provide an ESD protection element formed by a shallow trench isolation process, so as to achieve the purpose of simplifying the process and reducing the size of the element. 0 The present invention provides a method for simultaneously manufacturing a shallow trench isolation (sha 1 1 ow A method of trench isolation (STI) and an electrostatic discharge (ESD) protection device on a semiconductor wafer. The semiconductor wafer includes a substrate, and a well (we 1 1) region is disposed in the substrate. The method includes the following steps: firstly forming a mask layer on the surface of the substrate, which includes a first A shallow trench pattern and a second shallow trench pattern, wherein the second shallow trench pattern is located in the well region, and the first shallow trench pattern includes a first opening with a first width, and the second shallow trench pattern includes a first A second opening of two widths, and the second width is smaller than the first width, and then a dry etch process is performed,

502429 V. Description of the invention (4) The substrate is etched through the first opening and the second opening to simultaneously form a first shallow trench with inclined sidewalls and a trapezoidal vertical section on the substrate, and the vertical section is inverted One of the second shallow trenches in the triangle, wherein the second shallow trench and the first shallow trench have sidewalls having approximately the same slope, and the depth of the second shallow trench is less than the depth of the first shallow trench, and then the first shallow trench An insulating layer is filled in the trench and the second shallow trench, and then a doped region is formed in the substrate on both sides of the second shallow trench. When the shallow trench isolation process is performed, the present invention simultaneously generates a plurality of shallow trenches with small widths and depths as an ESD protection element, and adjusts the depth and width of the shallow trenches according to the required penetration voltage, so that it can be greatly reduced. The size of ESD protection components and their manufacturing process are simplified. Detailed description of the invention Please refer to FIGS. 4 to 6. FIGS. 4 to 6 are schematic diagrams of a method for manufacturing an ESD protection circuit according to the present invention. Please refer to FIG. 4, a semiconductor wafer 40 includes a P-wel 1 42, and a mask layer 44 is formed on the surface of the semiconductor wafer 40, and then a lithography process is performed. A first shallow groove pattern and one are defined on the mask layer 44. The second shallow groove pattern, wherein the second shallow groove pattern is located in the region of the p-well 1 (p-wel 1) 42, and the opening W2 of the second shallow groove pattern is smaller than the opening W1 of the first shallow groove pattern. Then, a dry etching process is performed, and a plurality of shallow trenches are formed on the surface of the semiconductor wafer 40 by adjusting the parameters of the etching process, and

502429 V. Description of the invention (5) The slopes of the sides of the shallow trenches are about the same. Because the first shallow groove pattern and the second shallow groove pattern defined in the cover layer 44 have different opening sizes, a deeper first shallow groove 46 will be formed in the place where the opening is large, and the opening will be formed in the opening. Smaller will form a second shallow trench 4 8 with a shallower depth. Among them, in a preferred embodiment of the present invention, the vertical cross section of the first shallow groove 46 is trapezoidal, and the opening width W1 is about 0 · 2 2 to 0 · 3 5 // m. The vertical section is approximately an inverted triangle, and the opening width W2 is less than 0.2 / zm. Please refer to FIG. 5, and then remove the mask layer 44 and perform a chemical vapor deposition (CVD) process. An insulating layer is covered on the surface of the semiconductor wafer 40 to fill the shallow trenches 4 6 and 4 8. ·. Thereafter, a chemical mechanical polishing (CMP) process or an etch-back process can be used to remove the insulating layer on the surface of the semiconductor wafer 40, leaving only the insulating layers filled in the first shallow trenches 4 6 and the second shallow trenches 48. 5 0. The function of the first shallow trench 46 is to form a shallow trench isolation area, which is used to define an active area on the semiconductor wafer 40, so as to further manufacture the components on the semiconductor wafer 40. Please refer to FIG. 6, and then perform an ion layout process to form two N-type doped regions 5 2 and 5 4 on both sides of the second shallow trench 4 8 and an empty region 56 under the shallow trench. From this N-type doped region 5 2, a P-type well and an N-type doped: region 54, an NPN bipolar transistor (BJT) transistor (BJT) structure is formed as an Esw die-cast element. After that, external electrical connection (not shown) of this B JT structure can be further performed to complete the production of an ESD protection circuit. Under normal operating conditions, this BJT structure is in an open circuit

502429 V. Description of the invention (6) --- state, and when a high voltage exceeding its penetration voltage passes, the bjt structure will form a path, and the current will be led out of the BJT structure to protect other semiconductor components from got damage. In addition, in the above embodiment, although an NPN bipolar transistor composed of a P-type well 42 and two N-type doped regions 52 and 54 is used as the ESD protection element; ^ However, the same principle can be used in one P-type ion doping is performed in the N-type well or the N-type substrate to form a PNP bipolar transistor as an ESD protection element. Generally, the purpose of the shallow trench isolation process is to completely isolate the components on both sides of the shallow trench. Therefore, the formed shallow trench often needs to have a certain width and depth, otherwise it cannot be effectively isolated, which may result in high voltage penetration. The phenomenon. The present invention in turn uses such a low-through-voltage structure to apply it to an ESD protection circuit, so that it is in an open state under normal conditions, but when it is exposed to a high voltage, a path is formed to guide the current to prevent other circuit elements. Damaged by high voltage. In addition, the shape (width and depth) of the shallow trench formed can be controlled by techniques such as yellow light and etching to adjust its penetration voltage. Compared with the prior art, the ESD protection element of the present invention has a simple structure, and can be performed simultaneously with a general shallow trench isolation process. In addition, since the ESD protection element of the present invention has a small area and low penetration voltage, it can be applied to deep sub-micron processes to further reduce the size of the element and improve economic efficiency.

502429

Page 502 502 Schematic illustration, simple illustration Figures 1 to 3 are schematic diagrams of a conventional ESD protection circuit manufacturing method. Figures 4 to 6 are schematic diagrams of a manufacturing method of the ESD protection circuit of the present invention. Symbol description

10 Semiconductor wafer 12 Substrate 14 Shallow trench 16 Insulating layer 18 Pad oxide layer 20 Gate 26 Pole 28 Source 30 Empty area 40 Semiconductor wafer 42 P-type well 44 Cover layer 46 Shallow groove 48 Shallow groove 50 Insulating layer 52 N-type Doped region 54 N-type doped region 56 Empty region 第 11 页

Claims (1)

502429 6. Application Patent Scope 1. A method for simultaneously forming a shallow trench isolation (STI) and an electrostatic discharge (ESD) protection element on a semiconductor wafer. The semiconductor wafer includes a A substrate and a well region are disposed in the substrate. The method includes the following steps: forming a mask layer on the surface of the substrate, which includes a first shallow trench pattern and a second shallow trench; Pattern 'wherein the second shallow trench pattern is located in the well region, and the first shallow trench pattern includes a first opening with a first width, and the second' / ¾ trench pattern includes a second opening with a second width, And the second width * is smaller than the first width; a dry etch process is performed, and the substrate is engraved through the first opening and the second opening to simultaneously form an inclined sidewall with a vertical on the substrate A first shallow trench with a trapezoidal cross section and a second shallow trench with a vertical cross section of an inverted triangle, wherein the second shallow trench and the first shallow trench have approximately the same slope Sidewalls, and the depth of the second shallow trench is less than the depth of the first shallow trench; an insulating layer is filled in the first shallow trench and the second shallow trench; and the two sides of the second shallow trench are A doped region is formed in the substrate. 2. The method according to item 1 of the patent application scope, wherein the substrate is a stone evening substrate. Page 12 502429 6. Scope of Patent Application 3. For the method of the first scope of patent application, the area of the well is a P-type well or an N-type well. 4. The method according to item 1 of the patent application scope, wherein the first width is between 0.22 and 0.35 micrometers, and the second width is less than 0.2 micrometers. 5. The method according to item 1 of the patent application, wherein the electrostatic discharge protection element is a bipolar junction transistor (BJT) ° 6. The method according to item 1 of the patent application, wherein the doping The region contains dopants of a different semiconductor type than the well region. 7. A method for manufacturing an electrostatic discharge protection element, the method comprising the following steps: providing a semiconductor wafer including a substrate thereon, and a well region provided in the substrate; forming a cover layer on a surface of the substrate Including an opening with a width of less than 0.2 micrometers located in the well region; performing a dry etch process, etching the substrate through the opening to form a shallow trench with a vertical cross section of an inverted triangle on the substrate; An insulating layer is filled in the shallow trench; and a doped region is formed in the substrate on both sides of the shallow trench. Page 13 502429 6. Scope of patent application 8. For the method of the seventh scope of patent application, the substrate is a silicon substrate. 9. The method according to item 7 of the patent application, wherein the well area is a P-type well or an N-type well. 10. The method according to item 7 of the scope of patent application, wherein the electrostatic discharge protection element is a bipolar transistor. 11. The method of claim 7 in the patent application range, wherein the doped region contains a semiconductor of a different type than the well region. Page 14