TW502403B - Method of fabricating a stringerless flash memory - Google Patents

Abstract

A semiconductor substrate is provided. A number of rows of layer stacks are formed on the semiconductor substrate with a shallow trench positioned between two adjacent layer stacks. Each layer stack is a polysilicon layer and a sacrificial layer and has two side walls. Each side wall of the layer stack intersects the bottom of the shallow trench at an angle of approximately 90 degrees. A HDPCVD silicon oxide layer is deposited to cover the layer stacks and the shallow trenches followed by a planarization process to remove portions of the HDPCVD silicon oxide layer to expose the sacrificial layer. Then, the sacrificial layer is removed. An insulating layer, a word line layer, and a photoresist layer are formed on the polysilicon layer, respectively. The photoresist layer is patterned so as to define a position for forming a word line. A first dry etching process is performed to remove portions of the word line layer not covered by the photoresist layer with a first selectivity of polysilicon to silicon oxide. Following that, a second dry etching process is performed to etch portions of the insulating layer not covered by the photoresist layer with a second selectivity of polysilicon to silicon oxide. Finally, a third dry etching process is performed to etch the polysilicon layer with a third selectivity of polysilicon to silicon oxide, forming a T-shape side view for the remaining polysilicon layer.

Description

502403

V. Description of the invention (1) Field of the invention The present invention relates to a method for making a flash memory (flash memory), and particularly to a method for operating a flash memory without stringerl ess. Effectively solve the problem of stringer leakage of flash memory, and improve data retention ability of flash memory at the same time. 0 "Background description Flash memory is a non-volatile (non- volati le) memory, which can also store the information content stored in the memory when there is no external power supply. In recent years, because flash & memory has rewritable and can be erased by electricity, etc. Advantages, it has been widely used in mobile phones (m 〇 bi 1 eph ο ne), digital cameras (digital cameras), video players, personal digital assistants (personal digital assistants, PDA) and other electronic products or The system on a chip (SOC) in development. Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of a conventional flash memory unit 30. As shown in FIG. The flash memory cell 30 includes a substrate 10, a floating gate 14, a 0N0 dielectric layer 18, and a word line 20. The floating gate 14 is generally made of polycrystalline silicon. And is located between the isolation dielectric layers 12a and 12b. Between the isolation dielectric layers 12a and i2b

502403 5. Below the description of the invention (2) are a doped region 11 a and 11 b, respectively, which are used as bit lines of the flash memory cell 30, sometimes called a buried drain (η) or Buried source. In addition, a tunneling oxide layer 13 is further included between the floating gate 14 and the substrate 10. Hot electrons tunnel into and out of the floating gate 14 through the tunneling oxide layer 13 to achieve the data access function of the flash memory cell 30. However, it is known that during the process of manufacturing the flash memory unit 30, a residual polysilicon 22 is often generated, causing a leakage phenomenon. This is due to the fact that the profile of the side walls of the isolation dielectric layers 12a and 12b is not perpendicular to the substrate 10. It is not easy to maintain a nearly vertical included angle, and the missing angle usually changes with small variations in process parameters. When the degree of isolation 0 (shown in Fig. 1) between the sidewalls of the isolation dielectric f 1 2a and 1 2b and the substrate exceeds 0 degrees, the residual dielectric element lines 20 and the floating gate η will result in the dielectric Residual polycrystalline silicon 22 is formed on the sidewalls of the layers 12a and Kb. This residual layer ^ sparite 22 is also referred to as a residue (31: 1 «111 ^ 1 ^). Residual polycrystalline silicon 22 remaining on the side walls of the isolation dielectrics 2a and 12b will affect the flash memory # = performance, cause leakage current, and thereby reduce the data dimension of the flash memory. 'In order to avoid the formation of remnants, Membrane Uranium must be strictly controlled to ensure that the gap between the isolation dielectric layer i 2a and the side walls of the dielectric layer i 2a and the substrate is kept at an orthogonal vertical angle as much as possible. That is, in etching the floating gate 1 4

Page 7 502403 V. Description of the invention (3) When the sidewalls are maintained vertical, the sidewalls of the isolation dielectric layers i 2a and 12b and the substrate can maintain an orthogonal vertical angle, but due to insufficient process window flexibility, The conventional method of controlling the process parameters to maintain the orthogonality Θ still cannot guarantee the consistency of the orthogonal angle, so it is impossible to determine the residual problem of the residual edge. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a flash memory manufacturing method to solve the above problems. Another object of the present invention is to provide a method for manufacturing a stririgerless flash memory, which can obtain reliability. Another object of the present invention is to provide a method for manufacturing a non-residue flash memory, which can obtain a relatively wide process window. Another object of the present invention is to provide a method for manufacturing a flash memory having a τ-shaped floating gate. According to the manufacturing method provided by the present invention, a plurality of layer stacks are formed on a surface of a silicon oxide layer on a semiconductor substrate, and

Page 8 V. Description of the invention (4) Stacked together next to each other The Xi Xi layer and: Sacrifice = Cheng-shallow trench. Each of the stacked layers is formed by stacking 4 polycrystalline sidewalls H and ΐ on top and bottom, and each of the stacked layers has two angles of about 88 to 9, 2 and each side wall of the stacked layer is at an angle with the bottom of the shallow trench. (After hUh deisfu, a high-density plasma chemical vapor deposition HDPCVD is deposited) Shi Xi oxygen layer 'Hi two products 〇Γ deP0sition, $ ,, between the stacked layers, cover the complex layers and fill the layers The plurality of columns expose the sacrificial layer t * f. Then flatten the HDPCVD oxygen-generating layer until it becomes an insulating layer 2 and ΐ 牺牲 the sacrificial layer, and then sequentially form a resistive layer on the polycrystalline silicon layer to define the two sub-line layers and define the word line layer. A photo-polycrystalline silicon pair is formed on the oxidation = a line position. Subsequently, a first dry etching process with a first etching selection ratio covered by the photoresist layer is sequentially performed. The etching is not performed on the silicon oxide, word = line layer, and a second polycrystalline silicon is performed. The layer is covered with the second dry etching process, the etching is not compared with the photoresist silicon etching selection ratio, and a dry etching process with a third polycrystalline silicon to the second oxide is performed, and the etching is continued. Polycrystalline silicon layer. According to the present invention, the structure of Erb a is T-shaped, so that the polycrystalline stone layer has a cross section.箆-a ancient 丨 manufactured in Xixi Rixi will not remain on the side wall of the HDPCVD Shixi oxygen layer; system: active power output and bias power input is better to sing 2 = material company's DPS-P01 y etcher. Helium-oxygen (ιΐ-ΐ) to m uses 90% to 95% of chlorinated chlorine and about 5%. 12: m out of about 70 to 150 watts, and the pressure is about 5. to m Torr. Under this condition, the third etching process has a larger side

Page 9 502403 V. Description of the invention (5) The ability to carve the surname can effectively avoid the residue of the residue. For a detailed description of the invention, please refer to FIGS. 2 to 8. FIGS. 2 to 8 are schematic diagrams of a flash memory cell fabricated on a silicon substrate 50 according to a preferred embodiment of the present invention. Sectional side view along tangent line AA '. The surface of the silicon substrate 50 can be generally divided into a memory area and a peripheral area. To facilitate the description of the technology of the present invention, FIG. 2 to FIG. 7 only show a part of the memory related to the present invention. Area enlarged section. Other areas on the silicon substrate 50, such as the peripheral areas, are not shown in Figures 2-7. First, as shown in FIG. 2, the method of the present invention forms an oxide layer 51 before the surface of a stone substrate 50. The oxide layer 51 can be used later as a tunneling oxide layer of the floating gate, and its thickness is between 30 and 150 angstroms. The manufacturing method of the oxide layer 51 can be a commonly used wet or dry oxidation method, which is not described herein again. In a preferred embodiment of the present invention, the silicon substrate 50 is a lightly doped P-type single crystal silicon substrate having a < 丨 〇 〇 orientation direction. However, the present invention is not limited to this, and other substrates, such as a commercial silicon-on-insulator (soi) substrate formed by a general Smox method, are also applicable to the present invention. Next, a thickness of about 800 to 1,000 is deposited on the surface of the oxide layer 51.

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Angstrom (undoped) polycrystalline silicon layer 52. The square f of the polycrystalline silicon layer 52 can be deposited by using the low pressure chemical vapor deposition (LPCVD) method. The process conditions are as follows: silane (Si HO) is used as the reaction gas, and the temperature is set between 570 ° C and 650 ° C. The pressure is about 0.3 to 0.6 Torr (t0rr). Subsequently, a thickness of about 0.001 to 9000 angstroms is deposited on the surface of the polycrystalline silicon layer 52, and preferably about 140. 0 Angstrom, the silicon nitride layer 5 4. The silicon nitride layer 5 4 can be deposited by a general CVD method, because it is well known to those skilled in the art, so it is not described. The nitride nitride layer 5 4 series It is used as a sacrificial layer and will be removed in the subsequent process 1. Then, a yellow light process is performed to form a photoresist layer 55 on the surface of the nitride layer f 54. The photoresist layer 55 forms a pattern To define the position of the floating gate and the channel length of the floating gate °

Next, as shown in FIG. 3, a high density plasma etching (HDP RIE) process is performed to etch the silicon nitride layer 54 and the polycrystalline silicon layer 52 which are not covered by the photoresist layer 55. As a result, a plurality of three-dimensional structures 58 having a stripe arrangement are formed on the surface of the Shixi substrate 50 in the memory area. The three-dimensional structure 58 will be defined as a floating gate in subsequent processes. A shallow trench 59 having a width of about 0.25 to 0.4 micrometers is formed between two adjacent three-dimensional structures 58. In a preferred embodiment of the present invention, the angle 0 formed by the bottom of the shallow groove 5 9 and the side walls of the three-dimensional structure 58 is between 88 and 92 degrees (that is, 88 $ 0 S 92.). When the inflammation angle θ is between '90 and 92 degrees (that is, 90S Θ S 92.) ', this is an angle that is easier to generate stringers in subsequent processes. Subsequently, the photoresist layer 55 is removed.

502403 V. Description of the invention (7) Still insert one as the bit line as shown in the bottom 50. And a dose of 1 E 1 4 to an ion at room temperature, for example, a chemical vapor deposition deposition, HDPCVD second oxygen layer I == itchy, and then an ion implantation process, as early as Shi Xiji on S2, conductive Doping, forming a doped region 62, for 1E1 · d =, the amount of arsenic ions of about 50 to 150 KeV in ancient mother square centimeters (ions / cm 2), doped one or more times at M degrees . Other N-type (Hiebu!) Is suitable for the present invention. Then a high density density plasma chemical vapor process is performed to fill the surface of the three-dimensional structure 58 with 63, and fill the shallow trench 59. Then, as shown in Figure 4, With the merhan i 1 ι ·,-mechanical milling (chem i ca 1 P called, CMP) process, the silicon nitride layer 54 is used as an abrasive layer, and the HDPCVD silicon oxide layer M is polished until exposed. Nitride stone ^ = this ^, after CMP grinding, an HDpcvD stone oxidized layer 6 is formed to isolate the three-dimensional structure 58 with 63 Å. It should be noted that only the schematic cross-sections are shown in FIGS. The disc effect (d 丨 A /, effect) of CMp is displayed. G Next, as shown in Figure 5A and Figure 5B (Figure 5A is a cross-sectional side view of Figure 5B along the tangent line AA '), first perform A wet etch process using a phosphoric acid (H3Pj) 4) solution heated to 150 to 180 ° C as an etching solution to completely remove the silicon nitride layer 54 to expose the polycrystalline silicon layer underneath. 52. The wet etching process is performed in an etching bath (not

502403 5. In the description of the invention (8), the soaking time is about tens of seconds to several minutes, depending on the thickness of the nitrogen fossil layer 54. In addition, other wet etching methods that can effectively remove the silicon nitride layer 54 are also applicable to the present invention. Next, a 0N0 layer 62 and a doped polycrystalline silicon layer 64 are sequentially formed on the surface of the polycrystalline silicon layer 52. A photoresist layer 66 is formed on the doped polycrystalline silicon layer 64. The photoresist layer 66 has a word line pattern for defining the position of the word line. The doped polysilicon layer 64 is used as a word line or flash memory cell. ^ Control gate, which can be combined with in-situ doping or other ion implantation using the general CVD method. The manufacturing process enables the doped polycrystalline silicon layer 64 to reach a desired dopant concentration. The 0N0 layer 62 is formed using a general OX (Oxidized-silicon nit Tide-si 1 icon oxide) process. An oxide layer with a thickness of about 10 to 50 angstroms is first formed on the surface of the polycrystalline silicon layer 64, and then a plasma enhanced chemical vapor deposition (pi asn ^ -enhanced CVD (PECVD) method or LPCVD method) Dichorosi lane (SiH2Cl 2) and ammonia (ammonia, NH 3) are reactive gases, and a silicon nitride layer (not shown) with a thickness of about 45 Angstroms is deposited on the surface of the oxide layer. Finally, a high-temperature healing process is performed in a high-temperature oxygen-containing environment at about 800 degrees Celsius for about 30 minutes to form an oxygen-containing silicide (about 40 to 80 angstroms) on the surface of the silicon nitride layer ( siliconoxy-nitride) layer. The oxygen-containing silicide layer is mainly used to fill the defects of the silicon nitride layer on the surface of the natural oxide layer, so as to reduce the leakage current. In addition, other methods of forming the 0N0 layer 6 2

Page 13, 502403

Processes such as the furnace tube emulsification process are also suitable for the present invention. In addition, in other embodiments of the present invention, a metal silicide layer such as a tungsten silicide (WSi 2) layer and an anti-reflection layer (anU-reflection layer) may be formed on the doped polycrystalline silicon layer 64. For example, a silicon oxynitride (Si ON) layer. The metal silicide layer is used to reduce the resistance of the word lines, and the anti-reflection layer is used to increase the accuracy of the yellow light process when defining the word lines.

Subsequently, as shown in FIG. 6, the photoresist layer 66 is used as an etch mask to perform a first etching process, and the doped polycrystalline silicon layer 64 that is not covered by the photoresist layer 66 is etched to the substrate and stopped at 0N0 layer 62. The selection ratio of the polycrystalline silicon layer 52 to the HDPCVD silicon oxide layer 63a / b in the first etching process (that is, the etching rate of the polycrystalline silicon layer 52 to the HDPCVD silicon oxide layer 63a / b) is about 5 to Between 10, you can use the general reactive ion etching process or plasma plasma etching process. For example, ‘use a device with a source power output (s 〇 u r c e power supply) and a bias power output (bias p0wer supply)

Etching machines, such as DPS (Decoupled Plasma Source) -Poly etcher from Applied Materials Co. It is recommended that a better etching gas system uses a mixture of hydrogen bromide (HBr), chlorine (C1 2) and helium-oxygen (He-〇2). The source power output is about 600 to 800 Watts, Bias power output is approximately 70 to 150 watts, and pressure is approximately 5 to 10 Torr. Next, a second etching process is performed to adjust the polycrystalline silicon layer 52 pair.

Page 14 502403 V. Description of the invention (10) The "selection ratio" of the Shixi oxygen layer 63a / b is between 0.7 and 0.9. The second etching process uses an etching machine port having a source power output and a bias power output, such as D P S-P ο 1 y e ΐ c h e r of Applied Materials. It is suggested that the better fj gas system uses carbon tetrafluoride (C ρ 〇 and argon (αγ), where the CF / Ar / ;, L ratio is about 0 · 1 3, the source power output is about 6 0 0 to 8 0 0 watts, bias voltage 'power output is about 60 to 100 watts, and pressure is about 5 to 10 torr. Then' as shown in Figure 7, a third etching process is performed to raise the polycrystalline stone Xi ^ 52 selection ratio of HDPCVD stone oxide layer 63a / b is more than 15. The third etching process uses an etching machine with source power output and bias power output, such as DPS-Poly etcher of Applied Materials. It is recommended to use a 90% to 95% hydrogen bromide and about 5% to 10% helium-$ (He-〇2) mixed gas for a better gas-engraving system. The source power output is about 300. To 600 watts, bias power output of about 70 to 150 watts, and pressure of about 500 to 100 Torr. Under this preferred condition, the polycrystalline silicon layer 52 is opposed to the HDPCVd silicon oxide layer 63a. The selection ratio of / b can be increased to between 15 and 20. Then the photoresist is removed ^ 66. As shown in FIG. 8, FIG. 8 is a schematic cross-sectional view taken along the tangent line BB in FIG. 7. After the second etching process, the polycrystalline silicon layer 52 has a Ti surface structure due to changes in the etching parameters. In addition, the third remaining process can produce a T-shaped facet structure, which means strong side etching, so it can avoid residual Margins (or polycrystalline silicon residues) are formed on the sidewalls of the HDPCVD silicon oxide layers 63a and 63b. _ Phase car means the flash memory manufacturing method known by the present invention.

502403 V. Description of the invention (11) 2M etching The etching method is divided into three stages, which are the above-mentioned process / process and the third process of etching. A third cross-sectional structure is formed by using the third etching process, and the bottom corner residues (b 0 11 0 m c 0 r n e r s t r i n g e r) can not be generated when the polycrystalline silicon layer 52 is etched. The quick memory system of the present invention can effectively solve the leakage problem caused by the residues at the bottom corners, which can improve the reliability of the product and maintain the data retention capability of the memory. The above description is only an equivalent change of the scope of the present invention. The scope of the present invention is covered by the following examples. A > Decoration ’should be covered by the invention patent

Page 16 502403 Brief Description of Drawings Brief Description of Drawings Figure 1 is a schematic cross-sectional view of a conventional flash memory cell. FIG. 2 to FIG. 8 are schematic diagrams of a method for manufacturing a flash memory cell according to the present invention. FIG. 5A is a cross-sectional side view along a tangent line AA ′ in FIG. 5B. Fig. 8 is a sectional side view taken along the line BB 'of Fig. 7. Explanation of symbols in the diagram 10 Silicon substrate 1 la / b Doping region 12a / b Isolation dielectric layer 13 Tunneling oxide layer 14 Floating gate 18 0N0 dielectric layer 20 Word line 22 Residual polysilicon / residue 30 Fast flash Memory tier — Early stage 50 Shixi substrate 51 Oxidation layer 52 Polycrystalline silicon layer 54 Silicon nitride layer 55 Photoresist layer 58 Three-dimensional structure 59 Shallow trench 62 ΟΝΟ Dielectric layer 63 HDPCVD Stone oxide layer 63a / b HDPCVD Oxygen layer 64 Word line layer 66 Photoresist layer 80 T-shaped structure _

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Claims (1)

502403 VI. Scope of patent application1. A method for making stringer 1 ess flash memory, the method includes the following steps: providing a semiconductor substrate with a silicon oxide layer formed on the silicon substrate; A plurality of layer stacks are formed on the oxygen layer, and a shallow trench is formed between two adjacent stack layers. Each of the stack layers is formed by stacking a silicon layer and a sacrificial layer on top of each other. The angle between the side walls of the layer and the bottom of the shallow trench is between 88 and 92 degrees; a high density plasma chemical vapor deposition (HDPCVD) stone oxide layer is deposited Covering the plurality of stacked layers and filling the shallow trenches between the plurality of stacked layers; planarizing the HDPCVD silicon oxide layer until the sacrificial layer is exposed; 'removing the sacrificial layer; sequentially on the polycrystalline silicon layer Forming an insulating layer and a word line layer; forming a photoresist layer on the word line layer to define the position of the word line; performing a first dry-remaining process with a first polycrystalline silicon oxide Shi Xi etching selection ratio Etching the word line layer not covered by the photoresist layer; performing a second dry-etching process with a second polycrystalline stone to oxide crushing etching selection ratio, and etching the insulation not covered by the photoresist layer And performing a third dry-repeated process, having a third polycrystalline silicon oxide oxide selection ratio, and continuing to etch the polycrystalline silicon layer. 2. The method according to item 1 of the patent application scope further comprises an ion implantation process' to form a buried bit line in the semiconductor substrate through the shallow trench. Page 18 502403 6. Scope of patent application 3. The method of the second scope of patent application, wherein the ion implantation process is performed after the shallow trench is formed. 4. The method according to item I of the patent application, wherein the sacrificial layer is composed of nitrogen &silicon; _ 5. The method according to item 1 of the patent application range, wherein the polycrystalline silicon layer of the stacked layer is composed of undoped polycrystalline silicon. 6. The method according to item 1 of the patent application scope, wherein the insulating layer is a 0 N 0 dielectric layer. 7. The method of claim 1, wherein the word line layer includes a polycrystalline silicon layer, a metallic stone material layer, and an anti-reflection layer. 8. The method of claim 1, wherein the first polycrystalline silicon to silicon oxide etching selection ratio is between 5 and 10. 9. The method of claim 1, wherein the second polycrystalline silicon to silicon oxide etching selection ratio is between 0.7 and 0.9. 10. The method according to item 1 of the patent application range, wherein the third polycrystalline silicon to silicon oxide etching selection ratio is greater than 15. ‘ Page 19 502403 6. Application scope of patent 11. The method according to item 1 of the scope of patent application, wherein after the second dry etching process, the polycrystalline stone layer has a T-shaped profile.