TW502163B - Device to increase the efficiency of processor-systems - Google Patents

Abstract

In order to increase the efficiency of processor-systems composed of many one-processors, which are used to maintain the cache-coherence inside the processor-system of the MESI-State model, it is suggested to expand the MESI-State model, which is limited to four states, with other states. The state situation inside the processor-system can be processed differently in this way and unnecessary Bus-access can be avoided. The operation-capacity that becomes available can be used to increase the performance of the system.

Description

502163 Repair troubles

Ⅴ. Description of the invention (1) The present invention relates to a device for improving the efficiency of a processor system in accordance with the preamble of item 1 of the scope of patent application. A large server is made up of a processor system with many single processors. The number of single processors may be, for example, 1, 6, 32, 64, 128, and so on. This kind of server is known as a 1 ^ 1) (system or NT system. Most single-system machines currently have a cache memory located in the chip. Therefore, it is also called the first stage on the chip (on chip first level) cache memory or first-level cache memory. In addition, other cache memories can still be configured outside the chip into a single processor. In the first other cache memory described above, There is a so-called off-chip second level cache memory or a second-level cache memory. In addition to the first- and second-level cache memories, other cache memories may be provided, such as It can be called third-level cache memory. In particular, other cache memories can be used in order to combine individual-or groups of single processors into a cluster. Today's standard processors only allow combinations of 1 to 4 single processors. If a plurality of additional such cache memories are respectively provided with, for example, 4 single processors, the above-mentioned large processing system can be constituted. These additional separate cache memories must therefore be cached. Take coherent This kind of coupling can maintain a hierarchical level, in which not only 4 single processors can be coupled to each other, but also multiple additional cache memories. As a result, a process with many single processors can be obtained. Machine system, which has great efficiency. 502163 Members are kindly requested to indicate whether the proposed amendment has changed the substance or whether the substance is allowed to be repaired. V. Description of the invention (2) As mentioned above, the processor system must be cache consistent. Here you can observe and explain the behavior of the bus. By analyzing the behavior of the bus, you can infer: what kind of state is this cache data block of the cache memory related to the bus action. If Knowing the state of these cached data blocks, you can note that the cache consistency has been formed or maintained within the processor system. The state description of the cached data blocks can be determined by the cache-protocol A known cache-protocol is the so-called MESI-standard. According to the MESI-standard, one of the four predetermined MESI-states is assigned to a separate cache data party. The 4 predetermined MESI-states are: MODIFIED (M), EXCLUSIVE (E), SHARED (S), and INVALID (I). These states can be expressed by encoding with two MESI-bits. The meaning of MODIFIED Yes: The cache block it belongs to is only contained in the cache memory, but it has to be rewritten. It is actually unknown in the rest of the processor system. The meaning of EXCLUSIVE is: the cache memory it belongs to The body block does not change, it is consistent with the content of the system-main memory. The meaning of SHARED is that the cache block it belongs to still exists in other cache memory and is still valid. The meaning of INVALID is: The cache block it belongs to is invalid or does not exist in the memory of TAG-RAM Φ ° The state of the cache block can be read-out or written by a single processor configured separately Into the process. This state can also be changed by interrogation (also known as Snooping) inside the system. The same can be explained by the outside member 502163 _ read the member ’s statement of #y in the y year A month whether the substance of the change is allowed to be amended. ° 5. The logical unit of the description (3) of the invention (for example, another single processor) Or second-level cache (ie, by external snooping) to change state. In each case at each point in time, separate cache memory blocks exist only in one of the four MESI-states described above. The correct functional description of the MESI-Protocol is, for example, bin / que ry shown below the Internet? Pg = q & kl = de & q = MESI & s earch = Search, Punktl, "Pentium: Neuerungen in de r X86 Architektur", It was recently changed or revealed in the documents belonging to the Internet on March 28, 1997. Its URL is: http://plweb.htu.tuwien.ac.at/pentium, Punkt 2.7.1 M, ESI.-Protocol 〇 One possible way to ensure cache consistency in a processor system with additional cache memory is to determine that these additional cache memories have all the large amounts of these other cache memories directly connected to them. Cache data box. Therefore, in all the exclusion process, it is necessary to perform and return such cache memory blocks related to the exclusion process to the connected single processor or its update on the cache memory. In terms of such an update requirement or its processing, the system power is required, and the system power cannot be used by the user as effective power. The efficiency of the entire system is therefore limited. The object of the present invention is to provide a technical measure whereby the efficiency of a large processor system can be improved, in particular. 502163 Would you please tell me whether the amendments mentioned in the year-end movie are approved or not? V. Description of the invention (4) According to the present invention, the purpose is to use the processor system with the first scope of patent application Features to achieve. Therefore, the additional cache memory can not only achieve simple cache memory block-management by the states M, E, S, and I, but also can be between additional individual cache memories or each single processor A combination of state management is implemented between cache memories. This combined state management is shown in the expansion of the MESI-state of the cache protocol of the extra cache memory, which has the advantage that the increased number of update requests is in the direction of other locations in the processor system It can be reduced because the expanded MESI-state can be determined in advance: the relevant cache data blocks required may not be located elsewhere in this processor system. The power consumption currently required for such an update requirement is therefore now available as the effective power of this processor system. The efficiency of the processor system can therefore be improved. In addition, in order to improve the efficiency of this processor system, the following situations are helpful. · Due to the extended MESI-state, some cases can be distinguished, in which some processes need to be performed, but these processes as a whole This can be achieved relatively quickly. For example, there may be situations in which a part of the processor system previously had an update requirement for additional cache memory, and a subsequent cache operation performed by the additional cache memory Hierarchical renewal needs are needed. For example, the relevant cache memory block can be assigned MESI-state I, but in this case it can be known that there is an extended MESI-state: the sender of the relevant cache memory block is not the previous one Corrected information. In this case, this extra speed is 502163. Members are kindly requested to show y years ^: The mentioned # 'it ~ Whether the substance of the change is allowed to repair iE .. ° 5. Description of the invention (5) The memory can be notified immediately Part of the processor system's activation of the previous update requirements: The above-mentioned MESI-assignment has been performed, although such an assignment has in fact been facilitated by subsequent cache memory in subsequent measures. This processor system therefore does not have to wait until the actual end of this update requirement has been confirmed, but can immediately start the next topic. Advantageous forms of the invention are described in the subordinates of the scope of patent application. The processor system is hierarchically structured in terms of its cache memory structure, so as to achieve a streamlined approach in the direction of these lower-level planes by intercepting these update requirements for the highest-level planes as possible. The largest demand for renewal. By selecting the appropriate MESI state, the number of required MESI-states can be kept as small as possible. When the number of MESI-states is as small as possible, the number of coding bits must be as small as possible when digitizing the MESI-states. As a result, hardware costs are reduced. The present invention will be described in detail below with reference to the drawings. The diagram is briefly explained as follows: Figure 1 Schematic diagram of the large processing system of the prior art. Fig. 2 State transition diagram of MES I-state of the prior art. FIG. 3 is a state transition diagram of the extended MESI-state of the present invention. The state table in FIG. 4, in which the system power can be saved when using the expanded MESI-state in FIG. 3 compared to the MESI-state used in FIG. Effective power. The 1st to 4th circles can help to understand the essence of the present invention. These diagrams do not require completeness, as long as the following description relates to the prior art and the present invention. Whether the substance of the amendment is allowed to be amended.

V. Description of the invention (6) The possible implementation forms are sufficient. Figure 1 shows two separate sets of single processors EP, which are connected to the additional cache memory CS via the respective first bus BS1. Each additional cache memory CS is connected to the main memory element MEM via a common second bus BS2. The second bus BS2 may also be referred to as a cache bus or a system bus. In addition to these additional cache memories on the second bus BS2, all types of I / O systems or connection systems can be connected to become further extended system components. In this embodiment, at least other systems are not connected in the figure. Therefore, the second bus BS2 may be referred to as a cache bus or a system bus, and the first bus BS1 may be referred to as a processor bus. The processor system shown in Fig. 1 is constructed in a hierarchical manner. From the perspective of the extra cache memory CS, the lower level is arranged in the direction of the first bus BS1 and the higher level is arranged in the direction of the second bus BS2. The single processor EP and the associated first bus BS1, between the first bus BS1 and the extra cache memory CS, between the extra cache memory CS and the second bus BS2, and the second bus The connection between the bank BS2 and the main memory component MEM is constituted in a bidirectional manner, so that data and codes and other required information can be transmitted in all directions between all components. The single processor EP has a cache memory inside and outside, which are not shown in detail in FIG. 1. The cache hierarchy (which consists of a single processor EP 502163, members are requested to indicate whether the substance of the changes mentioned in the month is permitted to be amended. V. The invention consists of two cache memories (7)) hereinafter referred to as the second Order cache remembers billions of bodies (SLC). As long as SLC is mentioned, the following refers to its single processor EP, which controls two cache memories. Conversely, whenever a single processor EP is mentioned, two cache memories belonging to this single processor EP, both internally and externally, will be mentioned. The abbreviation SLC is used in Figures 2 to 4. The extra cache memory CS is called the third-level cache memory (TLC). The abbreviation TLC is also used in Figures 2 to 4. The abbreviation TLC can then be used optionally in " extra cache memory CS ". The requirement between the extra cache memory CS and the single processor EP is called internal demand, and the extra cache memory CS and the main memory component MEM or CS and other coupled to the cache memory bus BS2 The requirements between components (for example, I / 0 components) are called external requirements. These commands (which initiate various requirements and their operation in the processor system and play a role in maintaining cache consistency) can be, for example: PREFETCH, READSHARED (RDS)? READEXCLUSIVE (RDE), RE ADMODIFIED (RDM), and WRITE (WR). These commands cause the transition of states, which are assigned to the relevant cache data blocks due to a cache-protocol operating according to the MESI principle in order to maintain cache consistency. The possible state transition diagrams are shown in Figures 2 and 3. The state transition diagram shown in Figure 2 is based on the following conditions, that is, the above-mentioned cache-protocol operates with 4 MESI-states. The state transition diagram shown in Figure 3 is based on the following conditions: The above-mentioned cache-rule 502163 Members are kindly requested to indicate whether # '0 £ mentioned in P, P, and P-Days-whether the substance of the change is allowed to be amended. V. Description of the invention (8) The operation is about the extended MES I-state. In the current situation this cache-protocol operates on 8 MESI-states. The state transition diagrams of Figures 2 and 3 can be seen from the viewpoint of the memory block of the extra cache CS. The cache memory of the single processor EP has a corresponding state transition_. The first 2_ is explained below. Starting from the state I of the relevant cache memory block of the extra cache memory CS (which shows: the registration of the relevant cache memory block is invalid), a kind of The internal RDS command finally changes the state from I to state S relative to this cache block. However, since the registration in this extra cache memory CS is invalid, the previous registration will be achieved by this extra cache memory CS. The other caches need to be queried to determine where the actual registration can take place. This process is also referred to as TLC-command below. After the TLC-command is completed, this login becomes a valid general login and exists in this additional cache CS. This situation also applies in the same output state (in this case, instead of using the RES-command) when performing a Prefetch-requirement (provided that this possibility is often set). In the table below the state transition diagram, the settings of the four possible states shown in the table on the left. Next to it are the possible states for SLC in each case, and for TLC the various possible states are also shown. Since this observation started with TLC, these states are consistent with the states given in the first row of this table. If the following is always not for the sake of simplicity -10- 502163

Yu Yue The repair is being mentioned V. Description of the invention (9) When explicitly set, the respective cache memory when setting the MES I-state box is related to the relevant cache memory. As can be seen from the first column of the above table: When state I in TLC, state I also has an advantage in SLC. This is because in this embodiment, the number of TLCs (not necessarily the actual registration amount but the information amount) is greater than the registration status of the connected SLC. The result is that in the SLC, only the same state or the lower state is always produced. Conversely, the state 値 in TLC is always equal to or greater than the state 中 in SLC. An exception can result in a state of Exclusive, because such a state is basically only meaningful if at least an attempt is made to modify the relevant entry. Since the TLC does not know whether the required login has actually been modified at the time of Exclusive-requirement, this TLC still starts with "login has been modified" and this situation. At the time of Exclusive-requirement, the actual status in the SLC is therefore also Can be M. This state is irrelevant, because the Modify-requirement is an Exclusive-requirement in the end, only "this login has been modified" is clear. If the login in the TLC has been marked as S and in this TLC If an RDS command has been issued for this type of login, the MESI-state of this login will not change. On the other hand, the login in the SLC is removed after this login is saved by the TLC. The MESI-state is relative to this login in the SLC. The classification is achieved by the single processor EP it belongs to. This is irrelevant to the TLC, because the login itself does not change, so it is still valid as a whole. The TLC will be noticed when it is changed, because previously This kind of registration must be loaded into the E state or M state through the relevant single-11-502163 V. Invention Description (10) Processor. The right to modify is independent of the RDS command or Prefetch- command. In state S After recording to the TLC, compared to this registration in the SLC (ie, general registration), one of the MESI-states I or S used by the related registration can actually be kept at a lower cache level This situation is shown in the second column in the table below on the left. The above principle also applies to various subsequent considerations. 5 This point will not be described in detail. 〇 之

The command RDE or RDM requires an exclusive login by the TLC. This has nothing to do with whether the previous registration in the TLC has detected this state I or S in advance, and then the registration in the TLC is marked as the state E. Based on the above, in the SLC, for this type of registration, it is actually finally assigned to one of the states I, S, E or M. This is shown in the third column in the table on the left.

Each command RDE or RDM will generate a TLC-command, that is, BUS-RequesU bus-demand. This is because TLC must pay attention before handing over this kind of registration: it is related to the lower cache level of the processor system. The TLC starts, and this type of registration is marked with status I. If the SLC requires the TLC to log in with the command RDE or RDM and then modify it, it must be noted that this modified login is written back to the TLC using the WR- command. The TLC therefore marks this modified entry as state M. After the required login has been modified, the required SLC can maintain such a modified login and be characterized as such. It can also write back such registrations. Once this writing back, the level of the status of such registrations is reduced and this -12-502163 is annoying

The workshop is mentioning the fifth of the invention description (11) For example, only state E. If such a registration is required in the SLC or it needs to be removed, such a registration can be assigned to the state S or I of the SLC in a corresponding manner. This is possible because state M is the highest in this sequence before states E, S or I. The aforementioned situation is shown in the fourth column in the lower left table in FIG. 2. If an RDS-, RDE-, or WR-command is issued to the TLC relative to the associated cache block with the state M, the state of this registration in the TLC will not change. If an RDM-command is issued to the TLC, the state of the related registration at the position of the mark M in the advantageous embodiment of the present invention can be the mark E. This has the advantage that in some cases this cache block will not be read out in an unnecessary way. If a single processor EP configured in a lower cache level requests an cache block with RDM-requirements, the TLC knows that this cache block will actually be changed. This kind of information is part of the RDM-requirements. If the cache block does not change, then the cache block is requested with the RDE- command. In other words, if this cache memory block is requested by an RDM-command, such a demanded single processor or its own SLC will eventually have the latest data Exclusive. If it is found that this is the case, then instead of searching for the data in the TLC when accessing the data, it immediately searches in the connected SLC at a correspondingly faster rate. A second table is shown at the lower right of Fig. 2 in which the above-mentioned commands are performed again. In addition to these commands, there are other main actions. In these commands related to TLC or SLC, these actions are related by -1 3-

502163 The commendation committee I stated clearly that the year aF of P: whether the amendments to the revised version of lij were allowed to be modified. V. Description of the Invention (1 2) The possible different output states of the cache memory block begin. The same table with the same meaning is also called a state transition diagram in FIG. In Fig. 3, a state transition diagram which is expanded relative to the state diagram in Fig. 2 can be seen. The state transition diagram in Figure 3 has extended states SI, ES, MI, and MS. States II, SS, EM, and MM start from states I, S, E, and M in Figure 2 and enter the set sequence. The first letter of the state notation is related to the state in the TLC, and the second letter is related to the state in the SLC or the state in the lower cache hierarchy. In this embodiment, this login EM is selected as the registration for the state description of the cache memory block at the location of this login EE, because, for example, the state SI or SS is started by the TLC when the RDE-command arrives. In terms of the single processor EP, this TLC must therefore calculate: When the single processor EP needs a cache memory block Exc 1 us i ve, it can also modify this block. Since the TLC has to maintain more than this number of state conditions in the system, this TLC registers this new situation as EM. If the relevant cache memory block is also required by the single processor EP with the RDM command, this situation is clear when the required cache memory block is modified. Such a registration relative to the required cache memory block is therefore logical. On the whole, the state transition picture can be optimized in the above-mentioned way, because the state situation does not have to be displayed, and the possible way for its data technology encoding is to provide an extra bit. Eight states can be encoded by three -14- 502163 V. Invention description (13) bits. More than three bits are required for more than nine or nine states. When the single processor EP has an Exclusive-Requirement (RDE command) for the cache memory block, it is not necessary to modify the cache memory block as described above. A single processor EP in need has an associated cache memory block Exclusive and finally enables such processing to achieve all possible changes. This EP enables the cache block to be transferred to, for example, another location or excludes this block. In the first case, the TLC for the relevant fast memory block must maintain this state ES, and in the second case, it maintains EI. The TLC includes all of these cases in the state EM5 This is because it ensures that if the relevant cache memory block is turned to the relevant single processor EP, then each of the relevant cache memory blocks can be maintained Happening. The foregoing cases are shown in the fifth column in the table on the lower left of Figure 3. The fifth column in the table on the lower left of Figure 3 corresponds to the third column in the table on the lower left of the second garden. In addition, columns 1, 3, and 8 in the lower left table of Figure 3 in the sequence shown correspond to columns 1, 2 and 4 in the lower left table of Figure 2. The above principles can be used correspondingly. Since the principle of the state transition diagram of Figure 2 can also be used in the state transition diagram of Figure 3, the description of the state transition diagram of Figure 3 is basically limited to the description of different points. When the respective state transitions and corresponding commands exist, refer to Figure 3 to add some states. According to the state transition diagram in Figure 3, one TLC can have two Shared 502163. V. Description of the invention (14) Members are requested to indicate whether the substance of the amendment A mentioned in the year ^^ Θ is allowed to be modified. An Exclus ive state and three Modi fi ed states. At the time of Prefetch-requirement, it was clear that a kind of registration obtained in TLC only existed in the relevant TLC. This situation is related to the state SI. If such special circumstances (other special circumstances can be given in addition) can be marked separately, then there is no need to ask other planes in the requirements based on such registration. The capacity is then available on the first bus BS1 side, and these capacities can be used by the single processor EP for other operations in order to improve the efficiency of the processor system. The state SI is indicated in the second column 2 in the left table of FIG. 3. In the Exclusive-state, an additional state ES is generated relative to the TLC. If an entry in TLC Exclusive is read by SLC Shared, this state ES can be maintained, for example. In this case, the TLC can maintain the state E and find the cache memory block in the state E of the SLC for labeling as the state S. The TLC then knows that the state in the SLC can actually be just S or I. The status may not be M or E, because no enquiries on such rights have been issued. This registration is therefore unchanged under all circumstances. The advantages of this method will be described with reference to FIG. 4. The various possible states for the SLC plane are shown in the fourth column of the table at the bottom left of Figure 3. In addition to the state MM, the expanded states M1 and MS are shown in Figure 3. If the SLC has obtained the TLC Exclusive login, modify it and write it back to the TLC with the WR command, then this TLC uses this state MI for this fast -16 »502163 repair

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The institute is mentioning Ⅴ.5. Description of the invention (15) Take the memory block. SLC has ruled out such logins and is no longer valid there. In the same case, when the TLC has a modified login (ie, for such a login in the state MM), the TLC arrives and writes this login again with the WR- command. The TLC therefore occupies the state MI. In this case, the TLC knows that the relevant entry can no longer be located in the SLC, for example. This is indicated in the lower left column of Figure 3. Finally, an extended state MS will still be generated, which is generated regardless of whether the state I or IT is already registered in the " SLC. This state MS is generated when read by SLCShared. But just like those mentioned many times above, the SLC can cause a state set logically down after the corresponding action, so that after the state description MS, there can be some states I or S for the relevant SLC . The above situation is indicated in column 7 in the table on the lower left of Figure 3. The advantage of the expanded cache state is that the TLC can have a deep understanding of the state inside the processor system, which can, for example, further guide or intercept these requirements for a single processor EP as appropriate. " Intercept " can be achieved because the needs of the TLC itself can be discussed. The load on the processor side can therefore be reduced. A single processor EP can accomplish some expanded tasks to increase the effective power of the processor system. Section 4_ shows some situations where some of the requirements on the processor side can be omitted. Two external orders can be considered as examples. As mentioned earlier, the external order -17- 502163 repair trouble I invite the hand committee member IS internal λ content A April tl The training institute is mentioning V. Description of the invention (16) is a command to the TLC from the bus side of the system . One of the external commands is an RDS command and the other is an RDE command. In Figure 4, the lower part is the case of the expanded MESI-state, and the upper part is the case of the current four MESI-states. When the cache memory block in the TLC has state I or 11, the result in both cases is the same. No action is taken in either case. In both cases, there is a so-called MISS-case, that is, it does not transmit any information. If the login status related to the RDS command or RDE command is marked as S in the TLC, there is no need to take any action in the RDS command in the 4 state modes or the extended state mode. This is because the TLC The registration is already S. Compared with the extended state mode, whether S (J " state SI or SS is actually set in advance " is no different. In the RDE command, there are four state modes for Both TLC and SLC must note that the state of this allocation to the relevant cache memory block changes from S to I. The relevant cache memory block is therefore only required for this side of the single processor EP. This will cause a load on the processor bus, so it cannot be used for other tasks temporarily. In the extended state mode, the demand on the processor side for the RDE command is usually not needed. For example, if it is found When the status is SI compared to the required registration in TLC, then you do n’t need to pay attention to the TLC view: the related SLC changes its status perception of the relevant cache block in status I. TLC already knows: related The cache memory block is in a single place-18- 502163 The annoying member expressly stated ^ One year Ap: whether the revision JE ·· has the substance of the book whether the amendment is allowed to be amended. V. Description of the invention (17) The machine side has been classified as I. In this case, the processor side is therefore no longer subject to additional load. Finally, more processor power can therefore be used for other tasks. If the registration related to the RDS command or RDE command is E in the TLC , Then in the 4 state modes and the RDS command, you notice that the “relevant cache memory block must be assigned to this state in the TLC and in the lower cache level S " before you check: to the relevant speed Whether the temporary new data of the memory block does not exist in this processor system anywhere. This is because a cache memory block that is required in an exclusive manner can be later used in the corresponding other actions. Other required units are introduced into one of states M, E, S, or I. In this case, the processor side will not be effectively loaded. The same applies to the RDE command. The difference is that The SLC unit must be introduced in order to represent the relevant cache memory block with state I. Here the processor side will not be effectively loaded either. The power of the processor system increases with the expanded state mode This can save non-effective power. If in this expanded state mode a cache memory block has been allocated to the state ES and an external RDS command has been executed relative to this cache memory block, then In the direction of the lower cache level, other promotion actions can be omitted for TLC. According to SLC, it can be known that the relevant cache memory block has entered the state s there. Because the relevant cache memory block is in The lower cache level has entered the state S, then we can know that: in the lower cache level, the relevant speed is -19- 502163. Members are kindly requested to indicate p only. i £ -o V. Description of the invention (18) A modi fi cat ion phenomenon does not occur when taking memory blocks. Therefore, actual data cannot be obtained from the lower cache side. Therefore, it is not necessary to check whether the actual data exists or not to note that the change of status has been achieved. In the TLC and the existing external RDE commands, the state ES starts from the above. According to the above, no new data can exist. Just note that "the cache memory block in the lower cache level is represented by I." Therefore only There must be a need for simplicity on the lower cache level side. In general, the non-effective power of this processor system is smaller than that in the four state modes, and it is necessary to additionally check in advance: whether new data may still be available Existing. Especially important is the potential saving of the cache memory block in TLC when it enters state M. Compared to the above 4 state modes (where this Modified-state is not further divided), all of the " The measures must always be applied to the two commands "Applicable to RDS Command and RDE Command" in order to check whether there is still new data before the relevant cache memory block is indicated by the state S or I. The above has been The extended state mode allows this Modified-state to have differences. In this embodiment, this Modi fied-state is divided into states MI, MS, and MM. When the external RDS command points to TLC, the In the case of MI and MS, it is not necessary to require each side of the lower cache level similar to the previously described. When the RDE command exists, at least you do not need to check: whether new data exists. In the direction of the lower cache level Some of the simple requirements are sufficient, so it should be noted that the relevant cache memory in the lower cache level is -20- 502163. Members are kindly requested to indicate whether there is any change in the substance of the amendment proposed by Λ, and whether the amendment allows the amendment. Description of the invention (19) The state of the block is changed to I. In Figure 4, these positions (where the above-mentioned measures are not needed at all or only limitedly required) are indicated by exclamation marks. For these positions, this process can be saved Non-effective load of the machine system. Explanation of symbols CS cache EP single--processor BS1, BS2 bus SLC second and second order cache ΙΑ memory mm TLC third and third order cache memory 0S MEM Main memory mm body assembly-21-

Claims (1)

502163 Repair annoyance, please ask Kui Wei, a member, ignorance, change the actual quality k ft year f A Xinyue ancient 6. Patent Application No. 891 03056 "Apparatus for Improving the Efficiency of Processor System" Patent Amendment (December 1990) 6. Application for Patent Scope 1. A device for improving the efficiency of processor system, this processor system It is composed of many single processors and multiple cache memories. The cache memories are set to maintain cache coherence with each other in order to process a cache-protocol that operates according to the MESI-standard. , Its characteristic is: This cache-protocol operated in accordance with the MESI-standard must be structured so that at least a part of the MES] ^ status is set into multiple displays 以便 so that at least they can be displayed separately: The MESI-state of the relevant cache memory (CS), the MESI-state of a single processor (EP) connected to this CS or the MESI-state of another cache memory (CS) connected to this CS. 2. The device according to item 1 of the patent application scope, wherein the processor system has a plurality of single processors (EP), at least a part of which has the first cache memory or the first and second cache memories. The processor system has an additional cache memory (CS), which is arranged at least in the first layer and connects to the individual-or a group of simple or mixed single processors ( EP) or connect other extra cache memory (CS). 3. The device according to item 1 or 2 of the patent application scope, wherein a plurality of display screens are used to display MESI-state combinations such as II, SI, SS, EM, ES, MI, MS or MM. -twenty two -