TW501232B - High density plasma-fluorinated silicon glass process stack and method of manufacture therefor - Google Patents

Abstract

The present invention provides a semiconductor device and a method of manufacture therefor. In one embodiment, the semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has a dielectric layer encompassing it. The semiconductor device also includes a barrier layer, comprising silicon, located on the metal feature and isolating the metal feature from the dielectric layer. Thus, the barrier layer tends to inhibit the diffusion of the dielectric layer into the metal feature. Another embodiment introduces a capping layer located over the dielectric layer and a metal feature located over the capping layer.

Description

501232 _Case No. 90108007 // Day__ V. Description of the Invention (1) Technical Field of the Invention The present invention generally relates to a semiconductor device, and more specifically, relates to a metal feature on a semiconductor substrate. A semiconductor device having a silicon-rich barrier layer thereon. BACKGROUND OF THE INVENTION Current semiconductor technology, as is well known, has been continuously reducing the size of its components. Included in this reduction in size is the reduction in distance between metal interconnects at different metal levels or at certain metal levels. Due to the overall reduction in device size and the current use of inter-level dielectric materials, RC delay has become a problem. The problem with RC delays is the result of inadvertent capacitive coupling between the metal interconnect and the interlevel dielectric material used. Therefore, in an attempt to prevent the RC delay problem associated with the reduction in device size, the semiconductor manufacturing industry is currently moving towards the use of low dielectric constant materials, such as fluorinated silicon glass (FSG), as interlevel dielectric materials. The FSG interlayer dielectric material will reduce the capacitive coupling between electrical runners, thereby reducing the RC delay of the circuit and providing a faster integrated circuit. However, there are several difficulties in integrating FSG into conventional integrated circuits. One of the difficulties is the instability of fluorine in FSG dielectric materials. Some fluorines are bound in the F S G dielectric material, while most fluorines are only loosely bound or not bonded at all. Unfortunately, loosely bound or unbound fluorine can move when the integrated circuit experiences large high temperature changes. Such large high temperature changes typically occur during the manufacturing process, but they also occur when using integrated circuits. Moreover, the movement of fluorine in integrated circuits can cause two general problems.

O: \ 70W0290.ptc Page 6 501232 Ά 90108007 Jo, q Amendment V. Description of the invention (2): f Ϊ ί ίThe unconnected fluorine attacks the dielectric material located between the FSG layers. The second is general: Included, when metal is stacked occur. When the metal stack contains materials:: '2! ° ί to form titanium fluoride, 4 has extremely poor adhesion, 4 miscellaneous f f, the titanium metal stack will buckle and separate from the FSG dielectric material, causing more problem. In theory, gold materials containing different materials: ® will also encounter similar problems as titanium stacks. Another problem caused by the movement of fluorine in FSG dielectric materials is fluorine.

U ί 属 ί Occurs when ΐ is combined. This interconnection is usually used as a semiconductor F m feature. Fluorine will try to combine with Minghua to form fluorinated Ming Uj 连 lian 2 of 2 which has a negative impact in nature. It is conjectured that when Qi is combined with other metals in a conventional integrated circuit, the same result will occur in%. Integrated Circuits Another problem that semiconductor technology currently encounters today is not flattening the surface of the material. a ίΐΓίϊτΓ: It ’s important. But what about speaking with today ’s technology? t = the size of the device, its importance is even more important than it = 桎 small order heat ^, to achieve an effective flattening to special in this sub-micron ^. It is important to follow the correct lithographic process. As mentioned above, the current semiconductor technology is to deposit a layer of a material, such as FSG, on a semiconductor wafer. Generally, the dielectric system is deposited using a high-density electrical assembly method in conjunction with isotropic J. This isotropic component is quite obvious in inductors and so on; these wide features, such as capacitors, and other features such as gate structure and product, are slightly left out. Isotropic components will only leave small protrusions. , Which ... both are small to T ± denier

501232-^-M08007 July // Said V. Description of the invention (3) The first (C MP) method can surface the layer Rigu Ping II # and effectively flatten it, but presents a completely different problem. ^ __ However, because the wide feature is taller than the surface on which it is located, the deposit: the effect of isotropic facets on this feature = anomaly. The problem is that the typical Mp ^ table: ‘including flattening of the raised area occurs ... likely, the speed f… will be in the material of the entire wafer… production: υ properties and will affect accuracy & device performance and device yield. And: the difference in pattern density between integrated circuits of the same type will lead to different polishing speeds, making manufacturing more difficult and expensive. The semiconductor manufacturing industry has developed several methods in the past that attempt to minimize the effect of pattern density during CMP. One of the methods is to change the "CMP method", such as the following forces (d0Wn f0rce), carrier speed and throw hardness. Changing the various CMP method variables does help; but unfortunately, there is a trade-off between the 'grain (d i e) and the overall wafer uniformity when these variables are changed. Moreover, the changed variables do not affect the polishing speed. Another method that has been tried is to deposit "pseudo" metal features to even out the pattern density. However, the effectiveness of this method depends on the characteristics of the circuit configuration and the deposition profile of the dielectric material used. Also, "Pseudo" technology is time consuming and costly. ^ m Therefore, what is needed in the art is a semiconductor device that uses an interlayer dielectric containing a low dielectric constant material such as fluorinated silicon glass (FSG), which does not encounter and disassociate with fluorine during large temperature changes There are related issues. this

501232 _Case No. 90108007 / February, / Days Amendment_ V. Description of the Invention (4) The technique also requires a flattening method that does not encounter the polishing speed differences and other polishing problems associated with previous techniques. SUMMARY OF THE INVENTION To make up for the shortcomings of the prior art discussed above, the present invention specifically provides a semiconductor device including metal features and a method of manufacturing the same. In an advantageous embodiment, the semiconductor device includes a dielectric layer deposited on a metal feature. The dielectric layer includes a substance that is permeable to metal features. To prevent this penetration, the semiconductor device includes a barrier layer on the metal feature to isolate the metal feature from the dielectric layer. The barrier layer can inhibit the penetration of the material of the dielectric layer into the metal features. Another example is to add a cap layer over the dielectric layer and a metal feature on the cap layer. In an alternative embodiment, the barrier layer, the dielectric layer, and the cap layer are all deposited in-situ in a single deposition chamber. Therefore, in one aspect, the present invention provides a semiconductor device having a barrier layer on a metal feature of the semiconductor device. The barrier layer enables a low dielectric constant (K) material such as fluorinated silica glass (F SG) to be reliably used to reduce the RC delay accompanying the integrated circuit. In another aspect of the present invention, the barrier layer is silicon oxide-rich and the dielectric layer is a dielectric layer having a low dielectric constant, such as fluorinated silicon glass (FSG). The barrier layer and the dielectric layer can be formed in the presence of argon, oxygen, and silane gas. The cap layer may contain a substance similar to the barrier layer and inhibit the dielectric layer from penetrating into the metal features above the cap layer. In an advantageous embodiment, the cap layer comprises a silicon-rich oxide. Moreover, in an alternative embodiment, the capping layer may be formed in the presence of argon, oxygen, and petrolane gas. In another aspect, the metal feature is a metal wire including an inscription. And, in another

O: \ 70 \ 70290.ptc Page 9 501232 _Case No. 90108007 > Year / Month / Day Revision_ V. Description of the invention (5) On the one hand, there may be many metal features on the semiconductor substrate, and the barrier layer may be Each of the plurality of metal features is isolated from the dielectric layer. However, those skilled in the art will understand that metal wires may contain other similar substances. In another specific example, the present invention includes an integrated circuit. The integrated circuit, in another specific example, may include a transistor and metal features used as an interconnect and electrically connected to the electronic crystal to form the integrated circuit. Also encompassed by the present invention is a method for planarizing interlevel layers on features on a substrate. In a specific example, the method includes depositing a dielectric layer on a feature, wherein the method of depositing has an isotropic etching composition that causes anomalies not to form on anything other than a wide feature. In another specific example, the dielectric layer may be a fluorinated silicate glass deposited using a high-density plasma method. The method further includes patterning the photoresist to expose a significant portion of the abnormality, etching the exposed portion to leave abnormal residues, and generally planarizing using a conventional CMP method to leave a substantially flat surface. In another representative example, the supplier is a semiconductor device having metal features on a substrate of the semiconductor device. The semiconductor device includes (1) a dielectric layer, which may include a metal feature permeable therethrough, (2) a silicon-rich barrier layer between the metal feature and the dielectric layer, and (3) a cap on the dielectric layer Layer and (4) a metal layer on the cover layer, wherein the cover layer can inhibit fluorine from penetrating into the metal layer. Moreover, on the other hand, the barrier layer, the dielectric layer, and the cap layer may be formed in situ by a high-density plasma. The preferred and alternative specific examples of the present invention have been summarized quite extensively above, so those skilled in the art will know more about the detailed description of the present invention below. Additional features of the invention that form the subject of the patentable scope of the invention will be described below.

O: \ 70 \ 70290.ptc P.10 501232 Case No. 90108007 Rev.//////-V. Description of the invention (6) Those skilled in the art should understand that they can easily use the disclosure The concepts and specific examples serve as a basis for designing or modifying other structures to achieve the same purpose of the present invention. Those skilled in the art should also understand that this equivalent construction does not depart from the spirit and scope of the broadest form of the invention. Brief description of the drawings For a more complete understanding of the present invention, please refer to the following description with reference to the accompanying drawings; the drawings are: FIG. 1 shows a cross-sectional view of a semiconductor device in the middle stage of manufacturing, including a barrier formed on a semiconductor substrate Figure 2 shows a schematic diagram of a low pressure inductively coupled HDP chemical vapor deposition (CVD) reactor; Figure 3 A shows the semiconductor device shown in Figure 1 after depositing a substantially flat dielectric layer on metal features and barrier layers; 3B shows the semiconductor device shown in FIG. 1 after an abnormal dielectric layer is deposited on a metal feature; FIG. 3C shows the semiconductor device shown in FIG. 3B after a photoresist material has been deposited and patterned; FIG. 3D shows FIG. 3C The semiconductor device shown in FIG. 3A shows a situation in which an angular residue is left after removing an abnormality ranging from about 75% to about 99%; FIG. 4 shows the semiconductor device shown in FIGS. 3A-3D after a cap layer is deposited on a dielectric layer; FIG. 5 shows a completed semiconductor device after conventional deposition of a second metal feature; and FIG. 6 shows a cross-section of a conventional integrated circuit that can be manufactured according to the principles of the present invention.

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V. Description of the invention (7) Plan view. Correction Detailed description Please refer to FIG. 1 first, which shows a cross-sectional view of a semiconductor device 100 in the middle stage f Ϊ 2 during manufacture. Also shown in FIG. 1 is a metal feature 110 located on a semiconductor substrate 120i. The metal feature 110 may include aluminum, which is a metal wire that connects different bracketed elements in the device 100. Generally speaking, these metal 11 features 1 1 0 may also include a conventionally formed titanium / titanium nitride (T i / T i N) layer i 1 o a, 1 1 0 b. It should be noted that the semiconductor wafer substrate i 2 o may be any substrate located in the semiconductor device 100, including the wafer itself or a substrate located above the wafer. It should also be noted that the semiconductor device 0 0 0 is not limited to 3 metal features and a single metal feature 1 1 0 or an additional plurality of metal features 1/0 may constitute a semiconductor device 100. Formed on the metal feature 110 is a barrier layer 130, which in a favorable embodiment contains a silicon-rich oxide. The barrier layer 130 can be deposited using the conventional induction coupled high density plasma (HDP) method. Please refer to Figure 2 briefly, which shows the conventional low pressure inductively coupled HDP chemical vapor deposition (CVD) reactor 2000. The HDP CVD reactor 2 0 0 typically includes a chamber 210, an induction coil 2 2 0, an upper RF power source 2 30, a side RF power source 2 40, and a lower RF power source 2 50. Please turn back to FIG. 1 and refer to FIG. 2 again. In order to form the barrier layer 130, the semiconductor device 100 is generally placed in the chamber 210 of the HDP CVD reactor 2000. Then, about 1500 watts of power are passed to the upper power source 230 and about 2500 watts of power are passed to the side power source 240, while a mixture of argon, oxygen, and silicon gas flows on the surface of the semiconductor device 100. Furthermore, after the HDP method has begun, a limited amount of power can be passed to the lower power source 2 50 to help fill the metal

O: \ 70 \ 70290.ptc Page 12 Amendment No. 3 90108007 V. Description of the invention (8) The gap between features 1 1 0. It is too early to cut the four corners of the metal feature 110, = 2I electric f source, and it will be used. The result is better and thicker argon d 4), but other gases can also make the wall layer 130.本 \ 本 、 / 蓺 度 ^ is about 50 nm and the refractive index is about 1.51. The design of the deposition parameters can be changed. As long as the support and the degree of change are all in line with the device / 〇0 in the V * quality 612 ′, the result is the situation after the semiconductor device shown in Figure 1/30. : Electric: = Shen; ^ Deposited by HDP method. The dielectric layer 31 〇a is preferably two persons / body; ^ Ϊ ίΐ'1 璃 (:; G) and is deposited to a thickness of about two and has a fold of θ. After entering the HDP CVD reactor chamber 210, the electricity, 7f 24 million 9 to 9 power to the upper power source 230, about 300 watts of power to the side

Alas. The mixture flows over the surface of the semiconductor device 100 in time. The gas mixture of Wei Yi to form the dielectric layer 3 1 0 a is si Η 4 and S i F Lei ϊ 而 η and: The dielectric layer 31 〇a uses the dielectric HDP located on the feature 1 1 〇 square it / supply Technical deposition of anomalous, substantially flat surfaces. However, the accompanying dielectric layer 310b causes an abnormality 3 2 0 as shown in FIG. 3B. Because of the isotropic etching composition of # 科 $ 1 q P method, the abnormality 32 will not be formed in a small '. However, the anomalous 3 2 0 will still form on the wide feature 1 1 〇

501232 銮 90108007 Amendment V. Description of the invention (9). The width of the anomaly 320 is generally larger than the width of the anomaly 320. The characteristic is generally a feature that is wide enough to produce a substantial anomaly; also ^. Wide CMP and non-flat wall tables generated after not using the methods covered by the present invention will result in the representative width of such features being wider than about 500 nm, and smaller widths will result in demand. Use the method currently described to reach it again. The abnormality of the brantan surface is also wide to substantially flat within the scope of the present invention. Conversely, small features, such as features 3 丨 5 shown in Figure 3B, are left in H without abnormalities or only small and sharp. Features such as the small process f method is proud. m & These summary tender Q 1 R — θ +. Corner characteristics. Because these small features 3 1 5-generally have a high aspect ratio, they can be removed by conventional CMP methods without affecting the desired flatness, and it does not need to be done, 丄》 rO Mountain, you. 7 Further reported easy nickname. Therefore, the “subsequent patterning and rice carving process” as provided here is not practical or necessary to achieve a substantially flat surface. It should be noted that ^ substantially flat table = is a surface on which the subsequent photolithography process can be performed. Confirmation Please refer to FIG. 3C, which shows the deposition of a photoresist material 33 °. The material 330 has been patterned so that a considerable portion 34 of the abnormality 320 is exposed. In general, a photoresist is exposed by using a mask having an aperture width smaller than the width of the abnormality 320. Then, the exposed portion 340 is subjected to conventional etching. For example, plasma exposure, reactive ion etching, or the like can be used to remove the exposed portion 340 of 3 2 0. In a preferred embodiment, the anomalous 32 0 between 75% and about 99% is removed by contact etching and etched to the dielectric layer 31 3 5 0. After the last name is engraved, the remnant 3 6 0 is preferred. As shown in FIG. 3D, the abnormal residue is 36. Angle or protrusion of residual aspect ratio. Shown specifically

501232 Amendment No. 90108007 V. Description of the Invention (10) In the example, the width of the residue is less than about 100 nm. Then, the dielectric layer 3 1 0 b is planarized. Due to their high aspect ratio, the residue 36 can be easily removed using a conventional chemical mechanical planarization (CMMP) method to obtain a substantially flat surface. So 'if necessary, planarization is done while at least substantially reducing the difference in polishing speed and other polishing problems that accompany previous techniques. After the dielectric layer 310a or 310b is deposited and the anomaly 320 (FIG. 3B) is removed, if necessary, a capping layer 410 may be deposited over the dielectric layer 310a. In an advantageous embodiment, the cover layer 4 10 contains a substance similar to the barrier layer 130, such as a silicon-rich oxide. Similar to the deposition of the barrier layer 130 and the dielectric layer 31 oa, 3 1 Ob, the cap layer 4 1 0 is generally deposited by the HDP method. Moreover, the cover layer 4 10 is preferably deposited to a thickness of about 40 nm and has a refractive index of about 1.51. The cover layer 410 is preferably connected to the upper power source 2350 and 2500 watts to the side power source 240 by 1500 watts, and at the same time, the mixture of argon, oxygen and silane gas flows through the semiconductor device. 〇〇〇 While deposited. The HDP method is not the only method available. For example, other conventional CVD and PVD methods can be used. However, when using another non-conformal deposition method, the cap layer 410 must be subjected to standard chemical mechanical planarization (CMP) before the semiconductor device is completed. Because the barrier layer 130, the dielectric layer 310, and the cap layer 410 can be deposited by high-density electropolymerization, all three layers can be deposited in-situ in the same deposition chamber. In-situ deposition is usually accomplished by placing a partially completed semiconductor device 100 (Figure 1) into the HDP CVD reactor chamber 210 and changing the amount of radio frequency (RJ?) Applied, the location of the electrical power, the gas mixture, and the temperature. The semiconductor device shown in FIG. 4 is obtained by the deposition. Further, the layers 130, 310, and 41 are formed in situ, with the following features having a width less than about 5 0 0 n m as discussed above or a thickness such that the η D p method

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Correction: When f forms an abnormality that needs to be removed by CMP, especially when ΐΚΚίΐ is used, the method is isotropic ... Lei; ί the need for a frankization step. The barrier layer 130, which is deposited in situ in a single processing step, is highly needed, which saves money and reduces the number of guarding steps. Therefore, local methods may provide additional benefits of the invention. Γ ΐ, FIG. 5, which is not a semiconductor device 50 completed after the second metal feature S10 and Ti / TiN are laminated. . The completed semiconductor device includes an n / TiN layer 52a, 52b on a semiconductor substrate 530 and a barrier layer 54 on a metal feature 520. Located on the barrier layer 540 are a dielectric layer 55 and a cap layer 56. As shown, the barrier layer 5 ^ 0 isolates the metal feature 520 from the dielectric layer 55o and inhibits fluorine from the dielectric layer 55o from penetrating into at least a portion of the metal feature 520. Similarly, the capping layer 56 prevents the penetration of a substance such as fluorine from the dielectric layer 5 50 into the second Ti / TiN layers 510a, 510b. Independent test and please briefly refer to FIG. 6, which shows a cross-sectional view of a dining knowledge integrated circuit 600 that can be manufactured according to the principles of the present invention. Integrated circuits can include BiCMOS devices, bipolar devices, EEPROM devices, including transient EPROMS or any other type of similar device. Figure 6 also shows the components of the integrated circuit 600, including a transistor 610, a metal feature 520, a wall layer 5 40, a cap layer 560, a second metal feature 510, and a dielectric layer 550. The gold feature 5 2 0 and the interconnect structure 6 2 0 form a part of the interconnect system, and its transistor 610 forms an integrated circuit 6 0 0. Also shown are the conventional 6 2 3, 62 5, the source region 6 33 and the drain region 63 5, all located on the substrate 63 /.

501232 _Case No. 90108007 Rev. 8/0 / 0_ V. Description of the invention (12) Although the invention has been described in detail, those skilled in the art should understand that they do not depart from the spirit of the broadest form of the invention Various changes, substitutions and changes can be made under the scope.

O: \ 70 \ 70290.ptc Page 17 501232 Case No. 90108007 YY month Y _ correction diagram brief description element symbol description 100 semiconductor device 110 metal feature 120 semiconductor substrate 130 barrier layer 200 reactor 210 chamber 220 induction coil 230 Upper radio frequency (RF) power source 240 Side RF power source 250 Lower RF power source 310a, 310b Dielectric layer 315 Small feature 320 Anomaly 330 Photoresist material 340 Exposed part of anomaly 350 Field height 360 Anomalous residue 410 Cover layer 500 Semiconductor device 510 Second metal feature 520 540 560 610 623,625 633 Metal feature barrier layer cover transistor basin source area 5 3 0 semiconductor substrate 5 5 0 dielectric layer 6 0 0 integrated circuit 6 2 0 interconnect structure 6 3 0 Substrate 6 3 5 Drain

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Claims (1)

501232 _Case No. 90108007 Rev. 0/0/0 of the household_ VI. Patent application scope 1. A semiconductor device with a metal feature on the substrate of a semiconductor device, comprising: located on the metal feature and including a feature that is permeable to the metal feature A dielectric layer of the material; and a silicon-rich barrier layer between the metal feature and the dielectric layer. 2. The semiconductor device as claimed in item 1 of the patent application, wherein the silicon-rich barrier layer isolates the metal features from the dielectric layer and inhibits substances from penetrating into the metal features. 3. If the semiconductor device in the first scope of the patent application includes a cap layer on the dielectric layer and metal features on the cap layer, the cap layer will inhibit the substance from penetrating into the metal features on the cap layer. . 4. The semiconductor device as claimed in claim 3, wherein the cap layer comprises a silicon-rich oxide. 5. The semiconductor device according to item 1 of the patent application scope, wherein the barrier layer is a silicon-rich oxide and the dielectric layer is a dielectric layer with a low dielectric constant. 6. For a semiconductor device as claimed in item 5 of the patent application, in which the dielectric layer having a low dielectric constant is fluorinated silica glass. 7. The semiconductor device as claimed in claim 1, wherein the thickness of the barrier layer is about 50 nm. 8. For example, the semiconductor device of the first patent application scope still includes a plurality of metal features on the semiconductor substrate, wherein the barrier layer isolates each of the plurality of metal features from the dielectric layer. 9. The semiconductor device as claimed in claim 8 wherein the semiconductor device is an integrated circuit. O: \ 70 \ 70290.ptc Page 19 501232 _Case No. 90108007 5 ^ Year Month '/ Day Amendment_ VI. Patent Application Scope 1 0 · If the semiconductor device in the 9th patent application scope includes a transistor and its Metal features form part of an interconnection system that electrically connects transistors. 11. A method of forming a semiconductor device including a metal feature on a semiconductor substrate, comprising: forming a silicon-rich barrier layer on the metal feature; and forming a dielectric layer on the metal feature and the barrier layer. 12. The method of claim 11 in the scope of patent application, wherein forming the barrier layer system comprises forming a silicon-rich oxide by a high-density plasma method. 1 3. The method according to item 11 of the scope of patent application, further comprising forming a capping layer on the dielectric layer and forming a metal feature on the capping layer, the capping layer inhibits the substance of the dielectric layer from penetrating into the metal feature located on the capping layer. . 14. The method according to item 13 of the patent application scope, wherein forming the capping layer comprises forming a silicon oxide-rich layer by a high-density plasma method. 15. The method of claim 11 in the scope of patent application, wherein forming a dielectric layer comprises forming a fluorinated silica glass layer by a high-density plasma method. 16. The method according to item 11 of the scope of patent application, wherein forming the barrier layer system includes forming the barrier layer to a thickness of about 50 nm. 17. The method according to item 11 of the scope of patent application, further comprising forming a plurality of metal features on the semiconductor substrate, and forming a barrier layer system includes forming a barrier layer on each of the plurality of metal features to isolate each of the plurality of metal features. With dielectric layer. 1 8. The method according to item 11 of the scope of patent application, further comprising forming an integrated circuit. 19. The method as claimed in item 18 of the scope of patent application, further comprising forming a transistor O: \ 70 \ 70290.ptc Page 20 501232 Case No. 90108007 ^^ 7 / Day Revised volume formation includes bulk crystal formation. The contract is a special type of f-shaped road that is owned by the Department of Metallurgical Industry, and is a multi-billion-dollar mutual-benefit specialist, and the method of the six methods in the formation of the electric six barrier silicon rich 11 11 The layer ^ ¾ interspersed with the M. 0 barrier ^ ¾ The introduction and the levy of special levy will form the encapsulation layer barrier silicon rich levy of special levy into the osmotic flattening interlayer sublayer. The upper plate substrate is guided in place so that the species and the singularity can be deposited on the sedimentary layer with a sedimentary layer in the normal eclipse. The implementation plan is the same as the direction of each agent. The dielectric layer on the upper surface of the upper layer will be charged; The appearance of the remaining surface is often flat and inferior, and it is thought that the inscription of # 化 份 坦 部 平平 的 露 电 介 机 will make the road containing the method of the method rpir volume to make U & ul seed forming upper plate The substrate is semi-singular and special: it is included in the spheroid, and it is calm and smooth, and the dielectricity of the interlayer dielectric is often special. Phase • Make the case-by-case plan into the same direction as the resistance of each agent into a light shape. The upper surface of the dielectric layer will be ^ ¾ and exposed, and the remaining differences are left under the engraved # 部 部The exposure of the exposed fsrc il can be made into, •, and the special surface is characterized by the shape and shape of the interlayer. The physical layer is connected to the interlayer to form the electric layer. Ο Make the dielectric path in the electrical volume O: \ 70 \ 70290.ptc Page 21 501232 _ Case No. 90108007 ρ /// said _i ^ E._ VI. Patent application scope 23. —A semiconductor device with metal features on the surface of the semiconductor device, including: Features and include fluorine that is permeable to metallic features A dielectric layer; and a silicon-rich barrier layer between the metal feature and the dielectric layer; a cap layer on the dielectric layer; and a metal layer on the cap layer, the cap layer inhibits fluorine from penetrating into the metal layer. 24. A method of forming a semiconductor device including a metal feature on a semiconductor substrate, comprising: forming a silicon-rich barrier layer on the metal feature; and forming a dielectric layer including fluorine on the metal feature and the barrier layer, the silicon-rich barrier layer may Inhibiting fluorine from penetrating into the metal features on the silicon-rich barrier layer; and forming a cap layer on the dielectric layer, wherein the silicon-rich barrier layer, the dielectric layer and the cap layer are formed in situ with a high-density plasma. O: \ 70 \ 70290.ptc Page 22