TW498502B - Flash memory structure and its manufacturing method - Google Patents

Abstract

A flash memory structure is provided. It comprises a pair of source and drain and at least three control gates (transfer gates) that are displaced between the source and drain and parallel to the second direction. Besides, a stripe-type layer covers the control gates. The gate oxide is on the substrate surfaces among the control gates. The selective gate parallel to the first direction is displaced on the gate oxide and the stripe cover. The floating gate sits beneath the intersection of the selective gate and the control gate and the dielectric layer is displaced between the floating gate and the control gate. The tunnel oxide locates beneath the floating gate and upon the substrate.

Description

498502 V. Description of the invention (1) [Field of the invention] The present invention relates to a method for manufacturing a semiconductor memory (semiconductor memory), in particular to a method in which a plurality of memory cells share a source / inverter. Manufacturing method of split gate flash memory. [Knowledge technology] In order to save layout space, traditional flash memory uses a source / drain shared by every two bits for writing, erasing and reading, as disclosed in

IEDM 1 994-57, titled " a Dua Bubit Split-Gate EEPR0M

Cell in Contactless Array for Single-Vcc High

Density Flash Memories ", its layout is shown in Figure 1A, Figure 1B is a B-B sectional view of Figure 1A. This memory cell is manufactured by a fully self-aHgned tHple-pQly process, which consists of a floating gate 22 (the first layer of polycrystalline stone) and a control gate. A separate gate structure composed of the electrode 26 (the second layer of the polycrystalline silicon layer) and the character selection gate 30 (the third layer of the polycrystalline silicon layer). A source / drain diffusion region 40 is placed every two floating gates 22 to change the density of the memory cells. Although the two floating gates 22 share the same character, the selection gate 30 and the source / drain region 40, but each has its own control gate 26, so a single floating gate 22 can be Read or write. When a floating gate 22 is selected and restored, the control gate 26 corresponding to the unselected floating gate 22 functions as a transfer gate. Therefore, the performance of the transfer gate and control gate will change with the selected memory cell. Compared with the traditional structure that each floating gate has a pair of source / drain

498502

Compared with the above-mentioned structure, it can have a higher memory cell density. Increasing the memory capacity per unit area is a current trend, so the present invention provides a structure and a manufacturing method thereof that can further increase the memory capacity. [Objective and Summary of the Invention]-In view of this, an object of the present invention is to provide a structure of a flash memory capable of increasing the density of a memory cell and a method for manufacturing the same. "Therefore, the present invention provides a flash memory including: a pair of source /: poles, and at least three control gates (transfer gates) located at this pair of sources; no β. Wherein this pair of sources / sinks The poles are located in the substrate, and the control gates (turn = poles) are located in the substrate λ ′ and are parallel to the second direction. The stripe-shaped cover layer is arranged on the gate electrode. The gate oxide layer and the cover layer are parallel to the first layer. In one direction, select the open-electrode and control inter-electrode (transfer inter-pole) & the intersection: = pole; between the selection gate floating gate and the control gate # (transfer gate). Pass through ::: stand in Floating gate and substrate surface. Pass-through oxide layer is located in the flash memory manufacturing method described above, such as forming a tunneling oxide layer on top of the tunneling oxide layer. The first strip is shaped on the substrate. A crystalline silicon layer. Then, a dielectric layer, a second layer, and a strip-shaped first replica cover layer, a second polycrystalline stone layer, and a strip-shaped layer are sequentially formed on the -parallel silicon layer in parallel with each other: Layer and cover layer, and etched to form strip-shaped openings so that they are parallel to each other: the crystalline silicon layer ' The crystalline silicon layer and the block-shaped first complex B-direction stripe cover layer and the compound crystalline silicon layer are used as floating gates. In the layer, the block-like first oxide layer and stripe-shaped cover

V. Description of the invention (3) layer, thermally oxidizable thermal oxygen layer, and electrode 'this layer. Move the first part ^ The surface of the second polycrystalline silicon layer and the bulk first polycrystalline silicon layer forms a para-oxide layer, and then covers the first mask pattern layer on the second part and exposes the first part Thermally oxidize the layer, and convert the first part into a first spacer, and remove the exposed through oxidation to expose the substrate surface. Next, a pair of source / drain pairs are formed in the substrate with at least three strips of second polycrystalline silicon ^ the first mask pattern layer, corresponding to the portion corresponding to the source / drain pairs. A third polycrystalline silicon layer is filled in the strip-shaped openings. The second part of the layer is converted into a second spacer to expose the open substrate of the second part here; the surface of the substrate and the surface of the third polycrystalline silicon layer are oxidized as the gate oxide layer and electrical properties, respectively. For isolation. Then, the fourth polycrystalline silicon layer is oxidized, and the fourth polycrystalline silicon layer is etched into stripe fourth polycrystalline silicon layers in a horizontal direction with each other as a selection gate to allow the above-mentioned objects and features of the present invention. The advantages and advantages can be more obvious and easy to understand. The following is a detailed description of the preferred embodiments and the accompanying drawings: [Simplified description of the drawings] Figure ^ Figures to 1B are traditional separation gates Layout and cross-sectional views of flash memory. 2A to 7A are layout diagrams illustrating a manufacturing process of a split gate flash memory according to one of the preferred embodiments of the present invention. Figures 2B to 7B are M scraping surfaces of Figures 2A to 7α, respectively.

in 0503-0537DVF; TSMC2001-0281; Amy.ptd p. 6 498502

V. Description of the invention (4) Figure 0 Figures 8A and 8B show the schematic diagram of the flash-memory unit of the present invention during writing and the schematic diagram of its electrical operation. , ° 2 * Figures 9A and 9B are schematic diagrams showing the structure and electrical operation of the flash memory unit of the present invention during erasing, respectively. ° Fig. 10A and Fig. 10b are respectively a schematic structural diagram and a schematic diagram of electrical operation of the flash memory unit of the present invention during reading. [Symbol description] Floating gate: 22 Control gate (or transfer gate): 26 Character selection gate: 3 〇 Source / drain diffusion area: 40 First direction: Di Second direction: D2 Base: 1 0 0 Active area: 1 50 Shallow trench isolation area: 1 6 0 Oxide layer (passage oxide layer): 102 Oxide layer (gate oxide layer): 124 Polycrystalline silicon layer: 104, 104a, 108, 120, 126 Dielectric layer: 1 0 6 Cover layer: 110 Opening: 11 2 Thermal oxidation layer (spacer): 114

498502

Photoresist pattern layer: 116, 122 source / drain: 11 8 [Example] Disk manufacturing method: Figures 2A and 2B to 7A and 7B show a separation gate according to a preferred embodiment of the present invention Method for manufacturing polar flash memory. Figures 2a to 7A are layout drawings, and Figures 2B to 7B are corresponding b-b sectional views. First, referring to FIG. 2A and FIG. 2B, an active region 150 and a shallow trench isolation region (STi) 160 are sequentially defined on a substrate 100 (such as a p-type semiconductor stone substrate) to sequentially form an oxide layer 102 and a polycrystalline chip. Layer 104. The oxide layer 10 is used as a tunnel oxide layer, and its formation method is, for example, formed by using a thermal oxidation method in an oxygen-containing environment; the polycrystalline silicon layer 104 above the oxide layer 102 The formation method is, for example, deposition by chemical vapor deposition (CVD). Then, a photoresist pattern layer (not shown) is covered on the polycrystalline silicon layer 104, and the photoresist pattern layer is a pattern of an active area. With the photoresist pattern layer as an etching mask, the polycrystalline silicon layer 104 is etched into a strip shape and parallel to each other in the first direction Di, and then the photoresist pattern layer is stripped. Form a crystal structure. Referring to FIG. 3A and FIG. 3B, a layer-shaped dielectric layer 106 'is formed on the surface of the stripe-shaped complex crystal layer 104. For example, the thickness from bottom to top is 580, 100 ~ 200 Angstroms and 20 ~ 80 Angstroms of oxidized stone / gasification dream / oxidized stone. ^ A polycrystalline stone layer 108 and a cover layer 110 are formed on the dielectric layer 106. The thickness of the polycrystalline stone layer m is about ⑽ Angstroms.

Gasified stone eve, its thickness is about 500 ~ 200 Angstroms. A photoresist pattern layer is formed on the cover layer 10, and a pattern θ which is parallel to the Ϊ pattern layer is used to control the gate and the transfer gate. The plane θ and the polycrystalline stone 106 are formed therewith. In the evening layer 104, stripe openings 2 ′ of the photoresist pattern 2 are stripped and then stripped 106 to form a large number of layers, and the rear layer / layer 110, the polycrystalline silicon layer 108, and the dielectric layer] W- I ^ stripes, parallel to each other in the second direction D2. And polycrystalline stone Xizhan! After a single etching, a block of polycrystalline ^ floating gate. You day / increase 1U4a, as the layer 108, enter the "thunder", Figure ^, on the cover layer 110, the polycrystalline silicon: the electrical layer 106, the polycrystalline silicon layer 10 "and the surface of the substrate 100 A 2 compliant thermal oxide layer 1 "is formed, with a thickness of about 3GG ~ 8GG angstroms. Then, a photoresist pattern layer 116 is overlaid, which exposes the source / drain region and makes the thermal oxidation layer in the bit region 114 turns into a spacer 114 that exposes the surface of the substrate 100. Each block of the photoresist pattern layer 116 covers at least three adjacent three-layer cover layers 110. In this embodiment, four are used as an example. Ion implantation process to form a source / drain 118 in the substrate. The implanted dopant can be As, the implantation energy is about 20 ~ 80, and the implantation dose is about 1E15 ~ 8E15 cur2. Then, please refer to FIG. 5A and FIG. 5B, remove the photoresist pattern layer 116, and fill a polycrystalline silicon layer 12 in the opening to make electrical contact with the source / drain 118. The method, for example, forms a layer of polycrystalline silicon material with a thickness of about 2000 to 3000 angstroms on the entire substrate, and then etches back to remove the opening.

498502 V. Description of the invention (7) ~ 1 1 2 Compound silicon material. Next, referring to FIG. 6A and FIG. 6B, a photoresist pattern layer 122 is formed on the cover layer and the polycrystalline stone layer 120. The photoresist pattern layer 122 roughly corresponds to the source / drain region 118, that is, The selected gate area is exposed. Thereafter, the polycrystalline silicon layer 120 of the non-source / drain region 118 is removed, and then an ion implantation process is performed to form a doped region within the substrate 100 in the exposed opening 112 to adjust the starting point. Voltage, the implanted dopant can be BF2, the implantation energy is about 20 ~ 80 KeV, and the implantation dose is about 1E12 ~ 5E13 cm_2. After that, the exposed thermal oxide layer 114 and the oxide layer 102 are anisotropically etched, so that the thermal oxide layer 114 in this region is also located on the side wall of the opening and exposes the surface of the substrate 100. Partition wall 11 4. Then, referring to FIG. 7A and FIG., After removing the photoresist pattern layer 1 22, an oxide layer 124 is formed on the surface of the substrate 100 and the surface of the polycrystalline silicon layer 120. [The thickness is about 100 to 200. Aye. The oxide layer 124 on the surface of the substrate 100 is used as the gate oxide layer, and the oxide layer 124 on the surface of the polycrystalline silicon layer 120 is used for electrical isolation from the wires formed above it. Then, a two-layered polycrystalline silicon layer 126 is formed with a thickness of about 1000 to 2000 angstroms, and a photoresist pattern layer is formed thereon. The photoresist pattern layer has stripes parallel to the second direction h. Shape pattern. Taking the photoresist pattern layer as an etching mask, the etching layer 126 is formed in a stripe and is parallel to each other in the first direction Di. Therefore, in order to select a gate electrode, the photoresist pattern layer is stripped. Operation method: _ The following will explain the operation of the flash memory of the present invention, here is a 4-bit shared pair of source / drain.

498502 V. Description of the invention (8) Figures 8A and 8B are shown separately. 6: The schematic diagram of the structure and the electrical operation. The flash of this month § has been defined as ί ^: its: the interstellar interlayer poles above the floating gate (tG ϊγχ: ί polyspar evening layers are defined as transfer generation), select Gate (SG), source ⑴ and turn = =, 6V, 2V, 0.5VM.5V. On). Therefore, the hot electrons flowing through the source (s) Shoukou drain channel are injected into the selected floating gate. Figure 9B of the memory card t is a schematic diagram of the flash memory of the present invention when it is erased, the schematic diagram of the structure, and the schematic diagram of the electrical operation. The bit to be erased when β is erased is determined by # 搂 ρ 搂 / line). These selected floating gates = = character gates. In the case, control the voltage selection of ㈣ (CG), ί gate (SG), source (S), and drain (D), OV and ον. The unselected selection gate (SG) is 0v. Existence; the electrons in the floating gate pass through the Fowler-Nordhein (FN) and enter the selection gate (Pi Shi 10A and 10B respectively Schematic diagram of the structure and electrical operation of the memory card of the present invention at the time of reading is shown. 4: After the read address is determined, the compound crystal above the floating gate means the control gate (CG ), The remaining three polycrystalline silicon layers are fixed soft idlers (TG). In this case, the control gate (CG), transfer ^ (TG), selection gate (SG), source (s), and wave are controlled. 〇) Voltage

mm Ιϋϋ1 0503-6537TW; TSMC2001-0281; Amy.ptd Page 11 V. Description of the invention (9) The values are 1.5V, the magnitude of the current is selected to select the gate (SG) 6V, 2V, if the floating rule is determined Is ον. 0V and J · gate write 5 v ′ is again entered or erased by the drain. Here, write the above into the following table. (D) Connected to unselected operation voltages such as erasing and reading, such as ------ ^ nesting and removal ------- '---------- control gate (CG) Read transfer gate (TG) ον 1.5 V --- 6 V ------------ Select gate (SG) ------ 1 13 V-11 '_ 6 V rj «Τ τ 2 V ον ------ ον pole (D) L 1 1 5.5 V ------------- ον-~~ ----- 1.5 V ----- -[Features and effects of the invention] In summary, the present invention has at least the following advantages: a multi-bit storage capacity is arranged between a pair of source / sink, =, so it can save area and improve unit memory capacity. It can also perform operations such as writing, erasing, and reading. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to

0503-6537TW; TSMC2001 -〇281; Amy.ptd 498502 5. Description of the invention (ίο) Anyone skilled in the art can be modified and retouched without departing from the spirit and scope of the invention. Therefore, The protection scope of the present invention shall be determined by the scope of the attached patent application.

0503-6537TW; TSMC2001-0281; Amy.ptd p. 13

Claims (1)

^ 8502 1. A method for providing a plurality of strips of a polycrystalline silicon layer in the shape of a plurality of strips formed on the substrate firstly through the electrical penetrating layer, and in a moment, the silicon layer; The substrate includes: a through oxide layer is formed on the bottom; a plurality of multiple crystalline silicon layers are formed parallel to each other on the oxidized layer: the first multiple crystalline silicon layer; and the cutting is performed in a first direction. ; A layer of a polycrystalline silicon layer and a cover layer are formed on the layer-by-layer layer and the strip-shaped poly-crystalite layer; the complete cover layer, the first-yi Yue 忐 # # π # 2— 复The silicon layer and the strip-shaped first complex crystals are formed, and Samoto is flattened to each other in a second direction S, the plurality of strip-shaped second complex crystal silicon layers, and the plurality of bulk-shaped caps, wherein the bulk-shaped first The polycrystalline silicon layer is used as the surface of the floating oxide layer, the strip-shaped covering layer, the strip-shaped second poly-silicon layer, and the bulk first poly-crystalline silicon layer. Forming a para-oxidation layer; "" covering a first mask pattern layer on the thermal oxidation layer of the second portion, and exposing the thermal oxidation layer of the first portion; Converting the thermal oxide layer of the first part into a first spacer, and removing the exposed tunneling oxide layer to expose the surface of the substrate; forming a pair of source / drain electrodes in the substrate, There are at least three strips of the second polycrystalline silicon layer disposed between the pair of source / drain electrodes; the first mask pattern layer is removed; the strips corresponding to the first portion of the pair of source / drain electrodes A third polycrystalline silicon layer is filled into the opening; 0503-6537IW; TSMC2001 -0281; Amy. Ptd page 14 498502 6. The scope of the patent application turns the thermal oxide layer in the second part into a second gap wall to + the surface of the substrate with the second part open ; Forming an oxide layer on the second polycrystalline stone layer and the surface of the substrate for electrical isolation and gate oxide layer; a knife, forming a fourth polycrystalline silicon layer on the oxide layer; And the fourth polycrystalline silicon layer is engraved with neodymium, so that a plurality of strip-shaped fourth polycrystalline silicon layers parallel to the first direction are used as selection gates. 2. The method of manufacturing a flash memory as described in item 丨 of the patent application scope, wherein before forming the tunneling oxide layer, it further comprises: — forming a shallow trench isolation region in the substrate to define A plurality of strip-shaped active regions parallel to the first direction and corresponding to the strip-shaped first crystalline silicon layers. One "film one complex method 3. The manufacturer of the flash memory as described in item 1 of the scope of the patent application, wherein the material of the cover layer is silicon nitride. 4. The flash memory as described in the first scope of the patent application A method for manufacturing a memory, wherein the dielectric layer is a stack composed of silicon oxide / silicon nitride / silicon oxide, and 5. The method for manufacturing a flash memory as described in item 1 of the scope of patent application, wherein A method for filling the third polycrystalline silicon layer in the strip-shaped openings corresponding to the pair of source / non-electrodes includes: covering a third mask pattern layer over the third poly-silicon layer; On the polycrystalline stone layer; removing the exposed third polycrystalline silicon layer until the second part of the thermal oxide layer is exposed; and ^ 8502 6. scope of patent application for removing the second mask pattern layer 6. The method for manufacturing a flash memory as described in item 5 of the scope of the patent application, wherein the exposed third polycrystalline silicon layer is removed until the second part of the thermal oxide layer is exposed. And further includes: performing an ion implantation process to implant the dopants in the second part In this substrate, it is used to adjust the starting voltage. 7. The manufacturing method of the flash memory as described in item 1 of the scope of the patent application, wherein four strip-shaped second electrodes are arranged between the pair of source / drain electrodes. Multiple crystal silicon layer. ❿ 8 · —A kind of flash memory structure, including: a substrate; a pair of source / drain electrodes are located in the substrate and parallel to a second direction; a pin-shaped control gate (Transfer gate) is located on the substrate and between the pair of source / drain electrodes and is parallel to the second direction; a plurality of strip-shaped covering layers are located on the control gates (transfer gate · substrate = pole oxide layer is located on the One of these control poles (transfer poles) = the pole is located on the free oxide layer and the cover layer, and the parallel floating floating gate is located below the intersection of the selected gate); The two control gates (transferring multiple dielectric layers are located between each floating blue ^ t gate); and the gate and the mother control gate (transfer 0503-6537TWF; TShOOO1-0281; Amy.ptd page 16) 498502 VI. The patent application Fanyuan Yichuan gasification layer is located at each buttercup gate Below the electrode and the surface of the substrate. The structure of the flash memory as described in the eighth patent application, where there are four stripe control gates (transferring electrodes) between the pair of source / drain electrodes. Shen Er \ Li Fan Yuan No. δ = Structure of Flash Memory '(Transition pole); i! Wall is located in the selection and the control poles (Transfer time) the dielectric layers and the Yang 1 gates As described in item 8 of the scope of the patent application, the control open electrode (transfer open electrode) and the floating structure of the compound = polycrystalline silicon. The material of the Yu gate is 12 Item 8 of the scope of the patent application states that the dielectric layer is a silicon oxide / silicon nitride silicon structure. Composition of stacked surnames page 17 0503-6537TW; TSMC2001 -0281; Amy.ptd