TW498487B - Method and device for array threshold voltage control by trapped charge in trench isolation - Google Patents

Description

498487 V. Description of the Invention (1). Background of the Invention In the semiconductor industry, trench isolation is used to reduce the circuit shape and to provide better isolation between adjacent semiconductor devices. In a typical process for forming a shallow trench insulation, a nitride substrate is formed on a thermal oxide film over a shallow trench. The nitride substrate shown is a high-efficiency oxygen diffusion barrier layer. Therefore, the nitride substrate is formed to prevent oxidation of the stone side wall in the neck region of a storage trench. However, currently formed nitrides have some problems. The nitride substrate is shown to be used as a charge trapping source, which can cause an interface leakage current in an supporting circuit to an unacceptable level. Charge trapping occurs on the interface between the nitride substrate and the oxide used to fill the trench. Many methods have been proposed to deal with charge trapping. Most methods improve insulation by reducing charge trapping, rather than asking questions by using charge to improve device operation. For example, U.S. Patent No. 5,7 4 7,8 6 6 describes a structure for limiting charge trapping. Ho et al. Describe a crystalline RTN nitride substrate deposited above 1050 ° C to reduce the density of trapping centers. Another problem in forming the nitride substrate is that the process window of the nitride layer is relatively narrow. The nitride substrate can easily damage the area near the top of the trench and the area near the corners of the active layer during subsequent process steps. When a pad of nitride film is etched using hot phosphoric acid, etching to the nitride substrate cannot be avoided. It is difficult to control the isotropic etching near the corner portion of the active area. This will greatly affect the off current (oif_current) of the device. Reduced width due to the semiconductor device and focus on corners of the active area

O: \ 71 \ 71319.ptd Page 6 498487 V. Description of the invention (2) ^ The electric field is divided, and the breaking current is determined by the conductivity of the corner of the active area. The breaking current is greatly affected by the geometry of the corner portion. Therefore, there is a need for a semiconductor device and its manufacturing process for addressing the current problems of charge trapping and current interruption in forming the nitride substrate. SUMMARY OF THE INVENTION The present invention provides a semiconductor device and a method for manufacturing the same. A trench is formed in a semiconductor substrate. It is preferable to form a thin oxide substrate on the surface of the trench. A nitride substrate is formed in the trench. The charge is trapped in the nitride substrate. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride substrate. Preferably, the oxide fill is formed directly on the nitride substrate. Brief Description of the Drawings The present invention will be further described with reference to the accompanying drawings, in which: FIGS. 1A-1D are cross-sectional views of a semiconductor device, which are used to explain a process according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of a memory array formed according to an embodiment of the present invention; FIG. 3 is a cross-sectional view of a MOSFET formed according to an embodiment of the present invention; Fig. 5 shows experimental data of a PFET formed according to an embodiment of the present invention; Fig. 6 shows replacement of a nitrided oxide The oxidized substrate and nitrogen

O: \ 71 \ 71319.ptd Page 7 498487 V. Description of the invention (3) Information on the substrate; Figure 7 is a table showing an oxide substrate with a fixed nitride substrate thickness at Vt Fig. 8 shows the relationship between the cutoff current of the critical voltage tailor profile of the implant array and the peak concentration. DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device having a small amount of interrupted current. The present invention is preferably implemented with a DRAM array and an NMOSFET. Generally, a DRAM array JNMOSFET includes NFET array devices formed in a p-well region and NFET and PFET support devices. The present invention is directed to doping a p-well region to reduce off current. The invention also allows the P-well region doping to be reduced for a given break current. Reducing the P-well region doping can improve the characteristics of semiconductor devices, such as: interfacial leakage current characteristics, retention time productivity, subcritical slope, substrate sensing, and interface capacitance. The reduced p-well region doping is accomplished by using a charge trapped on a nitride substrate. The charge trapped in the nitride substrate can be used to adjust the threshold voltage of the device. Therefore, in addition to the general design parameters (such as gate oxide thickness, channel / well region doping, gate conductor work function, etc.), the charge captured in the nitride substrate can be used as a device design parameter . Generally, the array device is an NFET and the captured nitride charge is negative. The minimum lithographic imaging width of a DRAM array NMOSFET allows for the greatest advantage presented by the negative charge in the nitride substrate. Therefore, the threshold voltage at the corners of the array will increase due to the narrow width of the array device. because

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Most of the supporting FETs are better than the array j? Et officer; the appearance of the charge in fp__ is near to the supporting FETs; the voltage of two is on the die substrate. However, the negative charge captured has the magnitude of the shadow voltage of γ to the outside. For the above-mentioned Π-angle Luo criticality of PFET, it replaces the ancient: Yi Yichan squatted the use of-side wall planting or, "" generation method to compensate, to increase the corner Pro. The main reason for the pilot is the electricity induced by the process The slurry is filled with the gaseous lining ... Therefore, the capture of the master takes place in the following: as-actively see the test Figure 1A-1D 'will be described in accordance with the present invention = body substrate U. Usually, formation-large = as much as possible The rhenium emulsion depends on the substrate nji. Then, a pad nitride film 13 having a thickness of about 100 nra to 25 0 nm is formed as shown in the section J. Next, the dysprosium nitride film 13 is etched with a neodymium film. The pad oxide film 12 and the substrate n: This forms a trench 14 as shown in FIG. 1B. The above-mentioned process is known and can be implemented using conventional techniques. As the tears go back to 1 C, traditional techniques can be used. An oxide substrate 15 is formed on the trench 14 = surface. Pass # to provide an oxide substrate 15 to cover the surface of the substrate 11. Preferably, only the surface of the oxide substrate 15 on the trench 14 is formed. Then, a nitride substrate 16 is formed on the oxide substrate 15. The nitride substrate may be formed by 7 0 0 It is -8 0 0. (3 is an amorphous layer formed by LPCVD, RTCVD, or other known coatings. The above processes are known to those skilled in the art. A nitride layer can also be formed. 4 medium and pad nitride

498487 V. Description of the invention (5) On layer 1 3. It is best to form the charge in the shape of the conductor device. A good physical filler 17 is isolated from the trenches. 4 The transistor and other fillers can be enhanced in the manufacturing process. Moderate temperature. So at a fraction of a voltage. The nitride, in which the filler 17 is preferably formed directly, is as described above. The process of trapped charge is roughly to separate the semiconductor substrate trenches in the substrate and the trenches in the trenches and isolate them. Preferably, a nitride substrate 16 is formed in the nitride layer so that electric charges can be trapped therein. The entire nitride substrate is distributed in the trench and the voltage as above is changed. Then, half can be completed using known methods. In the embodiment, after the nitride layer 16 is formed, an oxide trench 14 is formed (as shown in FIG. 1D). An oxidizing filler 17 is formed and the element 'active area is separated on a substrate, where the device is formed in the substrate. A negative charge concentration trapped in an HDP oxide fill nitride layer was found. The HDP plasma is assumed to have a potential of about 10 _ 1 2 volts. In addition, a P-type substrate with a higher electron concentration than at moderate temperatures across the oxide and nitride substrates will reduce most of them and will generate a high electric field, which will help electron tunneling To 4 where the nitrides are captured by the electrons. Therefore, oxidation is an HDP oxidation filler. Ideally, the HDP filler is on the nitride substrate 16 most. When the device is a DRAM array, it has a particular advantage over a nitride substrate. The process for forming a DRAM array according to the present invention is the same as that described above. In this device, it is divided into an array area and a support area. Some are formed by etching to isolate subsequent elements. A nitride liner is formed and then an oxide filler is deposited in the trench to form the oxide filler. The oxide filler is formed by the HDP process to increase the trapped charge. Next, an NFET is formed in the array region.

O: \ 71 \ 71319.ptd Page 10 498487 V. Description of the invention (6) domain, and forming NFET and PFET in this support area. The dopant concentration of the p-well region in the array region is reduced as a function of the negative charge captured in the nitride substrate. For example, a surface doping concentration that is usually 30% to 50% less than that of a conventional device can be completed in the p-well region without degrading the performance of the device (see Figure 8). FIG. 2 shows a method for forming a dram array according to the present invention. The semiconductor substrate 11 is divided into a plurality of array regions 20 and a plurality of support regions 22. Trenches 14 are formed in the substrate by etching. In the case of a p-well area, a well area 24 is formed in the substrate 11 of the array area 20. A nitride substrate 16 is formed in the trench between the array region 20 and the support region 22. A mask etch may be performed on the nitride substrate 16 to remove it from the area where the PFET is to be formed. This protects P F E T from the negative charges captured. Alternatively, the thicknesses of the oxide substrate 15 and the nitride substrate 16 may be selected, so that the PFET is completely aged by in-line charging. This ensures that the PFET does not age further and provides a reliable device. Next, the trenches are filled with oxides to form the isolation as described above, and conventional process techniques are implemented to form the MOSFET as shown in FIG. 3. A source / drain region 34a, 34b is formed in the substrate 11, and a gate conductor 33 is formed on the gate oxide 32. Figures 4-8 show experimental data resulting from testing the structure according to the invention. Figure 4 shows the array corner threshold voltage for different combinations of nitride and oxide substrates. It can be seen from FIG. 4 that for a semiconductor device formed with an oxide substrate with a thickness of 6 nm and a nitride substrate with an thickness of 11 nm, the threshold voltage at the array corner will increase. In this case, the critical

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塾 Increased almost 150 mv. Combined with the PFET branch voltage as shown in Figure 5, where the corner threshold voltage is large and the corner is placed clearly, the 1 1 nm thick nitride substrate keeps negative dipoles and decreases, very «7 ^ ^ ^ ^ T, 4 ^: oxide substrates of different thicknesses, "the array substrate is different from -with 丨: therefore, the negative charge in the gaseous substrate; to: have a large" oxide range between the two ranges The bottom thickness is not sensitive. In addition, the γ, fish-and-lice-oxidized oxide substrate also helps to capture the second one; the Γ 2 substrate and the nitride substrate J are replaced with an II-shaped oxide. This description clearly shows that the oxide substrate and the nitride substrate each have a -probabilityϋthickness ★. The thinner oxide substrate should greatly enhance the trapped negative number due to the increased tunneling of the thinner oxide substrate than that of the thinner substrate. The oxide substrate should be as thin as possible, but still sufficient to cover two, usually less than 10 nm in thickness. A preferred oxide substrate has a dry circumference of less than 4 ㈣, for example, 1-4 nm. In comparison, there is no upper limit to the thickness of the nitride 9 °. It can be observed that the thickness of the hafnium nitride base is between ^ -11 nm, and the increment of the threshold voltage will gradually decrease. However, it has no destructive effect on the use of the parent thick nitride substrate. The preferred thickness of the nitride substrate is 5.5 nm. * Figure 8 # shows the experimentally determined relationship between the cut-off current of the critical voltage tailor profile of the implant array and the peak peak degree. Here, a conventional device ^ shows the general relationship between the intermediate interruption current of the device iDRAM array mfsfet according to one embodiment of the present invention and the 11-round temple spikes. Traditional devices have a thickness of 3 nm

Page 12 498487 V. Description of the invention (8) The AA oxide substrate and a nitride layer with a thickness of 5.5 nm. The device according to the present invention has an AA oxide substrate having a thickness of about 6 nm and a nitride substrate having a thickness of about 11 n in. In this example case, τ X is 7 n m and the minimum feature size is 200 nm. As can be understood from Fig. 8, compared with a conventional device, for a device according to the present invention, the doping concentration in a P-well region for a given interruption current is reduced. The P-well region is doped by 30% to 50% less than the conventional device. In this way, it becomes possible to use the charge trapped in the nitride and the layer to control the voltage threshold. Therefore, compared with the conventional device, the interruption current of the present invention can be greatly reduced. Therefore, the above has provided a device having a small amount of interrupted current and a method for manufacturing the same. The reduction of the off-current is accomplished by the charge captured by the nitride substrate formed in ST I. This trapped charge allows the reduction of doping in a P-well region. Therefore, higher throughput can be obtained and interface leakage current can be reduced. The foregoing description of the invention has illustrated the invention. In addition, the disclosure only shows and describes the preferred embodiments of the present invention, but as mentioned above, it can be understood that the present invention can be used in different other combinations, modifications, environments, and the same skills or knowledge as the above teachings and related technologies. Changes or modifications can be made within the scope of the inventive concepts shown. The above embodiments are used to explain the best mode for carrying out the invention, and those skilled in the art can use the invention of this embodiment or other embodiments, as well as different modifications required for specific applications or use of the invention. Therefore, the above description is not intended to limit the present invention to the aforementioned forms. And, the scope of the attached patent application is used to explain that some alternative embodiments are included.

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Claims (1)

498487? / Year Case No. 90111961 6. Scope of Patent Application 1. A method for manufacturing a semiconductor device forming a trench in a substrate; and forming a nitride substrate in the trench; wherein the nitride substrate has a trapped charge. 2. The method of claim 1, further comprising: forming an oxide substrate between the nitride substrate and the trench, wherein the nitride substrate is among the oxide substrate, and the nitride is among them. The substrate is wherein the nitride substrate further includes filling with an oxide, wherein the oxide filler is wherein the oxide filler is, wherein the nitride liner, wherein the semiconductor substrate 3. As claimed in the scope of the patent application No. 1 of Method: The thickness is at least 5.5 nm. 4. For the method in the second item of the patent application: The thickness is at least 5 nm. 5. The method according to item 1 of the scope of patent application is formed by LPCVD. 6. Method for applying for the scope of patent application item 1: Non-crystalline. 7. If you apply for the method in item 1 of the patent scope, you can fill the trench. 8. The method of claim 7 is directly formed on the nitride substrate. 9. The method according to item 7 of the scope of patent application is formed by the HDP process. 10. The charge captured in the bottom of the method in the scope of patent application is negative. 11. If the method in the first patent application scope is a P-well area. O: \ 71 \ 71319-910626.ptc Page 15 498487 Case No. 90111961 Amendment VI. Patent Application Range 12. As the charge trapped in the bottom of the patent application range increases 13. If the patent application range charge is distributed throughout the nitriding Layer 14. If the scope of the patent application is roughly 15.15 in the middle; 16. Oxide lining oxide film 17. Degree is less 18. Chemical lining 19. Chemical lining 20. The P-well is made of a kind of nitric oxide to make semiconductor engraved trenches in half to lead to a nitrogen by a high capture negative If before the application, if the application is at 4 nm, if the application is as thick as the application, the thickness of the substrate is the same as the density of the substrate in the application area. Line the threshold voltage of the device. The method of item 1, wherein the captured electricity is applied. The method of item 1, wherein the nitride is formed. A device method includes: an array region of a bulk substrate and a support region in the trenches; a process of depositing an oxide filler in the trench nitride substrates, at least in the array region, item 15 The method further comprises forming the nitrogen substrate to form a method of item 16 of a patent range having a thickness of less than 10 nm, wherein the thickness of the oxide film is greater than 5. The patent range is greater than or the patent range is doped The method of item 15 of the impurity concentration, wherein the nitrogen formed is 3 nm ° The method of item 18, where the nitrogen formed is equal to 9 nm. The method of item 15, wherein the increase or decrease of the array area is a function of the captured negative charge O: \ 71 \ 71319-910626.ptc Page 16 498487 6. Number of patent applications. 21. If applying to the array area 2 2. If applying is amorphous. 23. If applied to form the nitride 2 4. If applied to the substrate and the oxide film 2 5. — a kind of semi-substrate, trench, whose nitride-lined charge is captured in the oxide-filled FETs, where Capture 26. If you apply for impurities for doping. 27. If applying for NFET ° 28. If applying for non-crystalline. Case No. 90111961 The method of amending the 15th patent scope further includes forming NFETs and PFETs in the support area. The method according to item 15 of the patent, wherein the nitride substrate The method according to item 15, wherein the substrate is made by LPCVD. The method of item 16 of the patent, wherein the nitride is formed as a nitrided oxide. A conductor device including: it is doped with impurities; formed in the substrate to define an active area of the element; a bottom formed in the trench, the nitride substrate having therein; a filler formed in the trench Formed in the active regions of the elements; the doping concentration of the impurity in the substrate is a function of the charge in the nitride liner. The device of the scope of patent No. 25, wherein the substrate is p-type The device of the scope of patent No. 25, wherein the FET is a device of No. 25 of patent scope, wherein the nitride substrate O: \ 71 \ 71319-910626.ptc Page 17 498487 _ Case No. 90111961 _? / Year "Amendment on the 27th of January _" 6. Application for a patent scope 2 9. For a device applying for a patent scope 25, the charge is Negative 0 30. The device according to item 25 of the patent application scope further includes an oxide substrate disposed between the nitride substrate and the trench. i 31. The device as claimed in claim 25, wherein the thickness of the nitride substrate is at least 5.5 nm. 32. The device of claim 30, wherein the thickness of the oxide substrate is at least 4 nm. 33. The device as claimed in claim 25, wherein the nitride substrate is formed by LPCVD. 34. The device as claimed in claim 25, wherein the oxide filler b is directly formed on the nitride substrate. 35. The device as claimed in claim 25, wherein the oxidizing filler is formed by a HDP process. 36. A memory array comprising: a semiconductor substrate having an array region and a support region; trenches formed in the semiconductor substrate, and a nitride substrate formed in the trenches; The nitride substrate has electric charges trapped therein; an oxide filler formed in the trenches; an element active region disposed between the trenches in the substrate with a _P-type impurity To dope the active regions of the elements in the array region, the doping concentration is a function of the charge trapped in the nitride substrate; and NFETs formed in the active regions of the elements in the array region in. O: \ 71 \ 71319-910626.ptc Page 18 498487 Amendment No. 90111961 VI. Patent Application Range 37. For example, the memory array of the 36th patent application range, wherein the nitride base is amorphous. 38. The memory array of claim 36, wherein the charge is negative. u 39. The memory array according to item 36 of the patent application scope further includes an oxide substrate disposed between the nitride substrate and the trench. _ 4 0. For the memory array of the 36th aspect of the patent application, wherein the thickness of the nitride substrate is at least 5.5 nm. 41. The memory array of claim 39, wherein the thickness of the oxide substrate is at least 4 nm. 4 2. The memory array according to item 36 of the patent application, wherein the oxidized 0 filling material is directly disposed on the top of the nitride substrate. O: \ 71 \ 71319-910626.ptc Page 19