498279 經濟部智慧財產局員工消費合作社印製 A7 _B7_ 五、發明說明（1 ) 發明領域 本發明係關於一種提高微控制器處理效率的裝置及方 法，特別是關於一種利用特定之條件跳躍指令識別碼及相 對應之硬體設計以提高微控制器處理效率的裝置及方法。 發明背景 在影像處理或語音信號處理時，經常須先進行一數學運 算，再依據運算完的結果決定是否要更新位於一記憶單元 内的資料内容，該記憶單元可例如為一暫存器組（register file) 或一記憶體（memory)或其它儲存機構。 以下的例子係以一高階語言表示當運算完的結果為非溢 位（non-overflow)時，可將運算之結果寫入一暫存器，否則 維持該暫存器之值。498279 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of the Invention (1) Field of the Invention The present invention relates to a device and method for improving the processing efficiency of a microcontroller, and in particular to a jump instruction identification code using specific conditions And corresponding hardware design device and method for improving microcontroller processing efficiency. BACKGROUND OF THE INVENTION In image processing or speech signal processing, it is often necessary to perform a mathematical operation first, and then decide whether to update the data content located in a memory unit based on the result of the operation. The memory unit may be, for example, a register group ( register file) or a memory or other storage mechanism. The following example uses a high-level language to indicate that when the result of the operation is non-overflow, the result of the operation can be written to a register, otherwise the value of the register is maintained.
IF OVERFLOW(AX+MEM)= 1 THEN NOP ELSE ΑΧ —ΑΧ + MEM 其中OVERFLOW()係一數學函數，當該函數内部之參數 之運算結果為溢位時，該函數值為1 ; AX為一暫存器； MEM為一記憶體資料。 上述之例子若以X86的組合語言表示時，可如表1所示： 表 1IF OVERFLOW (AX + MEM) = 1 THEN NOP ELSE Αχ —Αχ + MEM where OVERFLOW () is a mathematical function. When the operation result of the parameter inside the function is overflow, the function value is 1; AX is a temporary Memory; MEM is a memory data. If the above example is expressed in the combination language of X86, it can be shown in Table 1: Table 1
PUSH FLAG PUSH ΑΧ ADD ΑΧ，MEM JNO Label 1 POP AX -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁)PUSH FLAG PUSH AX ADD AX, MEM JNO Label 1 POP AX -4-This paper size is applicable to China National Standard (CNS) A4 (210 x 297 mm) (Please read the precautions on the back before filling this page)
-— ϋ I I 一 0、* ϋ I ·1 ϋ I I I I I 1 n ϋ n -^1 ϋ ϋ ϋ ϋ ϋ .^1 ϋ n I I 498279 經濟部智慧財產局員工消費合作社印製 A7 ____B7________ 五、發明說明（2 )-— ϋ II One 0, * ϋ I · 1 ϋ IIIII 1 n ϋ n-^ 1 ϋ ϋ ϋ ϋ ϋ. ^ 1 ϋ n II 498279 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ____B7________ 5. Description of the invention ( 2 )
POP FLAG Label 1 NOP 其中JNO為非溢位時跳躍指令，Label 1為非溢位之條件成 立時的跳躍地址。 一般微控制器内部之資料流（data flow)係以管線架構 (pipeline architecture)在進行。如圖1所示，假設一微控制器 之官線架構10共有7個管線，每一個管線均進行一特定之 工作。進入該管線架構10的資料係擷取自一連續的記憶體 地址的指令，該資料循序地裝填入該管線架構1〇的各個管 線中。當一管線，例如第4管線，處理完它的特定工作 後，便將資料交給第5管線處理，而第4管線本身則接收來 自第3管線的資料，並重複進行其特定的工作。由以上的 敘述可知，當一微控制器内部之管線架構1〇之各個管線充 滿資料時，將有最大的處理效率。但當一微控制器執行到 一條件跳躍指令時，會在某一管線中，例如第5管線中計 算出條件成立的跳躍地址；而若條件成立時，該微控制器 會π除（flush)其内邵之管線資料π〜14，再從跳躍後的地址 重新裝填資料18，和位於該跳躍後地址以下之連續記憶體 地址之指令。而該清除管線資料的動作必將造成該控制器 執行效率的下降。表丨之組合語言程式因包含一條件跳躍 指令，因此無可避免地將導致一微控制器之執行效率下降 之結果。 簡要說明 本發明之目的係為消除目前微控制器在處理依運算結果 _____ 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ---------訂---------線» A7POP FLAG Label 1 NOP where JNO is the jump instruction when non-overflow, and Label 1 is the jump address when the condition of non-overflow is satisfied. The data flow in a general microcontroller is performed using a pipeline architecture. As shown in FIG. 1, suppose a microcontroller's official line architecture 10 has a total of 7 pipelines, and each pipeline performs a specific task. The data entering the pipeline architecture 10 are instructions taken from a continuous memory address, and the data are sequentially loaded into each pipeline of the pipeline architecture 10. When a pipeline, such as the fourth pipeline, finishes its specific work, it will hand over the data to the fifth pipeline for processing, while the fourth pipeline itself receives the data from the third pipeline and repeats its specific work. It can be known from the above description that when each pipeline of the pipeline structure 10 in a microcontroller is filled with data, it will have the maximum processing efficiency. However, when a microcontroller executes a conditional jump instruction, it will calculate the jump address of the condition in a certain pipeline, such as the fifth pipeline; if the condition is true, the microcontroller will π flush (flush) The pipeline data π ~ 14 in it is refilled with the data 18 from the address after the jump, and the instruction of the continuous memory address below the address after the jump. The action of clearing the pipeline data will inevitably cause the controller's execution efficiency to decrease. Because the combined language program of Table 丨 contains a conditional jump instruction, it will inevitably result in a decrease in the execution efficiency of a microcontroller. Brief description of the present invention is to eliminate the current processing results of microcontrollers according to the calculation of _____ 5 This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling (This page) --------- Order --------- line »A7
經濟部智慧財產局員工消費合作社印製 五、發明說明（3 ) 決定是否更新資料内容時會執行一條件跳躍指令而導致該 微控制器之效率降低之缺點。為了達到上述目的，本發明 提出一個預設的條件跳躍指+識別㉟並搭配相對應之硬體 架構以解決習知之缺點。本發明並未增加或減少組合語言 的指令，亦未更改組合語言指令之語法，因此和既有之組 合語言編譯器（assembler)相容，程式設計者僅須使用本發明 所提供的條件跳躍指令識別碼即可解決前述依運算結果決 定是否更新記憶單元之資料的問題，並且不會導致該微控 制器之效率降低。 本發明在裝置方面包含一記憶單元、一處理單元及一控 制單元。該記憶體元用於儲存複數組資料。該處理單元連 接於該記憶單元，用於解碼及執行指令及處理來自該記憶 單元之資料’其運算結果並回授至該記憶單元之輸入端。 該控制單元依據該處理單元解碼之指令是否為該條件跳躍 指令識別碼及該處理單元運算後之結果是否符合該條件跳 躍指令識別碼之條件，以控制該處理單元運算後之結果是 否可窝入該記憶單元。 圖式之簡單說明 本發明將依照後附圖式來說明，其中： 圖1為一微控制器的管線架構及執行跳躍指令前和執行 後的管線流；及 圖2為本發明之一較佳實施例之裝置示意圖。 元件符號說明^ 10管線架構 11〜17 跳躍前的管線資料 一 6 - 本紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公31 ) (請先閱讀背面之注音？事項再填寫本頁) ---------訂---------線' 、發明說明（4) 18 跳躍後的管線資料 2〇微控制器 21記憶單元 22處理單元 23控制單元 輕實施例說明 圖2為本發明之一較佳實施例之裝置示意圖，其中一處 理單元22，自一記憶單元21擷取其運算所須之複數個資 料，該記憶單兀21可例如為一暫存器組或一記憶體或其它 儲存機構；該處理單元22並自另一記憶體（圖未示出）擷取 複數組指令。之後，該處理單元22將該指令解碼（mstmcti〇n decodmg)並依擷取的資料產生運算結果，再回授至該記憶 單兀21的輸入端。該處理單元22之部分運算結果，例如旗 標（flag)和指令解碼等，被送至一控制單元23以產生一控制 信號，該控制信號將決定該處理單元22之運算結果是否可 窝入該記憶單元22之内。 為了和既有之組合語f編譯器（assembler)相容，本發明提 供了一種例如表2之方式以解決依運算結果決定是否更新 記憶單元之資料的問題。 表2 JN0 〇〇〇〇〇〇〇〇 (步驟 1 ) ADD ΑΧ,ΜΕΜ (步驟 2 ) 步騾1之指令，即由一個條件跳躍指令運算碼…ρ⑶心）搭 配一個其值為〇的位移量（diSpiacement)，為本發明之條件跳 躍指令識別碼。該其值為0的位移量，代表記憶體地址偏 移量（memory address offset)為0，即當跳躍條件成立時，程式 A7 五、發明說明（ B7 經濟部智慧財產局員工消費合作社印製 將執行該條件跳躍指今 ^ ^ 為別碼之下一個指令；亦即該微控 制备内（管線資料不會褚 曰號/肖除，而該微控制器的執行效率 也不會因此而下降。當處 午 處里單元22執行到表2之步騾1之指 令，該處理單元將進行指人 二 丁如7解碼並辨認出其為本發明預先 設定的條件跳躍指令墦則 " 哉力】碼。接著進入表2之步騾2，若 AX加上MEM會溢位，則批制w _ 貝J &制早兀23會依據此溢位狀態和 步騾1之條件跳躍指今嗜則 " 师一 、 相7硪別碼而產生控制信號，使該記憶 早兀21《寫入失效（writedisable)，因此而達到解決依運算結 果決定是否更新記憶單元21之資料的問題。 β 以鳩的指令集而言，有溢位時跳躍（Jump on overflow)、 非溢位時跳躍咖叫⑽誠晴也⑽卜小於/不大於/等於時 躍（Jump on Belcm/Not Above or Equal)、等於零時跳躍（Jump Zero)、正號時跳躍（Jump 〇n Sign)等跳躍指令。本發明之 件跳躍指令識別碼對任一條件跳躍指令均適用，表2之 合語言程式僅是以JNO指令，即非溢位時跳躍為例子。 本發明之技術内容及技術特點巳揭示如上，然而熟系 項技術之人士仍可能基於本發明之教示及揭示而作種種 背離本發明精神之改變及修飾；因此，本發明之保護範 應不限於實施例所揭示者，而應包括各種不背離本發明 改變及修飾，並為以下之申請專利範園所涵蓋。 跳 條 本 不 圍 之 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公i )Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (3) When determining whether to update the data content, a conditional jump instruction will be executed, which causes the disadvantage of the microcontroller's efficiency to decrease. In order to achieve the above-mentioned object, the present invention proposes a preset conditional jump finger + identification ㉟ and a corresponding hardware architecture to solve the conventional shortcomings. The present invention does not increase or decrease the instruction of the combined language, nor does it change the syntax of the combined language instruction. Therefore, it is compatible with the existing combined language assembler. The programmer need only use the conditional jump instruction provided by the present invention. The identification code can solve the aforementioned problem of determining whether to update the data of the memory unit according to the operation result, and will not cause the efficiency of the microcontroller to decrease. The device includes a memory unit, a processing unit and a control unit. The memory element is used for storing complex array data. The processing unit is connected to the memory unit, and is used to decode and execute instructions and process data from the memory unit 'and its operation result and return it to the input end of the memory unit. The control unit controls whether the result decoded by the processing unit is the conditional jump instruction identification code and whether the result of the operation of the processing unit meets the conditional jump instruction identification code to control whether the result of the operation of the processing unit can be embedded. The memory unit. Brief description of the drawings The present invention will be described in accordance with the following drawings, in which: FIG. 1 is a pipeline architecture of a microcontroller and the pipeline flow before and after execution of a skip instruction; and FIG. 2 is a preferred embodiment of the present invention. Schematic diagram of the device of the embodiment. Explanation of component symbols ^ 10 Pipeline architecture 11 ~ 17 Pipeline information before jumping 1-6-This paper size applies to China National Standard (CNS) A4 specifications (21G X 297 male 31) (Please read the note on the back? Matters before filling out this page ) --------- Order --------- line ', description of the invention (4) 18 pipeline data after the jump 20 microcontroller 21 memory unit 22 processing unit 23 control unit light implementation Example Description FIG. 2 is a schematic diagram of a device according to a preferred embodiment of the present invention. A processing unit 22 retrieves a plurality of data required for its operation from a memory unit 21. The memory unit 21 may be, for example, a temporary storage. A processing unit or a memory or other storage mechanism; the processing unit 22 retrieves a complex array instruction from another memory (not shown). After that, the processing unit 22 decodes the instruction (mstmctin decodmg) and generates an operation result according to the retrieved data, and then returns the result to the input end of the memory unit 21. Part of the operation results of the processing unit 22, such as flags and instruction decoding, are sent to a control unit 23 to generate a control signal, which will determine whether the operation results of the processing unit 22 can be embedded in the Within the memory unit 22. In order to be compatible with the existing assembler f assembler, the present invention provides a method such as Table 2 to solve the problem of determining whether to update the data of the memory unit according to the operation result. Table 2 JN0 〇〇〇〇〇〇〇〇〇〇〇 (step 1) ADD AX, MEM (step 2) step 1 instruction, that is, a conditional jump instruction operation code ... ρ⑶ heart) with a displacement of 0 (DiSpiacement) is a conditional jump instruction identification code of the present invention. The value of this displacement is 0, which means that the memory address offset is 0, that is, when the jump condition is established, program A7 V. Invention Description (B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Executing the conditional jump instruction ^ ^ is the next instruction of the other code; that is, the micro controller is in the pipeline (the pipeline data will not be nicknamed / xiao divided, and the execution efficiency of the microcontroller will not be reduced as a result. When the unit 22 executes the instruction of step 1 in Table 2, the processing unit will decode the finger 2 and 7 and recognize it as the conditional jump instruction set in advance for the present invention. Code, then enter step 2 of Table 2. If AX plus MEM would overflow, batch w_ 贝 J & system 23 will jump according to this overflow state and the conditions of step 1 " Division I, generating a control signal with phase 7 code, makes the memory as early as 21 "writedisable", and thus solves the problem of determining whether to update the data of the memory unit 21 according to the calculation result. In terms of instruction set, jump when there is overflow (Jump on overflow), jumping when the non-overflow is called, Cheng Chengqing also said less than / not greater than / equal to (Jump on Belcm / Not Above or Equal), jump to zero (Jump Zero), jump when the positive sign ( Jump instruction such as Jump 〇). The identification code of the jump instruction of the present invention is applicable to any conditional jump instruction. The combined language program in Table 2 is based on the JNO instruction, that is, jump when it is not overflow, as an example. The technical content and technical characteristics are disclosed as above. However, those skilled in the art may still make various changes and modifications that depart from the spirit of the present invention based on the teachings and disclosures of the present invention; therefore, the protection scope of the present invention should not be limited to the examples. The revealer should include all kinds of changes and modifications that do not depart from the present invention, and are covered by the following patent application parks. The paper dimensions that are not included in the jumper are applicable to the Chinese National Standard (CNS) A4 specification (21 × x297) i)