TW497356B - Architecture suitable for executing two-dimensional discrete wavelet transform - Google Patents

Abstract

The present invention provides an architecture suitable for executing two-dimensional discrete wavelet transform, which is applied in image compressing system for performing a plurality layers of frequency dividing operation to divide the frequency of an original image into a plurality of frequency bands. The architecture comprises: a transform module for dividing the frequency of an input image data into four frequency bands, wherein the frequency bands which are low in the horizontal and vertical directions are used as the input image data for the next layer of frequency dividing operation; a memory module for storing the frequency bands which are low in the horizontal and vertical directions; a multiplexer for selecting the image data to be fed into the transform module. To increase the hardware performance of the transform module in the design of the transform module, two techniques are utilized to increase the hardware efficiency. The first one is a multi-phase decomposing technique applied in a first order of horizontal filtering operation to decompose the coefficients of the filter into an odd number part and an even number part. The second one is a coefficient folding technique applied in a second order of vertical filtering operation to make every two coefficients of the filter share a set of multiplier, adder and register. Accordingly, the formed architecture for performing two-dimensional discrete wavelet transform has a 100% of hardware utilizing rate, a fast operating time, a regular data flow and a low control complexity.

Description

497356 V. Description of the Invention (1) This case is about two-dimensional discrete wavelet transform (2-D DWT), especially a hardware architecture suitable for performing two-dimensional discrete wavelet transform. Nowadays, a variety of micro-processing that can process images and sounds in real time has been gradually developed with the vigorous development of ultra-large integrated circuit technology. The so-called two-dimensional discrete wavelet conversion (2-D DWT) technology f has become the core technology of new-generation image processing systems. In the new-generation image f-shrinking standards such as jPEG-2000 or MPeg-4, both are Use 2-D DWT technology to do image compression and processing. The technical development of two-dimensional discrete wave element conversion has so far not been limited to image compression, such as audio processing, electronic graphics, numerical analysis, radar target identification, etc., which have great application costs. The architecture used to perform the two-dimensional discrete wave element conversion technology is mainly composed of complex frequency; mu 11 filter (mu 11 iratefi 11 ers), because of the huge amount of data it needs to process, It has a pivotal position in practical applications. The two-dimensional discrete wave element conversion using a discrete FIR filter has the following mathematical formula: χ Llin \, n2) = κ-ικ-ι = ΣΣ ^ 1) .δ (Σ · 2). 2 , -0 2 ^ -0 ΧΙZ (2 ^ 1-21) (2 ^ 2- ^ 2) (1 ΧΙΗ ^ ηΐ ^ η2) = κ-ι κ-ι = ΣΣ§ (2 · 1) · Α (2 · 2) · Z | " 0-? Ι) (2 «2 (2) ^ (« ι ^ 2) = ΣΣΑ ^ ι) · ^ ¢ 2) -ϊι) (2 «2 -i2) (3) 497356

V. Description of the invention (2) J {丨 -1You-1 2 | -〇2 ^ -0 2 • ^) (4) In the above formula / J 疋 Number of layers for frequency division of one-dimensional discrete wave element conversion, ρ, please Suppression from the length 'g (η) and h (: η) discriminate you, s, check a K 疋 filter state, the ancient cry h (n) knife is a low-pass chirp waver G (z) and high-pass The impulse response of the filter port H (z) (impuise re. R 1 π)) is the input image. ㈠, the (2) generation is shown in the figure below. It is a three-dimensional two-dimensional discrete wave element conversion diagram

ί Qingbo: No .: F than 丄 evel) contains two stages, the first stage performs water filtering and the first one performs vertical filtering. In the first frequency division, the input image size is Nx N. So at 屮 66% for i 4 », the frequency is input X π υτ ^ υπ-, and the output & image is a subband with a size of N / 2X N / 2; in the second layer The frequency division 珣, ~ image is the LL frequency band, and the output image is three sub-bands: LLLH, LLHL, and LLHH, all of which are n / 4 XN / 4; in the third frequency division, the input image is the LLLL frequency band The output image is (LL) 2LL, (LL) 2LH, (LL) 2HL, and (LLVHH) four sub-bands, all of which are N / 8x N / 8. The frequency division of more layers can be deduced by analogy.

Among the many architectures used today to perform two-dimensional discrete wavelet transformations, the most common one is a parallel filter architecture (p a r a 1 1 e 1 f i 11 e r archi tecture). The design of the parallel filter architecture mainly uses a modified recursive pyramid algorithm (MRPA), which intersperses the operations of the second and subsequent layers in the operations of the first layer. Originally, MRPA was applied in one-dimensional discrete

Page 6 497356 V. Description of the invention (3) In wave element conversion, the amount of data to be processed in each layer is half of that in the previous layer because of the decrement operation, so the total amount of data to be processed is: j Σ N-NN 2 22

N + N… +-= 2'-1 (5) In the above formula, J is the number of frequency division layers, N is the amount of data to be processed in the first frequency division, and N / 2 is the second frequency division. The amount of data to process, and so on,

N / 2 ^ is the amount of data to be processed in the frequency division of the Jth layer. If J is large enough, then the formula (5) will become: 2 (l-2-J) N ^ 2N = N + N (β)

It can be seen that the amount of data (N) to be processed in the second layer and beyond is the same as the amount of data (N) to be processed in the first layer, so the computing time of the first layer can be filled. Please refer to the second figure. At this time, the calculation time of each layer is filled, and the hardware can be fully used. Therefore, MRPA is applicable to the technology of one-dimensional discrete wave element conversion. However, we have found that MRP Α is not suitable for the technology of two-dimensional discrete wave element conversion. Please refer to the third figure. At this time, the amount of data to be processed in each layer is only a quarter of the previous layer, so the amount of data to be processed is as follows:

Page 7 497356 V. Description of the invention (4) N2-l · N2 N2 N2 N2 / 7 + 7 +… + ^ ΓΓ (7) where J is the number of frequency division layers, and N 2 is the frequency division layer in the first layer. The amount of data to be processed, N 2/4 is the amount of data to be processed in the second layer frequency division, and so on, N 2/4 I-1 is the amount of data to be processed in the J layer frequency division. When When J is large enough, the formula (7) will become:-{\-A ^ j) N2 ^ -N2 = N2 ^ -N2 / r 3 3 3 (i From this we can know the data to be processed in the second layer and later The amount (N 2/3) is only one-third of the first layer (N 2), so the computing time of the first layer cannot be filled, resulting in idle hardware and low utilization rate, and requires complex control circuits to Processes the interleaved data streams between layers. Please refer to Figure 4, which is a schematic diagram of a parallel filter architecture, which mainly includes four filters and wave filters: Hor 1, Hor 2, Ver 1, Ver 2, and two Transpose memory: Storage 1 and Storage 2. Hor 1 performs the horizontal filtering of the first layer, and 〇 〇 2 performs the second horizontal filtering and all subsequent filtering, V er 1 and V er 2 performs all See the fifth figure, which is the parallel filter of the fourth figure, when the two-dimensional discrete wave element conversion is performed, the work distribution diagram of the four filters, from the fifth figure we can find four filters When the number of frequency division layers is different, its individual and overall average hardware utilization, where

497356 V. Description of the invention (5) J is the number of frequency division layers: Hor 1: 1

Ver Σ 1 · U 丄 + 2-4 ^ 1 2 8 32 2_4J_1 3 er Σ Z-l 2-4 ^ 1 2 8 32 2-4 ^ 1: (1-4,

Hor 士士 ... · ^ 4 (i—4_ (, (9) (10) (ID (12)

Average: (Hor 1 + Ver 1 + Ver 2 + Hor 2) (13) Erlu (1-4_J)

The first table lists the hardware utilization of the parallel filter architecture at different frequency division levels. We can find that with only one frequency division, the hardware utilization of the parallel filter architecture is only 50%. As the number of frequency division layers increases, the utilization rate will converge to 6 6. 6 7%, so its hardware utilization rate is not high and it requires a long computing time. This is a parallel filter architecture and is currently used to implement The biggest disadvantage of the hardware architecture design of two-dimensional discrete wave element conversion. Due to the lack of knowledge, I have studied carefully

Page 9 497356 V. Description of the invention (6) Combining the spirit of perseverance, a framework with 100% private utilization rate, fast calculation time, regular data flow and low control complexity was developed. The following is a description of this case. The purpose of this case is to develop an architecture suitable for performing two-dimensional discrete wave element conversion, so that the architecture has 100% hardware utilization, fast computing time, regular data flow, and low control complexity. According to the idea of this case, this case is a framework suitable for performing two-dimensional discrete wavelet transform (2D-DWT), which is applied to an image compression system, and is used to perform complex frequency division calculations. Dividing an original image data into a plurality of frequency bands, including: a conversion module for frequency dividing an input image data into four frequency bands, and a frequency band with low frequency in the horizontal and vertical directions is used as the next time Input image data for frequency division operation; and a multiplexer for selecting image data that is intended to be fed into the conversion module. According to the concept of the present case, the architecture further includes a memory module for storing the frequency band with low frequency in both the horizontal direction and the vertical direction. According to the concept of the present case, the conversion module includes a first stage for performing a horizontal filtering operation and a second stage for performing a vertical filtering operation. According to the idea of the present case, the coefficients of the first-order filter are decomposed into an odd-numbered part and an even-numbered part using a polyphase decomposition technique. According to the idea of the present case, the coefficients of the second-order filter adopt a coefficient folding technique so that every two of the coefficients share a set of multipliers, adders, and registers.

Page 10 V. Description of the invention (7) According to the idea of the present case, the second generation includes: a plurality of register regions, and the register is a row of temporary frequency division layers; a plurality of one-to-two and The number is the demultiplexer of the architecture, and eight η is (lx 2 to accept the input of a register area i * 2 between a plurality of temporary storage blocks ::-one output becomes the next register two to two Solution 2: Become the output of the register of the column; and a plurality of-output Si "al" 'are electrically connected to each of the' select ^ 'lines (select the output of the 1x2 multiplexer. 胄 -solution Multiplexer to select

According to the concept of the present case, the size of the memory module is a quarter of the size of the original image. Another aspect of the case is a framework suitable for performing two-dimensional discrete wavelet transform (2D ~ DWT), which is applied to an image compression system to perform single-layer frequency division operations. To divide an original image data into four frequency bands, which includes: a conversion module for dividing the original image data into four cheek bands. According to another aspect of the case, the conversion module includes a first stage for performing a horizontal filtering operation and a second stage for performing a vertical filtering operation. According to another aspect of the case, the system and number system of the first-order filter are decomposed into odd-numbered and even-numbered parts using a polyphase decomposition technique. According to another aspect of the present case, wherein the filtering according to the second order

Page 11 497356 V. Description of the invention (8) The coefficients of the ~ 'device use the technology of coefficient folding so that every two of the coefficients share a set of multipliers, adders and registers. This case can be explained in more detail with the following illustrations to gain a deeper understanding. 'The components included in the illustration of this case are listed as follows: Conversion module 71 Multiplexer 72 Memory module 7 3 Filter 81 Frequency converter 8 2 Please refer to the sixth figure, which is the two-dimensional implementation of this case Hardware architecture diagram of discrete wave element conversion, which includes a transf ornl module 71, a multiplexer 72, and a memory module 73, wherein the memory module 73 The size is N / 2χ N / 2. The method for performing the frequency division operation is described as follows: In the first layer of frequency division, the multiplexer 7 2 selects the input image and enters the conversion module 71. The conversion module 7 waits for its frequency division to be LL, LH, HL, HH four sub-bands, and stores the LL band back into the memory module 73. After the frequency division of the first layer is completed in this way, the multiplexer 7 2 selects data from the memory 73 and sends the LL frequency band to the conversion module 7 1 for frequency division of the second layer. The LL frequency band is divided into LLLL and LLLH. Four sub-bands, LLHL, LLHH, and stores the LLLL band back into the memory module 73. After completing the frequency division of the second layer in this way, the multiplexer 7 2 selects data from the memory 7 3 and sends the LLLL frequency band to the conversion module 71 for frequency division of the third layer to divide the LLLL frequency band (LL). 2LL, (LL) 2LH, (LL) 2HL, (LL) 2HH four sub-bands, and store the (LL) 2LL band back into the memory module 73. This is repeated until the desired layer J is reached. If the number of frequency division layers is single

Page 12 497356 V. Description of the invention (9) layer, that is, if only one frequency division operation is needed, the memory module 7 3 and the multiplexer 7 2 can be omitted, and the output of the conversion module 71 is LL, LH, HL, HH four sub-bands. The advantage of this approach is that the data flow (d a t a f 1 〇 w) is quite regular, so we can focus our attention on the design of the conversion module. Please refer to the seventh figure, where the conversion module is tree-structured »It contains two stages, the first stage performs the horizontal filtering operation, and the second stage performs the vertical filtering operation. In order to effectively design the conversion module Suppose that the hardware area required for the first order is a and the operation time is t. From the seventh figure, we can see that in the original design, the number of filters required for the second order is twice that of the first order, that is, Say, the required hardware area for the second stage is 2a. On the other hand, because the first stage performs a frequency reduction operation, the amount of data required for each filter in the second stage will be half of the first stage, so the operation time required for the second stage is t / 2, However, because the second-stage operation must wait for the first-stage operation, the 2nd-stage hardware performance has 2ax (tt / 2) = at idle, which means that the original design of the conversion module was not efficient. In order to solve these problems, we first consider a single reduction filter. Referring to FIG. 8, the frequency reduction filter is composed of a filter 81 (fi Iter) followed by a frequency reducer 8 2 (t w 〇-f ο 1 d e d d e c i m a t 〇 r). However, because of the downconverter, every two strokes of the filtered data are discarded, resulting in a great waste of filter hardware. Therefore, I have adopted two different techniques to increase its hardware efficiency. The first is multiphase decomposition

Page 13 497356 V. Description of the invention (10) (polyphase decomposition) technology, such as the eight beans in Figure 9 and the polyphase decomposition technology of the down-frequency filter, it will filter 1 'Zhao, Bawei, even number and Odd numbered two parts. In the even numbered clock cycle, 20% of the data enters the odd numbered part and is multiplied by two with the odd numbered coefficient. In the entered clock cycle, the input data is entered into the even numbered part and compared with The coefficients are multiplied, and the output is the odd part and the even part. After using polyphase decomposition technology, because the internal working clock rate = -_ of the input clock rate, we can turn the data around. = Between two 彳 σ, so that the amount of data is the same, the operation time is halved, and the frequency reduction of the mining phase decomposition technology = the second technique of the tenth figure: =: 2L = f = rf ° ldlng), such as (muitiPlier ), An adder (adder) and a register (rs switch) switch the path of the data stream 'the working principle ^ First of all, it will be explained for PE0, in the 0th clock cycle, input = 0) and coefficient multiply al and add the register to the value in (initial ,,) 'and Results a 1 X (0) is stored again in register R〇. In the 7th tuning period, the input data x (1) is multiplied by the coefficient a0, and is added to the register M ::::, two X (〇 二 'and then the result a ° X (1) + alx (0). In the first: Temple: Period 'input data χ (2) and coefficients, the value of m is a2x⑴ + a3x (〇), and then the result is temporarily a2x (l) + a3x (〇 ) And then stored in the register r〇〇 (the data x (3) multiplied by the coefficient a0 W, and = cycle 'input f is stored as the value in R0, ie

The description of the invention on page 14 (11) am ^ a2X (ma3x (〇), and then output the results. The next clock cycle is similar to PE0 with ^. Οσ 1 because it is shared by every two coefficients. Multiplying state, adder and temporarily left. Σ π ~ the body area is reduced from Α to Α / 2, so this technique can reduce the time required for :; the filter timing s. The second table lists the outline number folding technique. The target reduction ^ on if =: the company I have two techniques for the first-order and second-order frequency reduction filters, as shown in the four tables, we can find: get four different The design method is the same as the first technique, and the second stage adopts the multi-phase decomposition technique when the area area A is used to calculate the door and plate folding technology. Then the first and second stage stones are more 2a. The calculation time 0 is reduced to ΐ / 2. At this time, any filters and wave filters in the total hardware area are idle ^ its / multiplying to ^, and the inefficiency can be improved to the original two households: pair & 〃 = ° The overall design method of the brother conversion branch group will make H: the shape listed in the fourth table, so the hardware of the first-order filter is not idle. Therefore, j is not an efficient design strategy. ^ Raster stores a row of data in order to store the data. This coefficient requires a column register to temporarily store it. It must be changed to a column temporary test. The Temporary Qin column of 改 in the figure is light — ° See the eleventh figure of the brother. It is the data of the input column in Figure 10 — Λ (n) Table _, for every two structures, it is selected by V / V " t two graphs (a; is the column temporary, release L 旒 (select Slgnal), in order N / 2J,

Page 15 497356 V. Description of the invention (12) n / 2 ", ... ’N / 8, N / 4, N / 2’ and J register blocks,

The size is N / 2 'N / 2' N / 2J 'N / 2J_2, ..., N / 16 n / R D: composition, and J is the number of frequency division layers. At the time of frequency division in different layers, the relationship between the number ^ and the size of the register is explained as follows: ^ When the frequency division of the first layer, the selection signal N / 2 is the size of the register and all j registers The sum of the memory block and the remainder is 0. At this time, the column + ... (14) When the frequency division of the second layer is selected, the size of the column register at the time of selection is the first j- 丨 1's and the rest is 0, 廿Knowledge of the sub-block · 16 = When the frequency of the third layer is divided, when the selection signal N / 8 is (15), the size of the column register is the first J-2 register 1 and the rest is 0. And: ^ NN Ν ν fj ν + · ^ + ρ ^ _ ·· + ί = ^

16 R (16) By analogy, when the frequency division of the J-2 layer is 1, the rest is 0. At this time, the size of the column register Λ, and the selection signal N / Π are] W are 3 Register block

V. Sum of Invention Description (13) ·

N N

N 17) I: at the time of frequency division, the selection signal N / 2, 1, the size of the temporary storage benefit of A at the end of the two previous register areas is 0, A < and: (18) In the division of the J layer, the size of the column register when the signal N / 2 is selected is the first one, and the remainder is 0. Therefore, in the division of the first layer, the two are temporarily divided into two: N / 2,筮 s 八 姑 a can be stored, and the length of the existing state is I. Next, in the / th V :, flat ^ ^ ^ ^ N / 4, ^ ^ of "", and then halve the i 6, and so on, minus / is = the electrical connection in the second and fourth layer of the twelfth figure Yu Dixi: Figure η: It is the first and its input-turn-out relationship. One of them is a solution tool, J see figure 13. It is a conversion model designed by using these two technologies for this case. ：： set ： 1… coefficients: a., Small a2, a3, high pass 遽

V. Description of the invention (14) bO, bl, b2, such as ... F IR is directly 幵 彡 ★ In the step-down frequency reduction filter, Wuqiu is used; to PI V is used to make it, so the low-pass filter is high. 〇 people use ::: the same register. Although we assume that the first and the following Jt wave filters can: have: the same length I, but in practical applications it is not: the second-order chirp wave: 'two is used in the first-order down-frequency filter using polyphase :: Yes, half of this pulse rate. The fourteenth figure is the intention of the data input. Taking an 8x8 image block as an example, the _f scattered wave element conversion finally obtains 4 lx 1 pixels in the third layer. After the division of the first layer, the timing relationship of the clock cycle is based on the internal and listed in the fourteenth clock cycle. There are two data inputs. -Frequency division of the layer '帛 32 to 39 clock cycle execution cycle' Perform the third clock cycle to perform the frequency division of the third layer. Structure: It has regularity ', so it is easy to expand to multiple frequency divisions, + limited by the type. The response wave is the coefficient. Among the architectures that perform two-dimensional discrete wave element conversion today, the more representative are: Parallel filter architecture (direct architecture), direct architecture, non-separated architecture (non -separable architecture), SIMD architecture, and systolic-parallel architecture. Please refer to the seventh table. I compare the architecture mentioned in this case with the representative architecture listed above. The comparison items include the number of multipliers, the number of adders, memory size, operation time, control complexity, hardware Body utilization, etc. Calculation time has been adjusted to

Page 18 497356 V. Description of the invention (15) The same clock rate, unit Λ degree, ρ is the image size, and is 'time: period' parameter κ is the length of the filter as follows: J is the number of knife frequency layers, The calculation time of this case is τ: +-^ + ill. 4. -l 2 19) 1 2 4 42 43 +-+ ^ r) = | (l-4- ^ In the above formula, the first factor 1 / 2 θ rate is the external data input clock rate = one: At the pulse speed speed of the internal work in this case, we can set the clock of the data input to the same hardware as the required computing time. From the seventh, the rate It is doubled to reduce the structure significantly better than other architectures. Θ is more than the framework and hardware utilization rate mentioned in this case. 疋 The time and complexity of control are different. When the number of frequency division layers is different, the ratio of the parallel filter structure of the basin = two passes is compared—the parallelism, the ancient time force, the suspended operation time, and the hardware use will make it the second and the first. "Congmu uses MRPA to design. In the eighth table, the comparison results are shown. The calculation time when inserting the frequency division number in the brother-layer calculation is five. The fifteenth figure shows that the two are at different degrees. It can be found that only when there is only one level of knife frequency (J = 1), the calculation in this case ^ (1 ^ 4-1) clock cycle, P #eight phase gtf is 3 ) N2 2 0. 5N2 ~ w 'j The nearest division frequency layer is tossed 2 (J > 4), the operation time converges to 3 0 ~ 4 ^) Q. However, the parallel filter architecture

Page 19 3 Ν24 · 6 7N_Clock cycle 497356 V. Description of the invention (16) The operation time m of the clock cycle is always required. 50 /. As the number of frequency division layers increases (J > 7), the hardware converges to 66 -67%, and the architecture proposed in this case can always use the hardware. Lu Fu 1 u U / 〇

Regarding the memory requirements, this case requires a memory module 3 of size N / 2x \ / 2 to store intermediate data during the operation. However, if the processed image is already stored in the memory, such as a digital camera, we can use the same memory to store these intermediate data ', that is, the original image is used as the input of the (LL) band. In this case, the memory module will not be needed in this case, and NV 4 in the seventh table can be removed, so the required memory can be greatly reduced.

In order to meet the needs of real-time processing, many architectures have been proposed for performing two-dimensional discrete wave conversions. However, the low hardware utilization and the long computing time are the biggest disadvantages of these architectures. Therefore, this case proposes an effective architecture for the above disadvantages, and the architecture has been correctly verified by the Veri hardware description language. To sum up, the advantages of the architecture proposed in this case are 100% hardware utilization, fast computing time, regular data flow and low control complexity, so the architecture proposed in this case is very suitable for the new generation. Image compression standards, such as JPEG-2000 and MPEG-4. The reason is that “this case can be decorated by people who are familiar with this skill, but they are all as good as those who want to protect the scope of patent application.

Page 497356 Schematic description of the first diagram • It is a schematic diagram of a three-layer two-dimensional discrete wave element conversion. The second diagram; it is a conventional modified recursive pyramid algorithm (MRPA) applied to one-dimensional discrete Schematic diagram of wave element conversion (1- -D DWT); Figure 2 • It is a schematic diagram of the conventional modified recursive pyramid algorithm (MRPA) applied to two-dimensional discrete wave element transformation (2--D DWT); Figure 4 is a schematic diagram of a conventional parallel filter architecture; Figure 5 is a diagram of the work of a conventional parallel filter architecture; Figure 6 is a schematic diagram of the implementation of a two-dimensional discrete wave element conversion architecture in this case. Fig. 7 is a conversion module with a tree structure; Fig. 8 is a schematic diagram of a down-frequency filter with a frequency reduction of 2; Fig. 9 is a structural diagram of a down-frequency filter using polyphase decomposition technology. The tenth picture is collected Structure diagram of the frequency reduction filter of the coefficient folding technology; Figure 11 • This is the structure of the frequency reduction filter after the register of Figure 10 is changed to the column register Figure 5 Figure 12 (A) ·· Figure 12 shows the structure of a column register; Figure 12 (B): It shows a pair of two-demultiplexer and its input-output relationship electrically connected to the register of the column; Figure 13: It is the structure diagram of the conversion module of the case; Figure 14: It is a schematic diagram of the three-dimensional two-dimensional discrete wave element conversion of the case; Figure 15: It is the structure of the case and the conventional parallel filter structure Comparison chart of calculation time; and Figure 16. It is the hardware of this case and the conventional parallel filter structure.

Page 21 497356 Schematic illustration of body utilization comparison chart.

Claims (1)

497356 VI. Application for patent scope 1. A structure suitable for performing two-dimensional discrete wavelet tr an sf〇rm, which is used to perform the frequency division operation of the 4th complex Lou Zhang layer to divide The original image data is divided into a plurality of frequency bands, including: a conversion module for dividing an input image data into four frequency bands, and a frequency band with low frequencies in the horizontal and vertical directions is used as the next frequency division The input image data for the operation; and a multiplexer for selecting the image data that is intended to be fed into the conversion module. 2. The architecture described in item 1 of the scope of patent application, wherein the architecture further includes a memory module for storing the frequency band with low frequency in both the horizontal and vertical directions. 3. The architecture described in item 1 of the patent application scope, wherein the conversion module includes a first stage for performing a horizontal filtering operation and a second stage for performing a vertical filtering operation. 4. The architecture described in item 3 of the scope of patent application, wherein the first-order filter coefficients are decomposed into odd-numbered and even-numbered parts using a polyphase decomposition technique. 5. The architecture described in item 3 of the scope of the patent application, wherein the second-order filter coefficient is a coefficient folding technique so that every two of the coefficients share a group of multipliers, adders, and registers. 6. The architecture described in item 5 of the scope of patent application, wherein the register is a row of registers, including: a plurality of register blocks, and the number of which is the frequency division layer of the architecture; 497356 6. The scope of the patent application is a plurality of one-to-two demultiplexers (lx 2 demultiplexer), which are electrically connected between the plurality of register blocks to accept the output of one register block as an input, and One output of the one-to-two demultiplexer becomes the input of the next register block, and the other output becomes the output of the register of the column; and a plurality of selection signal lines (se 1 ectsigna 1) are electrically connected respectively. Select the output of the one-to-two demultiplexer for each one-to-two demultiplexer. 7. The architecture described in item 2 of the scope of patent application, wherein the size of the memory module is a quarter of the size of the original image data. 8. —Applicable to a two-dimensional discrete wavelet transform architecture, which performs a single-layer frequency division operation to divide an original image data into four frequency bands, including: The conversion module is used for frequency-dividing an original image data into four frequency bands. 9. The architecture described in item 8 of the scope of patent application, wherein the conversion modules each include a first stage for performing a horizontal filtering operation and a second stage for performing a vertical filtering operation. 10. The architecture described in item 9 of the scope of the patent application, wherein the first-order filter coefficients are decomposed into odd-numbered and even-numbered parts using a polyphase decomposition technique. 11. The architecture as described in item 9 of the scope of patent application, wherein the second-order filter coefficients use a coefficient folding technique so that every two of the coefficients are shared Page 24 497356 6. Scope of Patent Application A set of multipliers, adders and registers. Page 25 111