497257 A7 B7 五、發明說明（ 發明背景 1 ·發明範圍 本發明和一半導體記憶體裝置及其製造方法，更特別是 和-高積㈣揮發性記憶體裝置及其製造方法有關。 2 .相關技術描述， 能形成-高積體非揮發性記憶體裝置，需降低該裝置 ，大。已使用-自行校準源極㈣處理來降低記憶體 早凡。陣列之大小。孩自行校準源極蚀刻處理之範例揭 於 US 專利 Νο· 5，120,671 及 5 47〇7乃。 圖1是依照以上二專利形成之非揮發性記憶體裝置，如 快閃記憶體裝置之佈圖，圖2是沿圖W示之線•剖 示 圖 面 參考編號10代表一作用區型；參考編號2〇代表一浮 型；參考編號30代表一控制閘型；參考編號5〇代表一位 線接觸型；參考編號60代表一位元線型；參考編號7〇代 一共源極線接觸型，·以及參考編號8〇代表一共源極線型 在以上專利’連接一字凡線方向之相鄭單元源極區所 需之源極線擴散層不是在該作用區間形成。將一場氧化層 蝕刻，及在其下形成一源極擴散層以連接字元線方向之相 鄰單元源極區。因此無需維持該字元線及該源極線擴散層 間之絕緣距離，則可曄低記憶體單元陣列之大小。 均 現在大略描述該二專利揭示之方法。首先於一場氧化層 12足義之一半導體基層5作用區形成一疊閘。該疊閘由曰 澱一透納氧化物15、一浮閘20、_絕緣層25及控制閘 元 表 必 沉 30 -4 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱 5 2 97 4 A7 , ---- B7 " ~ ----- 五、發明說明（） 而形成。一氧化物間隔物3 2在該疊閘之側牆形成。接著形 成一字元線方向之相鄰氧化層12及一源極區之曝光光罩， 然後由自行校準源極蝕刻去除該場氧化層12。然後於該曝 光基體注入N +型離子，以形成一和該字元線（圖1之3〇)平 行之源極線擴散層4 1。該氧化物間隔物3 2可在該自行校準 源極姓刻後形成。將離子注入該源極及汲極區以完成一没 極區42及源極區43。沉澱一絕緣層47，然後由一照相石 版處理形成將該汲極區42曝光之一接觸孔5〇及將該源極區 46曝光之一接觸孔7〇。接著，一金屬層在該所得架構整個 表面沉澱，然後圖型化以完成一位元線6 〇及一共源極線 80 〇 依照本方法，在自行校準源極蚀刻中，除了該場氧化層 1 2也蝕刻形成該源極區4 3之作用區。換言之，該作用區之 矽基體過蝕刻爲厚度300人或更多，這將造成該源極區蝕刻 損傷。此損傷降低電荷保留能力。此蝕刻損傷可由徐冷處 理復原。但該徐冷必需以範圍9〇〇_1〇〇〇。〇範圍之高溫進 行，這會造成其它問題。 在傳統之非揮發性記憶體裝置，因各單元之源極區4 3及 共源極線80經該源極線擴散層42/相連，依該高積體降低之 單元大小降低該源極線擴散層區域，將增加源極阻抗。若 泫源極阻抗增加，該單元作用中之放電速度降低，這使該 單元之性能劣化。爲避免此問題，和一共源極線8 〇相連之 源極區4 3數目必需降低。換言之，在一單元陣列需形成更 多共源極線。共源極線80數目增加不利地將增加該單元陣 -5- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公 (請先閱讀背面之注意事項再填寫本頁) ^裝--------訂·--------， 經濟部智慧財產局員工消費合作社印制衣 3 3 五、 發明説明（ 列區域。 、另外’依照上述 < 專利，考量到％成該位元線接肩孔5 〇 〈照相石版處理之處理餘裕，必需確保該φ閘及該位元線 接觸孔5 0間有足夠之阳M T m tl ^ J心幻炙距離！^。因此，一位元線方向之積體 程度提升是有限的。 發明概論 、為能解決以上問題，本發明之一目的是利用提供一新的 源極線及一自仃权正接觸提供一高積體非揮發性記憶體裝 置。 本發明 < 另一目的是提供一適於製造具有一新的源極線 及一自行权準接觸之高積體非揮發性記憶體裝置之方法。 因此提供一非揮發性記憶體裝置，包含：多個作用區在 一半導體基體上形成及由多個平行延伸之絕緣區定義；多 個和該作用區垂直之疊閘，各疊閘包含一第一閘及一第二 閘，該第一閘和該半導體基體絕緣及在該作用區及絕緣區 之一些邵份’及該第二閘和該第一閘絕緣及接著在該第一 閘及絕緣區形成；多個源極區在該疊閘間之作用區形成； 經濟部智慧財產局員工消費合作社印製 多個第一接觸孔和該等疊閘自行校準，在該半導體基體之 中間介電層形成，及將該疊閘之該絕緣區域及源極區曝光 和遠®閘平行；多個*源極墊線在該第一接觸孔形成及連接 該曝光之源極區，和該疊閘平行；及一源極線和該源極墊 線連接，及和該作用區平行。 另外，該非揮發性記憶體裝置亦包含··多個汲極區在該 ®間間之作用區形成；多個第二接觸孔和該等疊閘自行校 -6 - 表紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 497257 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 準’在该半導體基體上一第一中間介電層形成，及將該没 極區曝光’多個插頭於該第二接觸孔形成及連接該汲極 區；及多個位元線和與該絕緣區平行配置之該等插頭相 連，及和該作用區平行。 在本發明’一蝕刻止子更佳地在該堆疊狀態之頂及側牆 形成。另外’於該第一接觸孔形成之插頭極佳地由阻抗低 於一種雜質擴散層阻抗之一金屬形成。另外，該插頭及該 源極墊線具有實質上共面之頂表面。 爲達成該第二目的，提供一製造非揮發性記憶體裝置之 方法，包含以下步驟：（a)提供一半導體基體；（b)由形成 多個在一半導體基體平行延伸之絕緣區定義多個作用區； (C )形成多個疊閘包含多個第一閘和該半導體基體絕緣及在 該作用區及絕緣區之一些部份形成，及多個第二閘和該第 一閘絕緣’於該第一閘及絕緣區形成和該等作用區垂直； (d)由於該疊閘間之作用區注入雜質，形成多個源極區及多 個汲極區；（e)於形成該等源極及汲極區之該所得架構形成 一第一中間介電層；（f)由將該第一中間介電層圖型化形成 將该®閘間之絕緣區域及源極區曝光之多個第一接觸孔， 和該疊閘平行；以及（g)在該第一接觸孔形成多個源極墊線 連接該源極區，和該疊閘平行。 接著在步驟（g)後挺彳共步驟（h)於形成該等源極墊線之所 得架構形成一第二中間介電層，（i)利用將該第二中間介電 層圖型化形成多個通孔，將該等墊線曝光，以及（j )填滿該 通孔’連接该源極塾線及形成和該作用區平行之一源極 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---1------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 五、發明説明（5 ) 線。 在本發明，步騾（f)由使用單一光罩形成該等第一接觸孔 及多個將該等疊閘間之汲極區曝光之第二接觸孔而執行， 及步騾（g)由形成該第二接觸孔之源極墊線及插頭而執行。 特別是’在步驟（e )前另提供在該疊閘頂及側牆形成一蚀 刻止子層之步騾，及其中步騾（f)由形成和該疊閘及該蝕刻 止子層自行校準之第一及第二接觸孔而執行。 另外’在步騾（f)後另提供使用光罩在該第一及第二接觸 孔曝光之源極及汲極區注入插頭離子之步驟。 依…、本發明，因相鄰單元之源極區和一源極塾線連接， 則可降低總單元陣列區域所需之共源極線數目。另提供自 行校準位元線接觸孔，以降低一疊閘及該位元線接觸孔距 離，因此使單元陣列區域之大小最小化。 圖式簡述 本發明以上之目的及優點由參照附圖詳細描述一較佳實 施例而較清楚，其中： 圖1是傳統快閃記憶體裝置之一單元陣列部份佈圖； 圖2是沿圖1中線π -1Γ之剖面圖； 經濟部智慧財產局員工消費合作社印製 圖3是依照本發明一實施例之快閃記憶體裝置單元陣列部 份佈圖； 二 圖4是圖3所示之快閃記憶體裝置等效電路圖； 圖5是沿圖3中線V - V ·之剖面圖； 圖6至1 3是沿線V-V’，圖3所示之快閃記憶體裝置製程 中產生之架構剖面圖；以及 ___-8- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X M7公釐） A7 B7 五、 發明說明（ 6 圖1 4及1 5疋/σ線V _ v ,，圖3所示之快閃記憶體裝置另一 1程產生之架構剖面圖。 較佳實施例描述 以下由參照附圖，描述本發明較佳實施例將詳細描述本 =本發明並不受以下實施例限制，並可以各種形式 ς:。这些實施例只是要對—般具有本技術者完全揭示本 :::完全透露本發明之觀念。爲求清楚在整個圖 =各種裝置之元件、其間之位間_及各種 度。在圖式中相同之元件全以相同之編號表示。 圖3是依照本發明—實施例之㈣記憶 :卩份佈圖，及圖4是圖3所示之快閃記憶體裝置之♦早效;車: 訂 ."ΙΓ,Γ,ίο：；!；*： 110 *—« 么丁 做馬子兀線心控制閘型，夂麥绝 :;4°表示-位元線接觸孔型，參考編號U5表：—= ，、泉接觸孔型，參考編號表示_位元 会Η、土 16〇表示一位元線型，參考編— ，/考編號 考编號1 80矣-4 表737 —源極線通孔，參497257 A7 B7 V. Description of the invention (Background of the invention 1) Scope of the invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a high-volume volatile memory device and a manufacturing method thereof. 2. Related technologies Description, can form-high-volume non-volatile memory device, need to reduce the device, large. Has been used-self-calibrating source ㈣ processing to reduce memory premature. Array size. Self-calibrating source etching process Examples are disclosed in US Patent Nos. 5,120,671 and 5 47〇7. Figure 1 is a layout of non-volatile memory devices, such as flash memory devices, formed according to the above two patents, and Figure 2 is shown along the figure. Line • Sectional drawing reference number 10 represents an active area type; reference number 20 represents a floating type; reference number 30 represents a control gate type; reference number 50 represents a single line contact type; reference number 60 represents one Bit line type; reference number 70 generation of a common source line contact type, and reference number 80 represents a common source line type in the above patent 'connecting a word where the line direction is the source of the Zheng unit source area The epipolar diffusion layer is not formed in the active region. An oxide layer is etched, and a source diffusion layer is formed thereunder to connect adjacent cell source regions in the direction of the word line. Therefore, there is no need to maintain the word line and the The insulation distance between the source line diffusion layers can reduce the size of the memory cell array. The methods disclosed in the two patents are now roughly described. First, a stack of gates is formed in the active area of the semiconductor substrate 5 which is one of the field oxide layers 12. The stacked gate is made of a transparent oxide 15, a floating gate 20, an insulating layer 25, and a control gate table 30 -4. This paper size is applicable to China National Standard (CNS) A4 (210 X 297) Love 5 2 97 4 A7, ---- B7 " ~ ----- 5. It is formed by the description of the invention. An oxide spacer 3 2 is formed on the side wall of the stack gate. Then a character is formed. The adjacent oxide layer 12 in the line direction and an exposure mask of a source region, and then the field oxide layer 12 is removed by self-aligning source etching. Then, N + type ions are implanted into the exposure substrate to form a sum of the characters. Lines (30 in FIG. 1) parallel to the source line diffusion layer 41. The oxidation The spacer 32 can be formed after the self-calibrated source electrode is engraved. Ions are implanted into the source and drain regions to complete an electrode region 42 and a source region 43. An insulating layer 47 is deposited, and then a photolithography The process forms a contact hole 50 that exposes the drain region 42 and a contact hole 70 that exposes the source region 46. Then, a metal layer is deposited on the entire surface of the resulting structure, and then patterned to complete a Bit line 6 0 and a total source line 80 0 according to this method, in the self-aligned source etching, in addition to the field oxide layer 12 is also etched to form the active region of the source region 43. In other words, the active region The silicon substrate is over-etched to a thickness of 300 people or more, which will cause etching damage to the source region. This damage reduces charge retention. This etching damage can be recovered by Xu cold treatment. But the Xu Leng must be in the range of 9000-1000. 〇 range of high temperature, which will cause other problems. In a conventional non-volatile memory device, since the source region 43 and the common source line 80 of each cell are connected via the source line diffusion layer 42 /, the source line is reduced according to the reduced cell size of the high volume. The area of the diffusion layer will increase the source impedance. If the radon source impedance is increased, the discharge rate of the cell will decrease, which will degrade the performance of the cell. To avoid this problem, the number of source regions 43 connected to a common source line 80 must be reduced. In other words, more common source lines need to be formed in a cell array. Increasing the number of common source lines 80 will adversely increase the unit array-5- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 male (please read the precautions on the back before filling this page) -------- Order · --------, Printing of clothing by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 3 V. Description of the invention (listed areas. In addition, in accordance with the above < patents, consider To the percentage line of the bit line shoulder hole 5 〇 <processing margin of photographic lithography processing, you must ensure that the φ gate and the bit line contact hole 50 between the sufficient MT MT tl ^ J heart magic distance! ^ Therefore, the degree of integration of the bit line direction is limited. In order to solve the above problems, an object of the present invention is to provide a new source line and a positive right contact to provide a high Integrated non-volatile memory device. Another object of the present invention is to provide a method suitable for manufacturing a high-volume non-volatile memory device with a new source line and a self-authorized contact. A non-volatile memory device including: a plurality of active regions in a semiconductor Formed on the substrate and defined by a plurality of parallel extending insulating regions; a plurality of stacked gates perpendicular to the active region, each stacked gate includes a first gate and a second gate, the first gate is insulated from the semiconductor substrate and Some of the active region and the insulating region, and the second gate and the first gate are insulated and then formed in the first gate and the insulating region; a plurality of source regions are formed in the active region between the stacked gates; The Ministry of Intellectual Property Bureau employee consumer cooperatives printed a number of first contact holes and self-calibration of these stack gates, formed in the intermediate dielectric layer of the semiconductor substrate, and exposed and isolated the insulating and source regions of the stack gate. ® gate parallel; a plurality of * source pad lines are formed in the first contact hole and connected to the exposed source region, and parallel to the stacked gate; and a source line is connected to the source pad line, and functions In addition, the non-volatile memory device also includes a plurality of drain regions formed in the active area of the ® space; multiple second contact holes and the stack gates are self-calibrated. China National Standard (CNS) A4 specification (210X297 mm) 497257 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () The first intermediate dielectric layer is formed on the semiconductor substrate, and the non-polar area is exposed. Multiple plugs are contacted on the second contact. A hole is formed and connected to the drain region; and a plurality of bit lines are connected to the plugs arranged in parallel with the insulation region, and are parallel to the active region. In the present invention, an etch stopper is more preferably in the stacked state. The top and side walls are formed. In addition, the plug formed in the first contact hole is formed of a metal having an impedance lower than that of an impurity diffusion layer. In addition, the plug and the source pad line are substantially coplanar. In order to achieve the second object, a method for manufacturing a non-volatile memory device is provided, which includes the following steps: (a) providing a semiconductor substrate; (b) forming a plurality of insulations extending in parallel on a semiconductor substrate Area defines multiple active areas; (C) forming multiple stacked gates including multiple first gates and the semiconductor substrate insulation and formed in the active region and some parts of the insulation region, and multiple second gates and the first brake The margin is formed by the first gate and the insulation region perpendicular to the active regions; (d) due to the implantation of impurities in the active region between the gates, multiple source regions and multiple drain regions are formed; (e) in the formation The resulting structure of the source and drain regions forms a first intermediate dielectric layer; (f) patterning the first intermediate dielectric layer to expose the insulation region and source region of the gate The plurality of first contact holes are parallel to the stacked gate; and (g) forming a plurality of source pad lines in the first contact hole to connect the source region and parallel to the stacked gate. Then, step (g) is followed by a total of step (h) to form a second intermediate dielectric layer on the resulting structures forming the source pads, (i) forming the second intermediate dielectric layer by patterning A plurality of through holes, exposing the pad lines, and (j) filling the through holes to connect the source squall line and form a source parallel to the active area. The paper dimensions are applicable to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) --- 1 ------------------ Order --------- (Please read the precautions on the back before filling (This page) 5. The invention description (5) line. In the present invention, step (f) is performed by using a single mask to form the first contact holes and a plurality of second contact holes that expose the drain regions between the gates, and step (g) is performed by This is performed by forming a source pad line and a plug of the second contact hole. In particular, 'step (e) is provided in addition to the step of forming an etch stop layer on the top and side walls of the stack gate, and the middle step (f) is self-aligned by the formation and the stack gate and the etch stop layer. The first and second contact holes. In addition, a step of implanting plug ions in the source and drain regions exposed by the first and second contact holes using a photomask is provided after step (f). According to the present invention, since the source regions of adjacent cells are connected to a source line, the number of common source lines required in the total cell array region can be reduced. A self-aligning bit line contact hole is also provided to reduce the distance between a stack of gates and the bit line contact hole, thereby minimizing the size of the cell array area. BRIEF DESCRIPTION OF THE DRAWINGS The above objects and advantages of the present invention are clearer by describing a preferred embodiment in detail with reference to the accompanying drawings, in which: FIG. 1 is a partial layout of a cell array of a conventional flash memory device; Figure 1 is a sectional view taken along the line π -1Γ; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs; Figure 3 is a layout diagram of a flash memory device unit array according to an embodiment of the present invention; Figure 5 shows the equivalent circuit diagram of the flash memory device; Figure 5 is a cross-sectional view taken along the line V-V · in Figure 3; Figures 6 to 13 are taken along the line V-V ', and the flash memory device manufacturing process shown in Figure 3 A cross-section of the structure produced in China; and ___- 8- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X M7 mm) A7 B7 V. Description of the invention (6 Figure 1 4 and 1 5 疋 / σ 线 V _v, A cross-sectional view of the architecture generated by the flash memory device shown in FIG. 3 in another pass. DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described in detail below with reference to the drawings. It is not limited to the following embodiments, and may be in various forms: These embodiments are only intended to be- Those skilled in the art have fully disclosed this :: fully disclosed the concept of the present invention. For the sake of clarity, the entire figure = the elements of various devices, the positions between them, and the degrees. In the drawings, the same elements are all numbered the same. Fig. 3 is a memory layout according to an embodiment of the present invention: a layout, and Fig. 4 is an early effect of the flash memory device shown in Fig. 3; car: order. &Quot; ΙΓ, Γ, ίο :;!; *: 110 * — «Modin is a horse-shaped line core control gate type, rye must :; 4 ° means-bit line contact hole type, reference number U5 table: — =, spring contact hole type ， Reference number indicates _bit yuan meeting, soil 160 indicates a one-line line type, reference series —, / test number test number 1 80 矣 -4 Table 737 — source line through hole, reference
表不一共源極線型，及參考編號190表亍韋开 線接觸孔型。 ^衣不一子7L 經濟部智慧財產局員工消費合作社印製 圖5疋沿圖3之線v - ν ’之剖面圖。 將參照圖3，4及5輪述依照本發明 置。依照本發明之快閃記憶體裝置可二::;=裝 其包含多個⑴作用區105，由多個 ：：二除料。 緣區102定義及於一半導體基體1〇〇 I延伸之絕 、 琢作用區105 9- 本紙張尺錢+關家標準（CNS)A4規格（210 X 297公^7 五 .經濟部智慧財產局員工消費合作社印製 發明説明（7) 7 中有^個（X X y)包含多個（χ χ y)浮閘ιι〇及多個（丫）控制閘 120之宜閘。該浮閘11〇在該作用區及絕緣區之一些部 伤形成。忒控制閘12〇做為字元線及經該作用區1〇5延伸。 在作用區1〇5及一控制閘120交叉之區域定義一晶胞。該 浮閘1 ίο由聚化矽形成及該控制閘12〇可由一單層聚化矽或 由一聚化矽層120A及一矽化物層12〇B組成之一多層形成。 遠浮問110由一插入之透納氧化物ισ6和該半導體基體1〇〇 之作用區隔絕。該控制閘12〇由一插入絕緣層115如具有高 介電常數I 一金屬氧化物材料或一氧化物及氮化物（〇Ν〇） 疊層絕緣層和該浮閘11 〇隔絕。 如源極區135及汲極區132之摻雜區於該疊閘Π0及120間 之作用區105形成。第一中間介電層型136ρ在該疊閘η〇& 120上沉澱。 該源極區135及該汲極區132分別由第一接觸孔145及第 二接觸孔140曝光。 該第一接觸孔145即源極墊線接觸孔，在該疊閘間和該字 元線120平行形成，以將該源極區135及和該源極135相鄰 之該絕緣區102在該字元線120之方向曝光。該第二接觸孔 140即汲極接觸孔，將該疊閘間之該等汲極區132曝光。此 時該第一及第二择觸孔145及140之形成，較佳地和該疊閘 繪 侧牆及上方之一氮化物層122自行校準。 在該字元線方向連接相鄰單元之源極區之源極墊緣145· 及位元線插頭140’分別在該第一接觸孔145及該第二接觸孔 140形成。該源極塾線145’及該位元線插頭140'較佳地由阻 -10- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閱讀背面之注意事項再 頁) 497257 A7 五、發明說明（ 抗低於該源極線擴散層（圖1之41)之金屬如鎢、鋁或銅形 成。 和孩等字元線120平行之該等源極墊線145，，經於一第二 中間介電層147形成以將該源極墊線145，曝光之通孔，和共 源極線180相連。該共源極線18〇和該作用區ι〇2平行。 該等位元線插頭140,經於該第二中間介電層147形成以將 該位元線插頭140,曝光之通孔15〇，和該位元線16〇相連。 該位元線160和垂直於該字元線12〇之該作用區1〇5平行。 於該源極墊線145’、該位元線插頭14〇,及該第一中間介電 層型136P上較佳地沉澱一蝕刻阻擋146。這是要防止在形 成孩通孔150及170之過程中，損害到該第一中間介電層型 136P。 如上述，相鄰晶胞之源極區和低阻抗金屬材質之該源極 墊線相連。因該源極墊線由阻抗較傳統源極線擴散層（圖2 之4 1)低之金屬形成，故其可較傳統源極擴散層連接更多 之源極區。因此不像傳統之技術在每16至32位元線必需提 供一共源極線，本發明只需在每3 2或更多位元線提供該共 源極線。因此该單元陣列區域可因一單元陣列區域中之共 源極線180數目降低而降低。 另外，爲形成該傳統之源極線擴散層（圖2之4丨），必需 蝕刻該場氧化層102，·這可能損害該作用區及降低電荷保 留能力。而在本發明，因該源極墊線145，在該自行校準接 觸孔形成，自行和該疊閘校準，根本地避免掉形成該源極 區之該作用區過蝕刻問題，因此改良裝置特性。 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱 (請先閱讀背面之注意事項再填寫本頁} 裝--------訂---------· 經濟部智慧財產局員工消費合作社印製 497257 A7 B7 五、發明說明（） ——J-------·!裝 (請先閱讀背面之注意事項再填寫本頁) 另外，因該位元線接觸會自行校準，則無需維持該字元 線120及接觸孔140間之距離（傳統技術中之L)，因此積體 改良。 以下參圖6至1 描述製造依照本發明之一快閃記憶體 裝置之單元陣列區域之方法。 參照圖6，一絕緣區1〇2在一半導體基體1〇〇上形成以定 義一作用區。接著一透納氧化物1〇6、一浮閘丨1〇、一絕緣 層115、一控制閘12〇及一蝕刻止子層122八於該作用區形 成，以形成疊閘。 孩控制閘120可由一單層聚化矽形成，但最好由一聚化矽 層120A及一矽化物層120B組成之一多層形成，以降低該控 制閘120之阻抗。該蝕刻止子122A防止該疊閘在接著形成 自行校準接觸孔之步驟曝光。因此該蝕刻止子層122A最好 由蝕刻率較該第一中間介電層（圖9之136)低之金屬形成， 如一氧化物層。例如該蝕刻止子層122A可爲一氮化物層、 一由氮化物層及一氧化物層形成之一雙層、或一氮氧化合 物層，厚度至2〇〇〇〜4〇〇〇。 經濟部智慧財產局員工消費合作社印製 接著如圖7及8所示，一汲極區132及一源極區135於一半 導體基體100之作用區形成。首先如圖7所示，將疊閘間之 作用區曝光之一第一光罩型13〇於該半導體基體1〇〇上形 成，然後將摻雜離子iii注入以形成該汲極區132。 接著’如圖8所示，於該疊閘側牆形成一蝕刻止子間隔 物，因此完成一蝕刻止子122。如同該蝕刻止子層122A， 孩蝕刻止子間隔物防止該疊閘在接著形成自行校準接觸孔 -12- 本紙張尺度適用中國國家標準（CNS)A4規格(210 X 297公爱了 497257 經濟部智慧財產局員工消費合作社印製 A7 B7 10 i、發明說明（） 之步骤曝光。因此該蚀刻止子間隔物最好由和於該疊閘頂 形成之蝕刻阻子層122A之相同材質形成，即具有較該第一 中間介電層（圖9之136)蝕刻率低之材質。例如一氮化物 層、一氮化物層及一氧化物層之一雙層、或一氮氧化合物 層沉殿至厚度500〜1000 A，然後回蝕刻以形成該間隔物。 在完成該钱刻止子122後，將該疊閘間之作用區曝光之一 第一光罩型133形成’然後將該掺雜離子134離子注入，因 此形成該源極區135。 在此實施例，形成該汲極區132之離子注入在構成該蝕刻 止子122之間隔物形成前執行，及形成該源極區135之離子 注入在形成該間隔物後執行。但依照該源極及汲極區之架 構，可變更該間隔物，該汲極區及該源極區之形成順序。 然後如圖9所示，該第一中間介電層136在該蝕刻止子 12 2上形成’充伤涵盖★亥登閉。該第一中間介電層13 6由分 別沉澱一高溫氧化物及一 BPSG層至厚度500〜1000 A及 4000〜6000，然後重新將之在溫度範圍850至900 °C流通1〇 至2 0分鐘而形成。定義該單元陣列之一位元線接觸部份及 一源極接觸部份之一第三光罩型137，在該第一中間介電 層136形成。 參照圖1 0，使用該第三光罩型137做爲一蝕刻光罩各向 異性地蝕刻該第一中間介電層136，因此形成一位元線接 觸孔140及一源極墊線接觸孔145，及在該疊閘頂留下一第 一中間介電層型136P。因容許一由該疊閘及該疊閘四週之 該蝕刻止子122執行校準之自行校準接觸處理，該位元線 -13- 本紙張尺度家標準(CNS)A4規格（210 X 297公釐） ---r------------------訂·-------- (請先閱讀背面之注意事項再填寫本頁) 497257 A7 B7 五、發明説明（H) 接觸孔140及該源極墊線接觸孔145可由一降低之設計準則 形成。因此可降低該單元陣列之大小。 接著，在遠位元線接觸孔140及該源極塾線接觸孔丨45曝 光之作用區，以5X10i3〜1X1〇15離子/平方公分之量使用 該第三光罩型137做為一離子注入光罩，執行砷或磷插頭一 離子-注入。在該位元線接觸孔14〇及該源極墊線接觸孔 145誤校準而偏離該汲極及源極區132及135時，該插頭-離 子- >王入由以該源極及汲極區之摻雜區適當覆蓋該位元線接 觸及源極墊線接觸，降低接觸阻抗。 在本發明，因咸位元線接觸孔i4〇及該源極塾線接觸孔 145由該自行校準接‘觸處理形成，形成接觸孔14〇及145及 該離子注入之處理可由使用單一光罩型137執行。因此該 處理較傳統之處理簡單。 經濟部智慧財產局員工消費合作社印製 參照圖11，在去除該第三光罩型137後，沉澱一金屬層 以填充泫位元線接觸孔140及該源極蟄線接觸孔丨45。然後 利用回蝕或化學機械拋光去除該位元線接觸孔14〇及該源 極塾線接觸孔145間外之該金屬層，形成一位元線插頭14〇, 及一源極墊線145’。因此該位元線插頭丨4〇，及源極墊線丨45， 之高度相同，則彼此頂表面同高。 孩金屬層最好由如，、鋁或銅之低阻抗金屬形成。因相 鄰單元之源極區利用此方式形成該源極墊線145，而連接， 則可降低源極阻抗。則因該單元陣列區域中之共源極線較 少’故可降低該單元陣列區域之大小。 參照圖1 2，在圖1 1所示之所得架構整個表面連續形成一 --------- 14 -_ 本紙張尺度適用中關家標準（CNS ) M規格（21QX297公釐） '- ^7257 A7 B7 五 、發明說明（ 12 蝕刻阻擋146及一第二中間介電層147。然後形成一第四光 罩型149定義將該位元線插頭140,及該源極墊線145,曝光之 通孔。 參照圖1 3，使用該第四光罩型149做爲一蝕刻光罩蝕刻 該第二中間介電層147，形成通孔15〇及170。在此，若發 生誤校準而形成一通孔150’，該蝕刻阻擋146防止該第一中 間介電層136P被蝕刻。 接著在該通孔150及170形成一金屬層及將之圖型化，因 此完成該位元線160及該共源極線18〇。 圖1 4及1 5説明製造本發明之快閃記憶體裝置之另一方 法。 如圖1 4所示，該第二實施例和該第一實施例不同處爲於 孩通孔150及170沉澱一金屬層，然後由回蝕或化學機械拋 光平面化，形成中間插頭155及175。在此，此平面化將_ 單元陣列區域及一外部電路區域（未顯示）間之步驟差減到 最小，並將該第二中間介電層147平面化。 接著如圖1 5所示，以傳統方式形成和該中間插頭155及 175相連之該位元線16〇及該共源極線18〇。 如上述，在本發明之快閃記憶體裝置中相鄰單元之源極 區由低阻抗金屬材質之一源極墊線連接。因該源極墊線由 較傳統源極擴散層阻撓低之金屬形成，則可較該源極擴散 層連接更多單7L足源極區。因此，該共源極線之間隔可增 至每3 2位元線或更多一個，因此降低該單元陣列區之她 減。 〜 -15 本紙張尺度適用中國國家標準x 297公爱 請 先 閱 讀 背 面 之 注 意 事 項 歲知· ί裝 頁i 訂 經濟部智慧財產局員工消費合作社印製 497257 A7 B7 五、發明說明（ 另因本發明之源極墊線在和疊閘自 且⑺目仃权準 < 接觸孔形 成，故無需傳統技術之場氧化層蝕刻處理，可根本防止該 作用區之蝕刻損傷及改良裝置特性。 另因孩位元線接觸之自行校準，可將該字元線及位元線 接觸間之距離最小化，則降低單元陣列區之大小。 依照本發明之製造方法，亦使用一形成該位元線接觸孔 及該源極墊線接觸孔之光罩型做爲一離子注入光罩，將該 製程簡化。 (請先閱讀背面之注意事項再填寫本頁) · ϋ m ·ϋ I ·ϋ n Αϋ I n n n —ϋ ϋ ϋ t^i 經濟部智慧財產局員工消費合作社印制农 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）It indicates the common source line type, and the reference number 190 indicates the line contact hole type. ^ Printed by Yibuyizi 7L Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 5 疋 Sectional view along line v-ν ′ in Figure 3. The arrangement according to the present invention will be described with reference to Figs. 3, 4 and 5. The flash memory device according to the present invention may include two ::; = devices. The flash memory device may include a plurality of plutonium action regions 105, and may be divided by a plurality of :: two. The definition of the marginal area 102 and the absolute and extended area 105 on a semiconductor substrate 100 9-this paper rule + CNS A4 specification (210 X 297 public ^ 7) 5. Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative's printed invention description (7) 7 has ^ (XX y) suitable gates including multiple (χ χ y) floating gates and multiple (y) control gates 120. The floating gates 11〇 在Some wounds of the active area and the insulating area are formed. The control gate 12 is used as a word line and extends through the active region 105. A unit cell is defined in an area where the active region 105 and a control gate 120 cross. The floating gate 1 is formed of polysilicon and the control gate 120 can be formed of a single layer of polysilicon or a multilayer of a polysilicon layer 120A and a silicide layer 12B. 110 is isolated by an interposed permeable oxide ισ6 and the active area of the semiconductor substrate 100. The control gate 120 is interposed by an insulating layer 115 such as a metal oxide material or an oxide having a high dielectric constant I and an oxide and The nitride (ON) stack insulation layer is isolated from the floating gate 110. For example, the doped regions of the source region 135 and the drain region 132 are in the stack. An active region 105 between the gates Π0 and 120 is formed. A first intermediate dielectric layer type 136ρ is deposited on the stacked gate η0 & 120. The source region 135 and the drain region 132 are respectively formed by first contact holes 145 and The second contact hole 140 is exposed. The first contact hole 145 is a source pad line contact hole, and is formed in parallel with the word line 120 between the gates, so that the source region 135 and the source electrode 135 are adjacent to each other. The insulating region 102 is exposed in the direction of the word line 120. The second contact hole 140 is a drain contact hole, and the drain regions 132 between the stacks are exposed. At this time, the first and second options are selected. The formation of the contact holes 145 and 140 is preferably self-aligned with the stacked gate sidewall and a nitride layer 122 above it. The source pad edge 145 that connects the source regions of adjacent cells in the word line direction And the bit line plug 140 'are formed in the first contact hole 145 and the second contact hole 140, respectively. The source coil line 145' and the bit line plug 140 'are preferably formed of resistance -10- Applicable to China National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back first) 497257 A7 V. Description of the invention ( A metal such as tungsten, aluminum, or copper is formed below the source line diffusion layer (41 of FIG. 1). The source pad lines 145, which are parallel to the character line 120, pass through a second intermediate dielectric. A layer 147 is formed to connect the source pad line 145, the exposed through hole, and the common source line 180. The common source line 180 and the active region ιo2 are parallel. The bit line plugs 140, A second intermediate dielectric layer 147 is formed to connect the bit line plug 140, the exposed through hole 150, and the bit line 160. The bit line 160 is parallel to the active area 105 which is perpendicular to the word line 120. An etch stopper 146 is preferably deposited on the source pad line 145 ', the bit line plug 140, and the first intermediate dielectric layer type 136P. This is to prevent the first intermediate dielectric layer type 136P from being damaged during the formation of the through-holes 150 and 170. As described above, the source regions of adjacent cell cells are connected to the source pads of a low-impedance metal material. Since the source pad line is formed of a metal having a lower impedance than the conventional source line diffusion layer (Fig. 41), it can connect more source regions than the conventional source diffusion layer. Therefore, unlike the conventional technique, it is necessary to provide a common source line every 16 to 32 bit lines, and the present invention only needs to provide the common source line every 32 or more bit lines. Therefore, the cell array region can be reduced by reducing the number of common source lines 180 in a cell array region. In addition, in order to form the conventional source line diffusion layer (4 丨 in FIG. 2), the field oxide layer 102 must be etched, which may damage the active region and reduce the charge retention ability. In the present invention, since the source pad line 145 is formed in the self-calibrating contact hole and self-aligned with the stack gate, the problem of over-etching of the active region forming the source region is fundamentally avoided, and thus the device characteristics are improved. 11 This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love (please read the precautions on the back before filling out this page). -------- Order -------- -· Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 497257 A7 B7 V. Description of the invention () ——J ------- ·! (Please read the precautions on the back before filling this page) In addition, because The bit line contact is self-calibrated, so there is no need to maintain the distance between the word line 120 and the contact hole 140 (L in the conventional technology), so the integration is improved. The following describes one of the manufacturing methods according to the present invention with reference to FIGS. 6 to 1. A method of a cell array region of a flash memory device. Referring to FIG. 6, an insulating region 102 is formed on a semiconductor substrate 100 to define an active region. Then a penetrating oxide 106 and a floating gate are formed. 10, an insulating layer 115, a control gate 120, and an etch stopper layer 122 are formed in the active region to form a stacked gate. The gate control gate 120 may be formed of a single layer of polymerized silicon, but is preferably formed of a single layer of polymerized silicon. A polysilicon layer 120A and a silicide layer 120B are formed in multiple layers to reduce the impedance of the control gate 120. The etch The stopper 122A prevents the stack gate from being exposed in the subsequent step of forming a self-aligned contact hole. Therefore, the etch stopper layer 122A is preferably formed of a metal having a lower etching rate than the first intermediate dielectric layer (136 in FIG. 9), such as An oxide layer. For example, the etch stopper layer 122A may be a nitride layer, a double layer formed of a nitride layer and an oxide layer, or a nitrogen oxide compound layer, and the thickness thereof is 2000 ~ 4. 〇. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in FIGS. 7 and 8, a drain region 132 and a source region 135 are formed in the active region of a semiconductor substrate 100. First, as shown in FIG. 7, A first photomask type 13 is exposed on the active region between the gates and formed on the semiconductor substrate 100, and then doped ions iii are implanted to form the drain region 132. Then, as shown in FIG. 8, An etch stopper spacer is formed on the side wall of the stack gate, so an etch stopper 122 is completed. Like the etch stopper layer 122A, the etch stopper spacer prevents the stacker gate from subsequently forming a self-aligning contact hole-12- This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 publicly loved 497257 The Intellectual Property Bureau of the Ministry of Economic Affairs ’employee consumer cooperative printed A7 B7 10 i. The steps of the invention description were exposed. Therefore, the etch stopper spacer is preferably formed by the etch resistance formed on the top of the stack gate. Sublayer 122A is formed of the same material, that is, a material with a lower etch rate than the first intermediate dielectric layer (136 of FIG. 9). For example, a double layer of a nitride layer, a nitride layer, and an oxide layer, Or a nitrogen oxide compound layer is sunk to a thickness of 500 ~ 1000 A, and then etched back to form the spacer. After the money-engraved stopper 122 is completed, one of the first mask types is exposed to the action area of the stack. 133 is formed, and then the doped ions 134 are ion-implanted, thereby forming the source region 135. In this embodiment, the ion implantation forming the drain region 132 is performed before the spacer constituting the etch stopper 122 is formed, and the ion implantation forming the source region 135 is performed after the spacer is formed. However, according to the structure of the source and drain regions, the spacer, the formation of the drain region and the source region can be changed. Then, as shown in FIG. 9, the first intermediate dielectric layer 136 is formed on the etch stopper 12 ' The first intermediate dielectric layer 13 is formed by depositing a high-temperature oxide and a BPSG layer to a thickness of 500 to 1000 A and 4000 to 6000, respectively, and then circulating it again in a temperature range of 850 to 900 ° C for 10 to 20 minutes. And formed. A third mask type 137 defining a bit line contact portion and a source contact portion of the cell array is formed on the first intermediate dielectric layer 136. Referring to FIG. 10, the third mask type 137 is used as an etching mask to anisotropically etch the first intermediate dielectric layer 136, so a bit line contact hole 140 and a source pad line contact hole are formed. 145, and a first intermediate dielectric layer type 136P is left on the top of the stack gate. As a self-aligning contact process is allowed to be performed by the stack gate and the etching stopper 122 around the stack gate, the bit line -13- this paper scale home standard (CNS) A4 specification (210 X 297 mm) --- r ------------------ Order · -------- (Please read the precautions on the back before filling this page) 497257 A7 B7 V. DESCRIPTION OF THE INVENTION (H) The contact hole 140 and the source pad line contact hole 145 may be formed by a reduced design criterion. Therefore, the size of the cell array can be reduced. Next, the third photomask type 137 is used as an ion implantation in the area of the remote element line contact hole 140 and the source / line contact hole 45 exposure area with 5X10i3 ~ 1X1015 ions / cm2. Photomask that performs an ion-implantation of arsenic or phosphorus plugs. When the bit line contact hole 14 and the source pad line contact hole 145 are misaligned and deviate from the drain and source regions 132 and 135, the plug-ion- > Wang Ruyou uses the source and drain The doped region of the electrode region appropriately covers the bit line contact and the source pad line contact to reduce the contact resistance. In the present invention, since the salt bit line contact hole i40 and the source line contact hole 145 are formed by the self-alignment contact processing, the formation of the contact holes 1440 and 145 and the ion implantation can be performed by using a single photomask. Type 137 is executed. Therefore, the processing is simpler than the conventional processing. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Referring to FIG. 11, after removing the third mask type 137, a metal layer is deposited to fill the bit line contact hole 140 and the source line contact hole 45. Then, the metal layer between the bit line contact hole 14 and the source line contact hole 145 is removed by etch back or chemical mechanical polishing to form a bit line plug 14 and a source pad line 145 '. . Therefore, the bit line plugs 40 and the source pad lines 45 have the same height, and the top surfaces of the bit lines are the same height. The metal layer is preferably formed of a low-resistance metal such as, aluminum, or copper. Because the source regions of adjacent cells use this method to form the source pad line 145, and the connection can reduce the source impedance. Because there are fewer common source lines in the cell array region, the size of the cell array region can be reduced. Referring to FIG. 12, the entire structure obtained in FIG. 11 is continuously formed on the entire surface of the structure. --------- 14 -_ This paper size applies the Zhongguanjia Standard (CNS) M specification (21QX297 mm) '' -^ 7257 A7 B7 V. Description of the invention (12 Etch stop 146 and a second intermediate dielectric layer 147. Then a fourth photomask type 149 is formed to define the bit line plug 140, and the source pad line 145, Referring to FIG. 13, the second intermediate dielectric layer 147 is etched by using the fourth mask type 149 as an etching mask to form through holes 15 and 170. Here, if misalignment occurs, A through hole 150 'is formed, and the etch stopper 146 prevents the first intermediate dielectric layer 136P from being etched. Then, a metal layer is formed and patterned in the through holes 150 and 170, so the bit line 160 and the The common source line is 180. Figures 14 and 15 illustrate another method of manufacturing the flash memory device of the present invention. As shown in Figure 14, the second embodiment differs from the first embodiment in that A metal layer is deposited on the through holes 150 and 170, and then planarized by etchback or chemical mechanical polishing to form intermediate plugs 155 and 175. Here This planarization minimizes the step difference between the _ cell array region and an external circuit region (not shown), and planarizes the second intermediate dielectric layer 147. Next, as shown in FIG. 15, it is formed in a conventional manner. The bit line 160 and the common source line 18 connected to the intermediate plugs 155 and 175. As described above, the source regions of adjacent cells in the flash memory device of the present invention are made of a low-impedance metal material. A source pad line connection. Because the source pad line is formed of a metal with lower obstruction than a traditional source diffusion layer, more single 7L foot source regions can be connected than the source diffusion layer. Therefore, the common source The line interval can be increased to every 32 bit lines or more, so reduce the cell array area. ~ -15 This paper size is applicable to the Chinese national standard x 297 public love, please read the precautions on the back first · Tiling page i printed 497257 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description So no field oxide layer of traditional technology is needed The engraving process can fundamentally prevent the etching damage of the active area and improve the device characteristics. In addition, due to the self-alignment of the bit line contact, the distance between the word line and bit line contact can be minimized, and the cell array area is reduced According to the manufacturing method of the present invention, a mask type forming the bit line contact hole and the source pad line contact hole is also used as an ion implantation mask to simplify the process. (Please read the note on the back first Please fill in this page for further information) · ϋ m · ϋ I · ϋ n Αϋ I nnn —ϋ ϋ ϋ t ^ i Printed agricultural paper sizes for employees ’cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs apply Chinese National Standard (CNS) A4 specifications (210 X 297 mm)