TW495673B - Method and apparatus for transmitting registered data onto PCI bus - Google Patents

Abstract

The present invention provides a method and apparatus for transmitting registered data onto PCI bus. The inventive apparatus and method can reduce the delay time of the output signal, and without greatly increasing the circuit complexity. The apparatus uses a 2R1W data buffer to advance one pulse cycle of the actual AD action for one PCI bus to send out the current phase data and the next phase data, and uses the multiplexer to select the current phase data and the next phase data based on the selection signal. The selection signal is the result by the OR operation for the IRDY# signal and the TRDY# signal. The apparatus uses the flip-flop to drive the output signal from the multiplexer to the PCI bus during the actual AD operation period. Thus, the inventive apparatus cannot only reduce the delay time for the output signal, but also be easy to implement.

Description

4W673

[Field of the Invention] The invention and method of reducing data are related to a method and a device for transmitting data, especially a device and a method for transmitting and temporarily storing data to a PCI bus without delaying the transmission of a signal without greatly increasing circuit complexity. [Learning technology]

Question systems usually use one or more peripheral buses to connect various devices. The connection between these agents is generally based on flow 2 A, or 仃. One of the agreements is to connect peripheral components (Pc 1) to each other = wide i. When the pulse frequency is 66MHZ, 266 Mbps of data communication is allowed. Basically, many devices will be connected to the Pc I bus at the same time. ^ When the bus action (bUS tranSaCti0n) is / to other receivers, the data transfer is performed. The requesting end is called " the master, and the receiving end is called " the controlled end ". When the master terminal outputs the address / command to the controlled = ί times, the command of the master terminal is " write ", the master terminal then outputs the shell; 'At the same time the controlled terminal decodes the address / command and Receive data; if the command of the master and the terminal is "read ,, action, the controlled terminal sends back the data. Therefore,

The sorting action includes an address phase and one or more data phases thereafter. ^ PCI data transmission is controlled by three signals: FRAME #, IRDY # and TRDY #. The frame # signal is driven by the master to indicate the transfer action. ^ Start and end. The IRDY # signal is also driven by the master, thereby notifying the controlled end of the message that the master is ready to send data. The TRDY # signal is driven by the controlled end ’to inform the master of the message that the controlled end is ready to send data.

495673 V. Description of invention (2). If both the FRAME # and IRDY # signals are disabled, the interface is in an idle state. When the FRAME # signal is enabled, it is regarded as the address phase, and the address / bus command code is sent out at the edge of the first pulse. When both IRDY # and TRDY # are enabled, data is sent during the subsequent data phase. When the master ends the final data transmission, the FRAME # signal is disabled. After the controlled terminal completes the final data transmission, the TRDY # signal is also disabled and the interface returns to the idle state. Figure 1 shows the functional block diagram of the conventional master control output connected to the PC I bus. There are more than 47 pins defined in the specifications of the PC I bus, but only AD [31: 〇] 101 is shown in this figure. The current phase data indicator 105, the current phase address indicator 1 06, and the address phase selection #No. 1 7 are internal status signals of the device. The current phase data index 丨 05 and the current phase address index 106 are indexes controlled by the output action, so that the data and addresses stored in the buffers 113 and 112 are changed respectively. The address S phase selection signal 1 0 7 is used to select the address phase or data phase. The multiplexer J and the I / O buffer 110 are used to drive signals to the PCI bus. The data buffer and address buffer can be implemented in any form. FIG. 2 is a timing diagram describing the operation of the conventional master terminal in FIG. 1. The upper part of the figure shows the waveform of the internal signal of the master terminal 'and the lower part shows the waveform of the output signal driven by the master to the PCI bus. In the third pulse period, the master uses the multiplexer 111 to select the address a output from the address buffer 112 according to the address phase selection signal 107, and passes the multiplexer "I and After the delay D2 of the I / O buffer 110, the address \ is driven to the PCI bus. At the next pulse period, the address phase selection signal 107 is disabled,

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= The master uses the multiplexer 11 1 to select the data Dj output from the data buffer 11 3 according to the address phase selection signal i 〇7, and passes through the multiplexer i J and I / O buffer | §11〇 Delay]) after 3, will the data]) factory drive to? (: 1 bus. Because no data conversion occurs in the sixth pulse period, Dj is continuously driven to the PCI bus. After the sixth pulse period, both trdy # signals are enabled at the same time. The current phase data index is 105. The exponent] will change to. In addition, the output delay is caused by the multiplexer lu and the 1/0 buffer 11 (), and the lean phase change from Dj to Dj + 1 also causes some delay. In addition, as shown in Figure 1 The master driving the AD signal to the PCI bus = 之 will include a large amount of delay, such as M and 〇2. This delay will reduce the control ^ receive the same-PC 1 bus signal available time. When the timing cycle = : Yuetu 2 for a short time will make it difficult for the controlled end to effectively process the signal. For example =, when the s clock frequency is 66MHz and the timing period is 15ns, the controlled will not be able to process the signal within this short or even shorter timing period ^ In order to solve the above-mentioned delay problem, FIG. 3 reveals other circuits having two layers of pipelines. The functional block diagram shown in Figure 3 describes the output control logic of the Xi T 2 device. In this circuit structure, the output signal is temporarily stored before the 5 ′ of the transmission row, and the signal is transmitted = data ββ A 1 material buffer 310 to prepare data one cycle in advance. Obviously, the circuit must use other materials The output is stored in the initial two-digit shellfish before the PC 1 bus. As shown in Fig. 3 ', this circuit uses two multiplexers 3 ι and samples ψ & six flip-flops 3 1 3 and 31 4 to maintain the initial value data until the data transmission is successful. However, the circuit of Figure 3 is quite complex. Begging

495673 V. Description of the invention (4) [Summary of the invention] The object of the present invention is to provide a device and method for transmitting temporarily stored data to a pcz bus that can reduce the delay time of the output signal without greatly increasing the complexity of the circuit. According to the present invention, the device 'packet-data buffer' for transmitting temporarily stored data to the PCI bus is used to store a plurality of temporarily stored data, and outputs the targets respectively according to the phase data index and the next phase data index of the target. The lease number L and the next data signal; an address buffer to store the address, and output the current address according to the current phase address index 丨 a first multiplexer 'is the current data signal and The bits t and Sheng of the address buffer output the current data signal or address according to the address phase selection signal; it = the second system receives the 1RDY # signal and the TRDY # signal from the PI bus, = the selection signal is changed;- The second multiplexer receives the data buffer ^ ΐ t 仏 and the signal output by the first multiplexer, and outputs the next data signal or the output signal pulse of the first multiplexer according to the information: ii. It receives the rotation of the second multiplexer and drives it to the PCI bus according to the signal of the reference rotation of the second multiplexer. Next step: A method for transmitting the temporarily stored data to the PCI bus, including the step (a \ address rotation), and the address buffer outputs a one-bit signal to the Wo-multiplexer; Step S2: 'Data buffer 11 outputs the current breeding signal of the current resource Γ to the first multiplexer and a second multiplexer respectively. 5. Description of the invention (5) is selected as the second selection step. Based on the aforementioned first multiplexer—revenge ^ »^ turns out the aforementioned current data signal or the aforementioned address signal;

Send the selection as the selection step, and the aforementioned second multiplexer will use the vacancy of U %% L to rotate the next data signal or the first multiplexed 3§ acknowledgment; and the working state Turn out

In the Te ^ driving step, a flip-flop sends the needle, +-"signal to the PCI bus according to the working pulse. Not to mention the first, by using a combination of the 10Υ # signal and the TRDYMf number, a material buffer is provided. The output current data and the next-data: the address or data is sent to the flip-flop at the first cycle. The most working pulse is sent to send the data or address to the PCI, and then the Beco or address will only be affected by the flip-flop. Delay. Therefore, [Embodiment] The following describes in detail the device and method for transmitting temporarily stored data PCI bus of the present invention with reference to the drawings, so as to reduce the delay time of the operation sending signal without greatly increasing the complexity of the circuit. " Fangdikou 4 display / Taiben Λming function applied to the output control logic of the main control terminal, picture. In the present example, the main control terminal 40 0 includes one of storing a plurality of data: a shellfish buffer 410, which stores a plurality of bits. The 2flw data buffer 410 is based on the current phase data index 407 and the bottom-phase: the shell material index 406 respectively rotates the current data 404 and the next data. The address data buffer 411 is based on the current phase bit: 412 丨 P address 40%. The main control terminal 400 further includes a first multiplexing mode 412 and a second multiplexer 413, basin,, and so on, so as to select the current data.

495673

5. Description of the invention (6) 404, next data 403 or current address 405. The first multiplexer 412 is connected to the 2R1W data buffer 410 and the 1R1W address buffer 411, and selects the current data 404 or the current address 405 according to the address phase selection signal 409. At the same time, 'the second multiplexer 413 is connected to the 2R1W data buffer and the first multiplexer 412' and selects the next data 403 or the first multiplexer 412 according to the data transmission selection signal 4qi enabled by the OR gate 415. The output signal Γ or gate 415 receives the IRDY ## ^ 421 and TRDY # signals 422 and performs an OR (qr) operation. The main control terminal 400 uses a flip-flop 414 to output the second multiplexer 413.

The Pre-AD signal is driven to the PCI bus. The flip-flop 414 is composed of pulses 424

The upper edge of the trigger. The main difference between the main control terminal of the present invention and the conventional main control terminal is (as shown in the figure) using a 2R1W data buffer 410. The data buffer 410 outputs data 404 and next data 403 according to the current phase data index 407 and the next phase data index 406, respectively.

^ The operation of the multiplexer 412 is similar to that of the multiplexer U1 shown in FIG. 1, except that the J pulse period (the cycle of the actual ad operation at the PC I bus) is raised to trigger the inverter 414 to clear the temporarily output. signal. After the data is transmitted by the PCI bus y, the multiplexer 413 is used to select the data—data 403; No: the 413 selects the data output by the multiplexer 412, so that it can be transmitted on the 1 ^ 1 sink! ϊ ί The control switch of the multiplexer 413 with the same data is 422 as the number 401, that is, after the 1RDY # signal 421 * TRDY "f ^, the information is input into the OR logic 415 When there is a data successfully, the host selects the item L f1 " 410 to output the data. Otherwise, the rural worker 413 # 'selects the item of the current data outline pointed by the phase data index 407, and fortunately

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5. Description of the invention (7) Pre-AD signal 4 02 is produced. The flip-flop 414 and the I / O buffer 416 are used to temporarily store output signals in the present invention. Because the node of the output flip-flop 414 is only connected to the I / O buffer 416, the advantage of the present invention is that the AD signal output from the flip-flop 414 can be directly sent to the buffer "" "Bus. Figure 5 is a timing diagram of the operation of the circuit of Figure 4. The waveform also includes the PC I write action of the preferred embodiment of the present invention. Similar to the configuration of Figure 2, the upper part of this figure shows the internal of the master. The waveform of the signal, and the lower half shows the waveform of the output signal output from the master to the P CI bus. It should be noted that the internal signal of the present invention outputs data to the flip-flops 4 丨 1 in advance, that is, One cycle is faster than the actual AD action on the PC I bus. In this embodiment, when the address phase selection signal 4 09 is 1, the multiplexer 41 2 outputs the address data, and when the data transmission selection signal 4 0 When 1 is 0, the multiplexer 413 outputs the next data. The following describes the operation of each signal in each cycle, but the description of the first cycle is omitted. In the second pulse cycle, the address phase selection signal 4 0 9 is 1. And the address buffer 411 outputs the address person ", and the data transmission option The signal 4〇1 is 1. Therefore, the multiplexer 412 outputs the address A ′ to the multiplexer 413 according to the address phase selection signal 409, and at the same time, the multiplexer 413 outputs the address A to the positive signal according to the data transmission selection signal 4 01. Inverter 414. Therefore, in this period, the pre-AD signal 402 is the address A ;.

J In the third pulse period, the address phase selection signal 4 0 9 is 0 and the data transmission selection signal 4 0 1 is 1, and the current data is 1 at the same time. The multiplexer 41 2 outputs the current data h to the multiplexer 41 3 according to the address phase selection signal 4 〇 9, and at the same time the multiplexer 413 outputs the current data Dj according to the data transmission selection signal 401.

Page 10 V. Description of the invention (8) To positive and negative = 414. Therefore, in this period, the pre_A]) signal is h before 402, and the AD signal is the address Aj. Month J * The chip is in the fourth pulse period, the address phase selection signal 409 is G, and the data selection signal 401 is 1, and the current data is Dj. The multiplexer 412 selects the phase selection signal 4 () 9 to output the current data. The multiplexer 413 transmits the selection signal 40 / to the current data according to the data. Input: to flip-flop 414. So in this period ... D signal 4.2 is the current i 枓 Dj, and AD signal is the current data Dj. In the fifth cycle, the 'address phase selection signal 409 is 0, and since both the m-number 421 and the TRDY # signal 422 are 0, it is 0' and the next data is'. The multi-monitor 413 selects the transmission according to the data = signal 4Q1 outputs the data-data core to the flip-flop ⑴. Therefore, in this week, the data D. P / e_AM5 谠 4〇2 is the next data Dj + 1, and the 〇 signal is the current, remote ii six-period 'address phase selection signal is 〇 and data transmission == No. 401 Is 0, meanwhile the data is ^ 2. The multi-jade 413 transmits the next data Dj + 2 to the flip-flop 414 according to the data, and transmits the selection signal 401. Therefore = this, during the period, the Pre_AD signal 402 is the next data d, and the M signal is the next data Dj + 1. At the seventh cycle, the AD signal is a data frame. Therefore, it can be clearly seen from FIG. 5 that the delay time of the master control terminal ^ & FIG. 6 shows a functional block diagram of the output control logic applied to the controlled terminal according to the present invention. As shown in the figure, the structure of the controlled terminal is similar to that of the master, except that it does not have an address signal control circuit. Therefore, the data transmission of Figure 6 495673 V. Description of the invention (9)

The circuit of the sending mechanism is similar to the circuit of FIG. 4. It should be noted that when the master sends the read command, the controlled end drives the corresponding data to the PCI bus ^, so the transmitting end can be the master or the controlled end. The present invention can also be applied to controllers having the same bus protocol. FIG. 7 is a timing diagram of the operation of the circuit of FIG. 6. This timing diagram is about the situation where the master sends a read instruction to the slave. In the fourth pulse period, when the control terminal drives the address or command on the PCI bus, the control terminal 600 decodes the address or command. When the controlled end 600 confirms the "read" command, it will start to prepare the data after the fourth pulse period. The operation of each period will be described separately below. ^ During the fourth pulse period, the data transmission selection signal 6 0 1 is 1, and the data is Dj, and the next data is Dj + 1. Therefore, the multiplexer 6 丨} outputs the current data Dj to the flip-flop 612 according to the data transmission selection signal 601. Therefore, in this cycle, The Pre-AD signal 602 is the current data Dj, and the ... signal is not required. A time at the fifth pulse period, the data transmission selection signal 6 0 1 is 0, and the purpose is: Dj is the shell material, and Dj + 1 is the next data. Therefore, the multiplexer 611 outputs the next data according to the data selection signal 601]) j + i to the flip-flop 612. Therefore, in the cycle, the Pre-AD signal 602 is the next data, and ad When the signal is the data / sixth pulse period, the master sets IRDY # 621 to enable, data) 迗 The selection signal 601 is 1, and the current data is, the next data is material D. Therefore, the multiplexer 611 selects according to the data transmission The signal 601 outputs the current and / m to the flip-flop 612. Therefore, in this period, the pre-AD signal

V. Description of the invention (10) 602 is the current information ^, and the AD signal is the information suppression. In the seventh pulse period, the main batch 嫂 θ data transmission is selected as = ni \ n without setting IR_21 to enable, AD. L tiger 6〇1 is 0, and the current data is Dj + 1, the next data 1 i \ D ^ multiplexer 6U will send B〇2 \ T + according to the data transmission selection signal 601: ^ " ^ Α: V2; ^ ^ ^ ^ Pe-AD ^ 勹 卜贝 枓 Dj + 2, and the AD signal is data D. When the number is the iiC pulse period, the Pre_AD signal has no effect, and the 0-letter transmission delay 2 can be seen in FIG. 5 to FIG. 7 'The preferred embodiment of the present invention. The transfer delay times D2 and D3 shown in 2 are short. In addition, the circuit shown in the present invention is complicated. The example circuit will not be as shown in Figure 3, = i the reference embodiment of the present invention, which does not limit the scope of the present invention. Please cover the scope of the patent. Various deformations or changes.

Page 13 495673 Brief description of the diagram Figure 1 is a functional block diagram of the output control logic of the conventional master control terminal. FIG. 2 is a timing diagram describing the actual operation of the master control terminal of FIG. 1. Fig. 3 is a functional block diagram of another output control logic of the conventional master control terminal. Fig. 4 is a functional block diagram of the output control logic applied to the main control terminal according to the present invention. FIG. 5 is a timing diagram illustrating the actual operation of the circuit of FIG. 4. Fig. 6 is a functional block diagram of the output control logic applied to the controlled terminal according to the present invention. FIG. 7 is a timing diagram describing the actual operation of FIG. 6. FIG. [Pattern number] 400 ~ Master 401, 601 ~ Data transmission selection signal 402, 602 ~ Pre-AD signal 403, 603 ~ Next data 404, 604 ~ Current data 4 0 5 ~ Address 406, 6 0 6 ~ Next phase data index 4 0 7, 6 0 7 ~ Current phase data index 4 0 8 ~ Current phase address index 4 0 9 ~ Address phase selection signal 410, 610 ~ 2R1W data buffer 411 ~ 1R1W address buffer

Page 14 495673 Brief description of the diagram 4 1 2 、 41 3, 6 11 ~ Multiplexer 414, 612 ~ Flip-flop 41 5, 6 1 3 ~ OR Gate 416, 417 > 418, 614, 615, 616 ~ I / O buffers 420, 620 ~ AD [31: 0] 421, 621 ~ IRDY # signal 422, 622 ~ TRDY # signal 60 0 ~ controlled end

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Claims (1)

The scope of the patent application includes: 1. A device that transmits temporarily stored data to the PCI bus. The phase before the packet is used to store a plurality of temporarily stored data, and it is based on the target signal and the next 1:; J: phase data index. Output the current data indicators respectively: used to store the address, and based on the current phase address, the letter = is the aforementioned address of the aforementioned current data selection device that received the aforementioned data buffer, and is selected according to the address phase = output description The current data signal or the aforementioned address; No .: Receives the 1 signal with the bus and deletes the selected signal from the W switch; It is expected to be: the f 2 multiplexer, which receives the previous data of the aforementioned data buffer. The signal output by the first multiplexer is based on the information transmitted by the foregoing data—the data signal or the first multiplexer turns out a flip-flop, which receives the output of the second multiplexer and tests it based on The pulse drives the signal output from the second multiplexer to the PCI bus ^ 2. The device for transmitting temporarily stored materials to the PCI bus as described in item 1 of the scope of the patent application, further including: M-first I / O buffer 'is connected to the front Said flip-flop and drives the output signal of the front flip-flop to the aforementioned PCI bus; a second I / O buffer is connected to the aforementioned logic gate and transmits the aforementioned signal from the aforementioned PCI bus to the logic Gates; and 495673 6. Patent application scope-A third I / 0 buffer is connected to the logic gate and transmits the TRDY # signal from the PCI bus to the logic gate. 3. The device for transmitting temporarily stored data to the PC I bus as described in item 1 of the scope of the patent application, where the aforementioned logic gate is an OR gate. 4. The device for transmitting temporarily stored data to the PC I bus as described in item 2 of the scope of the patent application, where the aforementioned logic gate is an OR gate. 5. The device for transmitting temporarily stored data to the PC I bus as described in item 2 of the scope of the patent application, wherein the aforementioned data buffer has two read ports and one write port. 6. —A method for transmitting temporarily stored data to the PC I bus, including the following steps: Address output step, outputting a bit signal from an address buffer to a first multiplexer; data output step, from A data buffer outputs the current data signal and the next data signal to the first multiplexer and the second multiplexer, respectively; in a first selection step, the first multiplexer outputs the current information according to a bit phase selection signal A data signal or the aforementioned address signal; a second selection step in which the second multiplexer outputs the next data signal or a signal output by the first multiplexer according to a data transmission selection signal; and a driving step in which a The inverter sends the signal output from the second multiplexer to the PCI bus according to the working pulse. 7. The method of transmitting the temporarily stored data to the PC I bus as described in item 6 of the scope of the patent application, wherein the aforementioned data transmission selection signal is provided by Page 17 495673 6. Scope of patent application The result of OR operation between IRDY # signal and TRDY # signal. Page 18