TW494515B - Method for preparing test piece for transmission electron microscope - Google Patents

Abstract

The present invention discloses a method for preparing a test piece for a transmission electron microscope, which enables the use of a transmission electron microscope to analyze a test piece containing a photoresist layer. The method comprises using a conductor layer and a dielectric layer to protect the photoresist layer of a test piece of a transmission electron microscope so as to prevent the photoresist layer from slicing damage and ion bombardment. The conductor layer and the dielectric layer can block the photoresist layer from an oxygen-containing and a moist environment and avoid a shrinkage of the photoresist layer caused by such an environment. Furthermore, the preparation of the test piece for the transmission electron microscope does not need to use an organic solvent or water to clean the test piece.

Description

494515 V. Description of the invention (1) 5-1 Field of invention: Method-2 Background of the invention: η JSC. In the analysis of the body circuit, the Prof He Image is a very important analysis in accordance with. Especially when the line width dimension of the ultra-large integrated circuit is advanced to less than 0.2 micron (

Micron), cross-sectional images that can directly display the results of many processes have become the key to further process technology development and solve various causes.

The problematic basic electron microscope (SeanningEiW called Cr0SC〇Pe) may wish to be one of the most commonly used tools in the modern semiconductor industry, but the application of scanning electron microscopes in modern ultra-large integrated circuit process technology has been Faced with a bottleneck, this is because the maximum resolution of the sweep second is only about 12 Angstroms. In order to be able to: ‘= a very small feature of a semiconductor element, a transmission electron microscope: = an analysis tool, because the maximum resolution of a transmission electron microscope is 1.4 angstroms. In spite of this, the analysis of the transmission electron microscope is still available. All the requirements are 4. For example, when the test piece to be analyzed has light II, even the photoresist material on the test piece itself is observed. Formula 494515 V. Description of the invention (2) The sub-microscope analysis will encounter some problems. The problem comes from the difficulty in preparing the test piece. Due to the requirements of the transmission electron microscope analysis, the preparation process of the test piece usually includes at least cutting, grinding, The process of polishing and cleaning. The cutting process usually uses a focused ion beam (Focused I on Beam) to bombard the cutting test piece, which causes damage to the photoresist layer and destroys the characteristics to be observed. In addition, the cleaning process often uses organic materials such as acetone Solvent, while organic solvents will dissolve the photoresist layer and completely destroy the characteristics to be observed. Another problem of analyzing photoresist materials by transmission electron microscopy comes from the photoresist materials in the environment containing oxygen and moisture. Dimension change distortion phenomenon. The size change distortion of photoresist materials that have been exposed and developed to form a pattern will greatly reduce the development of process technology. This is because the precise size of the photoresist layer patterns used to form contact holes, vias, and gates is very important for the next generation of integrated circuit process technology. In addition, a transmission electron microscope Another problem that must be encountered when analyzing photoresist materials is that the direct electron beam bombardment (B 0mbardment) of the electron beam used for imaging to the photoresist material will cause the photoresist material to shrink and cause dimensional distortion during observation Therefore, it is very necessary to propose a novel method for preparing a transmission electron microscope test piece that can solve the above-mentioned problems, and the method of the present invention meets such a demand.

Page 5 494515 V. Description of the invention (3) 5-3 Purpose and summary of the invention: One object of the present invention is to provide a photoresist test piece that can be analyzed by a transmission electron microscope. Another object of the present invention is to propose a method for preparing a photoresist test piece for a transmission electron microscope. This method does not cause damage caused by cutting a test piece with a focused ion beam, and can avoid the problem of charge accumulation during observation. Yet another object of the present invention is to provide a transmission electron microscope photoresist test piece with precise size, and at the same time, can make the cross-sectional image of the photoresist test piece clear, and accurately measure a deep sub-micron semiconductor element The size of the photoresist layer becomes possible. To achieve the above object, the present invention utilizes a conductive layer and a dielectric layer to protect a photoresist layer of a transmission electron microscope test piece. Both the conductor layer and the dielectric layer are formed by physical vapor deposition at a temperature at which the photoresist layer remains stable. When the test piece is cut and observed with a transmission electron microscope, the size of the defined photoresist layer can still be maintained, so the cross-sectional image of the photoresist test piece can be clearly displayed and the size of the photoresist layer can be accurately measured. may. The foregoing brief description of the invention and the following detailed description are examples only and are not limiting. Other equivalent changes or modifications that do not depart from the spirit of the invention should be included in the patent scope of the invention.

Page 6 494515 V. Description of the invention (4) 5-4 The invention contains a complete application. The following illustrations are for the convenience of understanding the reference to a photoresist layer circle, but do not use the traditional form of dielectric layers or modern semiconductors. Coating) Detailed description of reference hole formation and transfer to light development: It must be noted that the process steps and structures described below do not include the manufacturing process. The present invention can be implemented by various integrated circuit process technologies. Only the process technologies required to understand the present invention are mentioned. The detailed description will be made according to the accompanying drawings of the present invention. Please note that the form of the drawings is not drawn to scale, and the dimensions are exaggerated for the present invention. As shown in the first figure, a substrate 100 is shown, and the substrate 100 has 102 on it. The substrate 100 can be a semiconductor substrate, for example, a silicon crystal must be a semiconductor substrate. The substrate 100 can also include at least one conductor layer, depending on the needs of the analysis. The photoresist layer 102 can be any photoresist material used in the bulk industry. In addition, the photoresist layer 10 can be formed as a photoresist layer. For example, spin coating (Spi n method 0 shown in Figure 2A), in order to obtain the The cross-sectional image of the photoresist layer, the pattern of a hole was blocked by the layer 102 to expose the substrate 100 by a traditional lithography process. Later, a hole was formed. Due to the standing wave effect, the hole's 494515 V. Description of the invention (5) The side wall actually shows the outline as shown in the second figure B. Such a side wall profile can only be a penetrating type with a resolution of about 1.4 Angstroms to about 1.8 Angstroms The electron microscope can clearly observe, especially when the diameter of the hole shown in the second figure B is less than 0.2 micrometers, the size of the recess of the sidewall profile is extremely small and difficult to distinguish. If accurate measurement is required in the second figure Obviously, the diameter of the hole shown must first be obtained with a clear sidewall profile image, so a clear sidewall profile image is very important. Referring to the third figure, a conductor layer 104 is formed between the photoresist layer 102 and the second The bottom of the hole shown in Figure A, and a dielectric layer 106 is then formed on the conductor layer Above 104. The conductor layer 104 can be a platinum layer, a gold layer, a copper layer, a shaw layer, and a titanium layer, and a rhyme layer is preferred. The reason why the ship was chosen is because Platinum is a stable or noble metal, and platinum can easily form a thin layer. The conductor layer 104 is preferably formed by a physical vapor deposition method, for example, a DCS pu 11 ering method and about 20 ° C to about 30 ° C. The temperature of this physical vapor deposition method must be maintained at an appropriate level, because the high temperature environment will shrink or change the shape of the photoresist material. In fact, not only the formation of the conductive layer 104 The temperature should not be too high, and the temperature during the entire preparation process of the transmission electron microscope test piece should not be too high to avoid causing the photoresist material to shrink or change its shape. The thickness of the conductive layer 1 0 4 is about 50 angstroms to about 2 Between 0 0 angstroms, and preferably about 100 angstroms. As shown in the third figure, the conductor layer 104 did not fill the hole because of the small size of the hole and the physical vapor deposition method. For reasons of limited step coverage. This is not important and does not affect the invention Effectiveness. 1 square conductor layer 4 and the dielectric layer 106 is used for

Page 8 494515 V. Description of the invention (6) Isolate the external humid environment and prevent the photoresist layer from oxidizing 102. In addition, the conductor layer 104 can also avoid the charge accumulation phenomenon, which is caused by the use of an electron beam or an ion beam. Furthermore, the conductive layer 104 is very helpful for clearly distinguishing the interface between the photoresist layer 102 and the dielectric layer 106. The dielectric layer 106 may be a dioxide layer or a nitride layer, and is preferably a dioxide layer. The dielectric layer 106 can be formed by a physical vapor deposition method, and a DC sputtering method is preferred. This sputtering method can be performed with an ion mill (Ion Miller) used in the preparation process of a conventional transmission electron microscope test piece. By accelerating the argon ion (Ar +) plasma, silicon dioxide or silicon nitride molecules are removed from a quartz glass target or a silicon nitride target. This sputtering method is performed at a pressure of about 10 to 6 torr and between about 20 ° C to about 30 ° C. The thickness of the dielectric layer 106 is between about 500 angstroms and about 1 micron, and preferably about 100 angstroms. The dielectric layer 106 is used to protect the photoresist layer 102, and to prevent the photoresist layer 102 from being destroyed during the preparation of the transmission electron microscope test piece, especially when using gallium ions (Ga + ) Focused ion beam (Focused Ion Beam) bombarded the cutting test piece. Since the thickness of the damage caused by the focused ion beam was found to be about 500 angstroms during the actual preparation of the test strip, the thickness of the dielectric layer 106 must exceed 500 angstroms. After the photoresist layer 102 is formed, a substrate 100 such as a silicon wafer is cut with a focused ion beam to form a transmission electron microscope test piece 200 shown in the fourth figure, and its size is 2 微米。 About 10 microns X about 5 microns X about 0.2 microns, wherein the length is about 10 microns, the width is about 5 microns, and the thickness is about 0.2 microns. In order to observe the test piece 200 with a transmission electron microscope, the test piece 200 was picked up by a static absorption method using a thin glass needle and placed on a copper mesh coated with a thin carbon film.

494515 V. Description of the invention (7), this thin glass needle has a tip of about 1 micron. The above-mentioned preparation process of the transmission electron microscope test piece is used to prepare a photoresist test piece having contact holes and interlayer holes therein. Nevertheless, the method for preparing test pieces of the present invention can also be used to prepare photoresist test pieces having other structures. For example, as shown in the fifth figure, the photoresist layer 102 is used to define a gate, and the substrate 100 can be a conductive layer, such as a polycrystalline silicon layer. In any of the embodiments of the present invention, the conductive layer 104 and the dielectric layer 106 can effectively protect the photoresist layer 10 and isolate the photoresist layer 1 02 from being exposed to moisture and oxygen. Environmental attack. In addition, the shrinkage of the photoresist layer 102 caused by the transmission electron microscope and focused ion beam bombardment can also be avoided. The conductor layer 104 is mainly used to avoid the charge accumulation phenomenon originating from the electron beam and focused ion beam of the transmission electron microscope. Since the test piece 200 is placed on a copper net coated with a thin carbon film for observation, the conductor layer 104 can also be omitted. The foregoing brief description of the invention and the following detailed description are examples only and are not limiting. Other equivalent changes or modifications that do not depart from the spirit of the invention should be included in the patent scope of the invention.

Page 494515 Brief description of the drawings The first diagram shows a cross-sectional view of a substrate having a photoresist layer thereon; the second diagram A shows a hole formed in the photoresist layer shown in the first diagram Figure 2B shows the cross-sectional profile of a hole formed by the standing wave effect; Figure 3 shows the result of the continuous formation of a conductive layer and a dielectric layer on the structure shown in Figure 2A; Figure 4 shows the A transmission electron microscope test piece produced by the test piece preparation method of the present invention; and the fifth figure shows a cross-sectional image of a photoresist layer defining a gate produced by the test piece preparation method of the present invention. Main symbols: 1 0 0 Substrate 102 Photoresist layer 104 Conductor layer 106 Dielectric layer 2 0 0 Test piece

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Claims (1)

494515 6. Application scope 1. A method for preparing a transmission electron microscope test strip, including at least the following steps: providing a substrate, the substrate including at least a photoresist layer; forming a dielectric layer on the substrate On; and cutting the substrate. 2. The method as described in item 1 of the scope of patent application, wherein the substrate mentioned above includes at least one Shi Xi wafer. 3. The method according to item 1 of the scope of patent application, wherein the substrate mentioned above comprises at least a conductor layer. 4. The method according to item 1 of the scope of patent application, wherein the substrate mentioned above comprises at least a dielectric layer. 5. The method according to item 1 of the scope of patent application, wherein the dielectric layer described above comprises at least a dioxide layer. 6. The method according to item 1 of the scope of patent application, wherein the dielectric layer includes at least one nitride layer. 7. The method according to item 1 of the scope of patent application, wherein the dielectric layer is formed by a physical vapor deposition method. Page 12 494515 6. Scope of patent application 8. The method described in item 1 of the scope of patent application, wherein the dielectric layer is formed between about 20 ° C and about 30 ° C. -9. The method according to item 1 of the scope of patent application, wherein said substrate is cut with a focused ion beam. 1 0. A method for preparing a transmission electron microscope test strip includes at least the following steps: providing a substrate, the substrate including at least a photoresist layer; forming a conductor layer on the substrate with a first Physical vapor deposition method; forming a dielectric layer on the conductor layer by a second physical vapor deposition method; and cutting the substrate. 11. The method according to item 10 of the scope of patent application, wherein the substrate mentioned above comprises at least one silicon wafer. 1 2. The method according to item 10 of the scope of patent application, wherein the substrate mentioned above comprises at least one conductor layer. Ο 1 3. The method according to item 10 of the patent application scope, wherein the substrate mentioned above comprises at least one dielectric layer. 14 4. The method as described in item 10 of the scope of patent application, wherein the above guide Page 13 494515 6. Scope of patent application The body layer contains at least one turning layer. 15. The method according to item 10 of the scope of patent application, wherein the conductor layer includes at least one copper layer. 16. The method as described in item 10 of the scope of patent application, wherein the conductor layer described above includes at least one gold layer. 1 7. The method as described in item 10 of the scope of patent application, wherein the conductor layer mentioned above comprises at least one layer. 18. The method according to item 10 of the scope of patent application, wherein the dielectric layer described above comprises at least a dioxide layer. 19. The method as described in item 10 of the scope of patent application, wherein the dielectric layer includes at least one nitride layer. 20. The method as described in item 10 of the scope of patent application, wherein the first physical vapor deposition method described above includes at least a coin plating method. 2 1. The method according to item 10 of the scope of patent application, wherein the second physical vapor deposition method includes at least a sputtering method. 2 2. The method described in item 10 of the scope of patent application, wherein the above Page 14 494515 6. Scope of patent application A physical vapor deposition method and the second physical vapor deposition method are performed between about 20 ° C and about 30 ° C. 2 3. The method as described in item 10 of the scope of patent application, wherein the substrate is cut with a focused ion beam. 2 4. A method for preparing a transmission electron microscope test strip, including at least the following steps: providing a substrate, the substrate including at least a photoresist layer; Φ forming a conductor layer on the substrate with a first A sputtering method; forming a dielectric layer on the conductor layer by a second sputtering method; and cutting the substrate. 25. The method according to item 24 of the scope of patent application, wherein the substrate mentioned above comprises at least one chip. 26. The method according to item 24 of the scope of patent application, wherein the substrate mentioned above includes at least one conductive layer. 27. The method according to item 24 of the scope of patent application, wherein the substrate mentioned above comprises at least one dielectric layer. 28. The method according to item 24 of the scope of patent application, wherein the conductive layer described above includes at least one turning layer. Page 15 494515 6. Scope of patent application 29. The method according to item 24 of the scope of patent application, wherein the conductor layer includes at least one copper layer. 30. The method according to item 24 of the scope of patent application, wherein the conductor layer described above comprises at least one gold layer. 3 1. The method according to item 24 of the scope of patent application, wherein the conductor layer mentioned above includes at least one inscription layer. 32. The method according to item 24 of the scope of patent application, wherein the dielectric layer described above comprises at least a dioxide layer. 33. The method according to item 24 of the scope of patent application, wherein the dielectric layer includes at least one silicon nitride layer. 34. The method according to item 24 of the scope of patent application, wherein the first sputtering method and the second sputtering method described above are performed between about 20 ° C and about 30 ° C. 35. The method according to item 24 of the scope of patent application, wherein the substrate is cut with a focused ion beam.