TW494506B - Manufacturing method of multi-tier substrate for ball grid array package structure - Google Patents

Abstract

A manufacturing method of multi-tier substrate for ball grid array (BGA) package structure contains the followings. (a) An inner layer circuit board is provided, in which the first conducting circuit is formed on its upper surface and several solder ball bonding-pads are formed on its lower surface. (b) The first dielectric layer is formed on the upper surface of the inner layer circuit board. (c) The first opening is formed on the first dielectric layer and is followed by forming several first via holes on the first dielectric layer so as to expose the first conducting circuit of the inner layer circuit board. (d) The second conducting circuit is formed on the first dielectric layer and the first conducting circuit that is exposed from the first via hole. (e) The second dielectric layer is formed on the first dielectric layer and the second conducting circuit by halftone printing such that the second dielectric layer is provided with the second opening, which is larger than the first opening of the first dielectric layer, and one part of the second conducting circuit is exposed. (f) Several second via holes are formed on the second dielectric layer to expose the second conducting circuit. (g) The third conducting circuit is formed on the second dielectric layer and the second conducting circuit that is exposed from the second via hole. (h) A solder block is formed on the layout surface of the multi-tier substrate so as to make the region on the conducting circuit, which is used for electrically connecting to a semiconductor chip, and the solder ball bonding-pad, which is used for electrically connecting to the external portion, expose from the solder block.

Description

494506 V. Description of the invention (1) [Field of the invention] The present invention relates to a method for manufacturing a ball grid array (bga), and more particularly, to a method for manufacturing a multi-tier substrate using a # V 体 封 封 structure k. method. ] (GA) 封 扃 结构 [Previous Technology] These issues have become more important as the wafer design orientation reduces transistor size. At present, the size of the positive film makes the chip unable to have fast system efficiency: the packaging of the industry is matched with each other. Basically 'a package or package supports the original source, and the performance of other functions such as heat dissipation, support and pairing: two = protection: and the other-the important function is to simply assign the secret from the chip' I / O to the printed circuit board I / O terminal. v. Considering the integration method of the chip, the ball grid array (BGA) package is roughly a cavity up (cavity up) and a cavity down (cavity doown ° a) knife. Please refer to Figure 1 for cavity direction The bottom ball grid array (bga) is fabricated, which includes a wafer 40 provided with a cavity 10 on a lower surface of a substrate 10, and a wafer pad (not shown in the figure) on the surface of the wafer 40 is connected by wires. '(bonding wires) are connected to chip bonding pads 22, 36 provided on the periphery of the substrate 10 cavity, and a plurality of solder ball pads 3 4 are located on the lower surface of the substrate 10 The periphery of the wafer connection pads 2 2, 3 and 6. The plurality of solder ball pads 34 are electrically connected to the opposite connection pads 22 and 36, respectively. Each solder ball pad 34 is provided with a solder ball 38. It is used to communicate with the outside world electrically. The chip 40, the connecting line and the cavity of the substrate 10 are a colloid coating (including a part of the lower surface of the substrate). ^

P01-074.ptd Page 5 494506 V. Description of the invention (2) Two = $ 'Use the structure where the substrate and the wafer are connected for the first-level connection. The chip f * is electrically connected. And * the external circuit The number of component connections (generally referred to as "input_〇utput" or :, 1 / 处 〇 " connection ") is determined by the structure of the chip, and it does the same thing. An advanced chip with many functions requires a certain number of "I / O" connections. However, since the wiring density (Uiring density) of the substrate 10 is limited by its recess 10a, it is possible to "I / O" connections There are not enough leads to provide electrical connection. As early as the second, the national patent No. 5,688,408 disclosed a cavityca package structure, #mainly contains a chip 50 which is carried in a multi-level (nulti-Uer) Substrate 60. U.S. Patent No. 5,688,408 also provides a method of manufacturing the substrate 60, which includes providing an inner core layer (eg, made of FR-4) 62, and attaching copper cymbals to its lower surface. After that, copper is formed into the desired conductive circuit. Next, the "electrical layer 64 (such as a prepreg) having conductive openings and conductive circuits 66 * _I formed of copper foil are staggered" It is arranged on the inner core layer 62 to form at least one pre-impregnated body between two adjacent conductive circuits. Two layers of copper foil are formed on the outer layer of the printed circuit board, and then etched. To form the desired conductive circuit 68. Finally 'add the stack Hot pressing to cure the resin material of the prepreg to obtain a laminate of the stack. The total number of layers of the prepreg and copper foil (including 4 copper layers above and below the inner core layer) And each copper foil layer etched into a critical circuit) depends on the need.-In general, electrical connections between different conductive circuit layers are made by drilling through holes in the laminate (thrugh_h〇 le) 70, and in Poll-〇74.ptd 494506 V. Description of the invention (3) The through hole is coated with a layer of conductive metal. However, the multi-layer (mu 11 i -1 ier) substrate For 60, through-holes and their pads are one of the main factors limiting the density of the line. Hole pads are usually about 0.2 mm larger than the hole diameter to compensate for drilling deviation (dri 1 1 misregistration), Expand expansion / shrinkage and photo tool expasion / shrinkage of the exposure equipment. In addition, the inner via pad in a multilayer structure is more difficult to control the positional relationship because it cannot be seen from the outside. The hole pad is about 0 · 5-0 · 8mm larger than the hole diameter. Therefore, the circuit design It is difficult to achieve true high density. [Summary of the Invention] Therefore, the main object of the present invention is to provide a multi-layer (mu 11 i -1 ier) substrate manufacturing method for a ball grid array (β GA) package structure, which can overcome Or at least the problems and disadvantages of the foregoing prior art are improved. According to the first preferred embodiment of the present invention, a method for manufacturing a multi-layer (mu 11 i -1 i er board) method includes: (a) providing an inner layer circuit board on which A first conductive circuit has been formed, and several solder ball pads have been formed on its lower surface; (b) a first dielectric layer has been formed on the surface of the inner layer circuit board;) a first opening has been formed in the first dielectric layer 'And forming a plurality of first via holes in the first dielectric layer and exposing a conductive circuit of a brother of the inner layer circuit board, (d) forming a second conductive circuit in the first dielectric layer And exposed on the first conductive circuit of the first dielectric hole; (e), the screen prints a second dielectric layer on the first dielectric layer and the second conductive circuit, so that a dielectric is far away; The layer has a second opening larger than the first dielectric ^

P〇lO74.ptd Page 7 494506

494506 V. Description of the invention (5) It is understood that the second conductive circuit and the third conductive body are formed by an additive method or a subtractive method. However, because the inner circuit board, the second conductive circuit, and the second series are electrically connected to each other using blind vias, the circuit layer, the second conductive circuit, and the third conductive circuit are electrically connected to each other. The interconnection does not need to be achieved through holes (through holes). Therefore, the wiring density of m = multi-layer substrate of Ming 'is no longer limited by the through-holes, and therefore, it can accommodate at least a large number of conductive circuits, thereby overcoming or at least technical problems and disadvantages. 』4Special techniques [Explanation of the invention] FIG. 3i shows a ball grid array (bg package structure) according to a preferred embodiment of the present invention. The ball grid array package structure mainly includes a multi-tier BGA substrate 100 is used to carry and electrically connect the half body chip 150. The multi-tier BGA substrate 100 mainly includes an inner substrate 100 and a first dielectric layer 11 disposed on the inner circuit 100 A first opening lu is provided thereon, a second conductive circuit 1023 is provided on the first dielectric layer 110, and a second dielectric layer 120 is provided on the first dielectric layer 110 and the second conductive circuit. There is a second opening 121 on the 102a, a second conductive circuit 102a provided on the second dielectric layer 120, and a solder mask 104 on the wiring surface on the multi-layer substrate. The inner layer is suspected. The substrate 100 has a first conductive circuit 101a and a wafer holder 101b provided on an upper surface thereof, and a plurality of solder ball pads 10lc provided on a lower surface thereof. The inner layer substrate has several conductive vias. A hole (Plated thrugh ughle) 13〇 is used to electrically connect the first conductive circuit 1 〇1 a and a plurality of solder ball pads 丨 〇 丨 c. The first guide

P01-074.ptd Page 9 ^ 4506 V. Description of the invention (6) 1 = The road 10a is partially exposed in the first opening 丨】 and forms a plurality of fingers 101d. The second conductive circuit 102 is partially exposed at the port 121 to form a plurality of second fingers 1021). The third conductive circuit is partially formed with a plurality of third fingers. The first conductive circuit 101 & the second conductive circuit 102 and the third circuit 103a of the inner layer circuit board are electrically connected to each other by using a blind via (bHnd νί〇), the first finger 101d, the second finger The finger 102b, the third finger 10, and = 101 (: are exposed on the solder mask m. The semiconductor wafer is electrically connected by a plurality of bonding wires such as gold wires " two fingers 1 〇18, the second finger 102b and the third finger 103b. The f-ball soldering system 10lc is provided with a solder ball 142 for electrical connection with the outside world. = Sheet ioib solder ball pad 1 〇4 solder ball pads 010 solder ball pads 10b, a to 3g figure discloses a method for manufacturing a mil ti-tier substrate according to a preferred embodiment of the present invention. Figure 3a reveals According to the present invention, the inner-layer circuit board ι0, 1 has formed the first conductive circuit 101 & and a wafer holder 101; upper = forming a plurality of solder ball pads 101c. The inner-layer substrate 10 There are several iii: ;;; ated thr〇Ugh V electrical circuit 10a and a plurality of solder ball pads 1011 ^ The internal sound 100 can be reinforced by glass fiber BT (bismaleimide_tFiaz) is a core layer made of FR-4 glass fiber reinforced epoxy resin (relnf0rced epoxy resin). This increases the mechanical strength of the inner circuit board. Figure 3b of the hunting reveals-the first introduction The electrical layer 11 is formed on the inner circuit board P P01-074.ptd Page 10 494506 V. Description of the invention (7) Surface. The first dielectric layer 1 has a first opening 1 and several A first via hole 1 12, wherein the first conductive circuit 10a is partially exposed on the first opening 1 1 1 to form a plurality of first fingers 丨 〇 丨 d. The first dielectric The layer 110 may be coated on the inner layer circuit board 100 by a conventional technique using a photodielectric medium (PID). Then, the photosensitive medium is formed by imaging and developing. The first opening lu and the first interlayer hole 112. In addition, the first dielectric layer can also be coated on the inner-layer circuit board 100 using a screen print and directly form the first dielectric layer. The opening 111 is formed by phase forming and developing the first dielectric layer. Interstitial hole 1 1 2. Furthermore, 'the first interstitial hole 丨 2 can also be formed by mechanical drilling or laser drilling force ^. Laser types suitable for this step include carbon dioxide laser I aluminum garnet (Yttrium aluminum garnet, YAG) laser, quasi-early early emperor 4 丄 / · Putian laser (excimer laser), etc. Among them, the use of dioxide = laser is preferred because of its high yield. 1 1 (Tα Figure ^ A second conductive circuit 102a is formed on the first dielectric drop 11ϋ and a tree is formed on the iridium kSr. The first conductive circuit 101 of the first interlayer hole 112 ^^ 2. The fine circuit 102a can be formed using a subtractive method (plating); Shidao :: electrolessly (including the first dielectric); the same dielectric layer on the surface of the first dielectric layer 110 ( After that, the conductive metal layer is preferably a copper layer. The conductive i: an etchant is on the conductive metal layer, and the selective etching is, the first: forming The second conductive circuit 102a. It can be understood that the electrical circuit 102a can also use an additive method.

P01-074.ptd Page 11 4V4!) 06

It = 1 咩 In detail, a plating mask is formed on the surface of the electric layer 1 10, and then a conductive metal is electrolessly plated to form the conductive circuit 102a. # 多 ”第 3d 图 ， The second dielectric layer 丨 2 〇 screen is printed on the first " electrical layer 0 and directly forms the second opening 丨 2 i, the second opening 12 is greater than A The first opening 11i thereby exposes the finger 102b of the second conductive circuit. Referring to FIG. 3e ', the second dielectric layer 120 is imaged and developed to form a plurality of via holes 122 and expose the second conductive circuit 102a. Figure 3f reveals that a third conductive circuit 103a is formed on the second dielectric layer 1/0 and the second conductive circuit 102 & exposed on the second via 122. The second conductive circuit can be formed using an additive or a subtractive method. Referring to FIG. 3g, a solder mask is formed on the wiring surface of the multi-layer substrate so that the second conductive circuit 102a and the third conductive circuit (in accordance with 3a for electrical connection to the semiconductor) The area of the chip 丨 5 〇 and the solder ball pads for electrical connection to the outside 丨 〇 c are exposed to the solder shield 1 / 4_ 'the third conductive circuit 1038 is exposed to the solder shield 104 Partly, it is the second finger 103b ', thereby making the multi-tier substrate 100. Figures 3h to 3i are used to illustrate the use of the multi-layer substrate of the present invention to manufacture a ball grid array (BGA) package structure. Please refer to Figure 3h to complete the multi-tier substrate.

P01-074.ptd Page 12

15〇 After using L, a piece of film 150 is pasted to the wafer holder 10lb, the wafer buckle 1 n 9k XZ is set with several Xue wires electrically connected to the first finger 1 0 1 d, the second hand Eight Ang two fingers 103b. Please refer to Tu Tu. Shi Gu Γ Figure 'Several solder balls 142 adhere to the solder ball pad 101c by ltu m 0¾ ^ [tth B, JL' κ I i .. Printed thorium 4-layer ball grid array The package structure is mounted on a substrate, such as a ^^. Board, and the solder balls 142 can be electrically connected to the package structure. The board is shown in Fig. 1 as a multi-level base according to another preferred embodiment of the present invention. The manufacturing method is as follows: (a) An inner layer circuit board 200 is provided, and a first conductive circuit 201 and a second conductive layer 201 have been formed on the upper surface 2fl / surface of the "inner layer circuit board 200." Hole 250; (b) forming a -first dielectric layer 210 on the upper surface of the inner-layer circuit board 200. :)) Two and two open 0211 and several first via holes (212) ^ 200 of the "first; 1 〇 first via hole 2 1 2 exposed the inner layer circuit board from two Λ circuit 2 〇1; U) formation-the second dielectric layer "0 on the lower surface of the second electrical plate 200; (e) forming a number of second dielectric hole (222) in the second dielectric layer 22, The second interlayer hole 222 exposes the second conductive circuit 202 of the inner layer circuit board 200 (" Plating first: genus: 203) On the inner layer circuit board, the upper surface (including the first opening and the ΓΓΛ hole) ) The second conductive metal layer 2 of ΛΛ power ore is on the lower surface of the inner circuit board 2: 0 (including the second via hole); (g) Selective etching = gold I: 2 ::: to form a third conductive circuit 〇3a and selective | etch the second conductive metal layer 204 to form a fourth conductive circuit 20 "; " stencil p-brush-third dielectric layer 230 on the first-dielectric layer 2i0 and Direct form

P〇l-074.ptd Page 13 494506 V. Description of the invention (10) A second opening 231 is formed, which is larger than the first opening 211 to expose a part of the third conductive circuit 203a; (I) forming a first dielectric layer 240 on the second dielectric layer 220; (j) forming a plurality of third via holes 232 in the third dielectric layer 230 and exposing the first dielectric layer 230 Two conductive circuits 20 3a and several fourth via holes (via h0ie) 242 are formed in the fifth dielectric layer 240 and the fourth conductive circuit is exposed; (k) the third conductive metal layer 205 Plated on all surface areas (including the first: layer holes and through holes); (1) selective etching of the third conductive metal to form-the fifth conductive circuit 2G5a,-the wafer holder 252 and the number: :: = 53; (m) forming a solder shield 2. 6 on the surface of the multi-level base wiring, so that the first conductive circuit 201, the third conductive circuit 203a and the fifth conductive circuit 205 & are used for electrical connection The area of 260 to the film and exposed to the zinc tin shade 2G6 for electrical connection 0x V body every day. The solder ball material 253 connected to the outer part 1 is naked. However, the present invention has been disclosed in the foregoing preferred embodiment. When various modifications can be made: Jing Qin Wei is subject to the definition of the scope of the attached patent. Mao Yue's Protection 494506

Figure 1 · Partial cross-sectional view of a conventional cavity down package (BGA) package structure; 1 Sectional view of a dry-line package structure Figure 2 · Conventional cavity up (cavity up chart, Figures 3a to Figure 3g: It is used to explain a multi-tier substrate manufacturing method according to a preferred embodiment of the present invention. Figures 3h to 3i are diagrams illustrating the use of the multi-layer substrate of the present invention. Manufacturing method of ball grid array (BGA) package structure; and Figure 4 · A cross-sectional view of a multi-tier substrate according to another preferred embodiment of the present invention. [Illustration of drawing number] 10 heat sink 20 sandwich circuit board 22 conductive circuit 24 opening 30 dielectric layer 32 via hole 34 solder ball pad 36 conductive circuit 38 solder ball 40 chip 50 chip 60 substrate 62 inner core layer 64 dielectric layer 66 conductive circuit 68 conductive circuit 70 through-hole 100 levels Type substrate 1 0 1 a first conductive circuit 101b wafer holder 101c solder ball pad 101d finger 102a second conductive circuit 102b finger 103a third conductive circuit 103b finger

494506

Brief description of the drawing 104 Solder masking 110 First dielectric layer 111 First opening V 112 First via hole 121 Second opening V 130 Through-hole 142 Solder ball 150 Chip 200 Inner circuit Plate 201 first conductive circuit 202 second conductive circuit 203 first conductive metal layer 2 0 3a third conductive circuit 204 second conductive metal layer 2 04a fourth conductive circuit 205 first conductive metal layer 2 0 5a fifth conductive circuit 21 0 First dielectric layer 211 First opening 212 First first via hole 220 Second dielectric layer 222 First-via hole 230 Third dielectric layer 231 First opening D 2 3 2 The third via hole 240 The fourth dielectric layer 242 The third via hole 2 5 0 through-hole 2 52 chip holder 2 5 3 solder ball pad 2 6 0 chip 2 62 tin Ball 2 0 6 solder mask

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Claims (1)

494506 VI. Application Patent Scope 1. A ball grid array, j includes: providing an inner circuit board to form a first dielectric layer to form a first opening in the via hole in the first conductive circuit; forming A method for manufacturing a multi-level substrate of a first conductive electrical package structure with a second conductive dielectric layer hole, which has a first conductive circuit formed on the upper surface of the inner layer circuit board surface; a first dielectric layer, and Forming a plurality of first dielectric layers and a first dielectric layer and exposing the inner layer circuit board on the first dielectric layer and exposing on the first road; the screen is printed on a second dielectric path so that the first The first openings of the two electrical layers are thereby electrically connected to a semiconductor to form a plurality of second dielectric layers to expose the second conductive circuit to form a third conductive dielectric layer. The second conductive electrical layer forms a tin to shield the conductive circuit A tin electrical layer for electrically and electrically connecting to the outside is provided on the first dielectric layer and the second conductive dielectric layer with a second opening larger than the first dielectric to expose a part of the second conductive circuit for Chip via hole) on the second dielectric layer, and ^ is on the second dielectric layer and exposed on the second road; and the wiring surface on the substrate, so that the ^ is connected to the area of the semiconductor wafer And I'zinc pad is exposed to the solder mask. 2 · According to item 1 of the scope of the patent application, the step 1 is used to achieve 1 plating-conductive metal layer, and the post = step is to selectively etch the conductive metal by the following and after P0i-074.ptd $ 17 pages 494506 6. Apply for a patent scope layer to form the conductive circuit enclosure = use a two-ball grid array package to construct a multi-level electrical metal to form the conductive atlng mask), and then conduct electricity mining-conductive 4. Manufacture according to the first scope of the patent scope Method, where the upper surface of the inner # 7 7 array package structure has multiple steps on it for carrying: = In addition-the chip holder is located at 5. according to the application § month patent scope! In the manufacturing method of the layer substrate, the multiple steps of the first conductive 7-row package structure are exposed from the first dielectric layer to the first dielectric layer, and a part is a bare wafer. … Openings ”for electrically connecting to the semiconductor 6. The method for manufacturing a ball grid layer substrate according to item 丨 of the patent application scope, wherein a multi-stage ball pad with f-split structure under the inner circuit board is used for electrical connection Several tins have been formed connected to an external circuit surface. 7. A method for manufacturing a multi-tier substrate for a ball grid array (BGA) package, which includes an inner layer circuit board provided on the upper layer, and the upper surface of the circuit board has a shape of 2a. The screen prints a first dielectric layer on the inner first conductive circuit, that is, the surface of the circuit board, so that the P01-074.ptd Page 18 494506 VI. Scope of patent application The first dielectric layer has a first opening;-forming several first via holes in the first dielectric layer and exposing the inner layer; A first conductive circuit of a circuit board; electroplating a first conductive metal layer on the first dielectric layer and a first conductive circuit exposed on the first via hole; selectively etching the first conductive metal layer to form a A second conductive circuit; a second dielectric layer is printed on the first dielectric layer by the screen so that the second dielectric layer has a second opening larger than the first opening of the first dielectric layer and is exposed. A part of the second conductive circuit; Forming a plurality of second via holes in the second dielectric layer and exposing the second conductive circuit; electroplating a second conductive metal layer on the second dielectric layer and exposing the second dielectric layer On the second conductive circuit of the hole; selectively etching the second conductive metal layer to form a third conductive circuit; A solder is formed to shield the wiring surface on the multi-layer substrate, so that the area on the conductive circuit for electrically connecting to a semiconductor wafer and the solder ball pad for electrically connecting to the outside are exposed to the g solder. 8. A method for manufacturing a multi-layer (mu 11 i -1 ier) substrate for a ball grid array (BGA) package structure according to item 7 of the scope of patent application, wherein the conductive circuit forming step is achieved by the following steps: The conductive metal layer is then selectively etched to form the conductive circuit. P01-074.ptd Page 19, 494506 VI. Patent application scope, 9. Multi-tier substrate manufacturing method for ball grid array (BGA) package structure according to item 7 of patent application scope, wherein the conductive The circuit formation step is achieved by forming a plating mask, and then electroplating a conductive metal to form the conductive circuit. 10. A method for manufacturing a multi-tier substrate for a ball grid array (BG A) package structure according to item 7 of the scope of the patent application, wherein the inner-layer circuit board further comprises a wafer holder provided on the upper surface thereof, Used to carry the semiconductor wafer 0: The A in G (B in the column, the matrix method is used to make the base board of the manufacturing board) 7 r th e • 1 round-t · IX It JnJ li u u (m Please ⑤ layer Shen Jieyi; the 11th construction of the package D-first layer of the dielectric layer of the first. In the exposed part of the bare system, the first half of the first to the access to the electrical power N > A in G (B is the list, the base of the matrix ball is made from the board) 7 r th e • 1 t t AT ATi i t tnj. The structure of the package sealing βτ outside the one-to-connected-\ gc electric power to form the number of solder balls with a pad has been surfaced. Road Ivl · ' P01-074.ptd Page 20 Electrical Guide, Board Circuit < 4