TW494482B - Method for forming an extended metal gate using damascene process - Google Patents

Abstract

A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure, wherein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer, whereby the metal gate layer has a greater width than the gate structure.

Description

^ 44 ^ 2, Description of the invention (1) [Background of the invention] (1) Field of the invention The present invention relates to the manufacture of semiconductor elements, and more particularly / in a self-aligning, Extension is the gate method. (2) Explaining the know-how, the semiconductor geometry continues to shrink, and design requirements require faster efficiency. X gate reduction, the gate delay resistance of the circuit delay gradually becomes important, and the metal to reduce the gate contact resistance of the metal Gate becomes a compelling option, but there are several issues preventing economically commercial metal gate fabrication. 〇, ϊ ϋ 1 'The top layer of the Γ structure is exposed and formed-the metal gate layer is opened and filled. Etching: The erosion of the dielectric material (ie, the infiltrated layer or STI), this infiltration causes multiple winding effects. Will generate a higher electric field, the danger of @filling the gap caused by the invasion of money will increase the multi-collapse problem. The accuracy of the gate continues to shrink with the gate geometry, because the pattern is reduced on the non-flat surface. Huaxu Yu Yu Fei # ί 2 poles of conventional techniques require lithography imaging steps. In addition, $ :: surface, it is difficult to achieve the necessary patterning accuracy. The contact window will change :: 2 a few: continued. : 'This setup forms a dogbone structure on the gate structure, ", compensates for this, extends beyond the field isolation, and these structures increase 1 y into a window \ for increasing the area of the contact window, ^ contact_resistance This causes circuit delays. ...,

Page 7 4944 ^ 2

The patents and technical literature related to click-throughs have various shortcomings mentioned above, and the closest and most obviously related are the following patents. And, and: 3 Γ No. 5'422,289 (Pierce) shows a flat source And / or pole and gate contact window structures. ^ Eng =, Patent, No. 5,856,227 ("etc.") shows a polycrystalline oxide compound " '" The second one is implanted through ion implantation-a thin residual polycrystalline silicon layer And the formation of 'after the oxidation of the thin residual polycrystalline silicon layer. U.S. Patent No. 5,915,183 (Gambino et al.) Shows a method of raising the source electrode and the extreme contact, using a blanket-type polycrystalline silicon layer for wall engraving. 0, U.S. Patent No. 5,807,779 ( Liaw) shows a process for forming self-aligned source and drain contact windows and regional intra-wire structures. U.S. Patent No. 5,869,396 (pan, etc.) shows a method for forming a polycrystalline silicide gate contact window. U.S. Patent No. 5,856,225 (Lee et al.) Shows a process of forming an implant channel region by removing an empty gate to form an implant opening and a self-aligning gate in the opening. U.S. Patent No. 5,731,239 (Wong et al.) Shows a method for forming self-aligned stone oxide gate electrodes [Summary of the Invention] / The main purpose of the present invention is to provide a method for forming a Method for self-aligning and extending metal gate. Another object of the present invention is to provide a separate mask and etching

Page 8 494482 V. Description of the invention (3) f Ϊ An integrated method of self-aligning and extending metal gate and source and drain contacts is formed. Another object of the invention is to provide a method for removing the multi-winding effect on the STI / source / pole junction. Another objective of Yicheng is to provide a method for self-aligning the gate electrode to form an extension with a reduced flatness difference during lithography. King Mi? The ... The present invention provides-a kind of formation-extension !, the semiconductor structure has a-idle structure on-a hetero-silicon oxide layer, and a car ss gate silicide layer, a doped interlayer and an orderly layer On top of each other, H 1¾ and Pyrene are formed on the side walls of the interpolar structure: Gap and V-body structure and gate structure, two complex 蛊 π, and the first-nitrogen-cut layer is covered; Xin discarded A closed dielectric layer is formed overlying the first nitride layer, and-a trench is formed on the gate structure; 2 cases are made in the bean layer, and the dielectric layer is formed by the width of the pole structure in the trench and the Discard the gate ;;, a first silicon nitride layer with a width greater than the gate system using one or more selective f = parts, a system with a dopant oxide to: In addition, the barrier layer is formed on the barrier layer with a highly selective U gate layer covering the two daggers; thereby: f silicide layer, and the X beam is larger than the width of the gate structure. 3 The metal barrier layer has — the present invention provides a heavy pole that exceeds the conventional technique and provides an increase in the tolerance for setting the contact window of the idler electrode to extend the metal space to clear the need. Page 9 494482 V. Description of the invention (4) dogbone The structure covers the need for a field isolation structure. Since the present invention provides a higher selectivity of the doped silicide layer in the gate structure than the undoped silicide layer in the infiltration layer, the multi-winding effect can be avoided, and due to the etching, The lithography step is performed on a flatness, so the errors of the lithography step can be reduced, and the patterning accuracy can be increased. The present invention achieves the advantages of known processes. However, the purpose and effect of the present invention can be understood and obtained from the specification and drawings. [Comparison of drawing number] 11 Semiconductor structure 12 Shallow trench isolation (STI) structure 15 Isolation trench 19 Isolation mask 20 Gate structure 22 Gate dielectric layer 24 Gate silicide layer 26 Doped silicon oxide layer 28 May Discard the gate layer 29 Gate mask 30 Dielectric cell Γ: Λ Wall 40 Filler layer 50 First silicon nitride layer 52 Second silicon nitride layer 54 Photoresist mask

Page 10

494482 V. Description of the invention (5) 60 dielectric layer 6 5 trench 7 0 barrier layer 80 metal gate layer 90 second dielectric layer 93 metal gate contact window opening 95 source and drain contact window opening [compared to Description of the preferred embodiment] The present invention will be described in detail with reference to the drawings. The present invention provides a method for forming a self-aligned extended metal gate, and the present invention also provides a method for forming a self-aligned extended metal gate and self-aligning Method of quasi-source / drain contact window. [First Preferred Embodiment] Please refer to FIG. 1. The first embodiment of the present invention starts by providing a semiconductor structure (1 1). It can be understood that the semiconductor structure (1 1) may include A wafer or substrate with semiconductor material, such as silicon or germanium, an insulating layer on silicon (SO I), or other similar structures of known technology. The semiconductor structure (11) can be understood to include one or more A plurality of conductive and / or insulating layers are covered on a substrate or the like, and one or more active and / or passive elements are formed on a substrate or the like or covered on a substrate or the like. Referring to FIG. 1 again, a gate structure (20) is formed in a semiconductor structure.

The gate structure is preferably formed on the semiconductor structure (11) 1 1) on the MU). Although Shi Xi, b Shi Xi layer, g pole layer I * use any k has a 1 electric constant Shi Xi (multiple days and days Factory year, ·: Λ deposited silicon nitride thick; see Figure 1, patterned gate dielectric layer (22), gate silicide layer-> hetero-silicon oxide layer (2 6), and The gate layer (2 8) is discarded to form a gate structure (2 0) with a sidewall. The gate structure can be lithographically imaged, such as a photoresist layer, a photoresist layer, or through a photomask or pattern. It is formed by exposing the photoresist layer and developing the photoresist layer—the photoresist mask, etching the bottom layer through a photoresist mask, and removing the photoresist mask). A dielectric spacer (30) is formed on the gate. Description of the invention (7) On the side wall of the one-pole structure (20), ^ ^ blanket deposition, gap clearance (3 (η 6), the dielectric of the dielectric after anisotropic etching, read the "quotation of ()") The electrical quality is preferably composed of silicon nitride. (4 .... 4:;: doped on the electrode enhancement layer (28), the infiltration layer grinding process (CMP) is planarized and flattened. And a chemical mechanical research Referring again to Figure 2,- —Name 1 "/ Discard the leisure pole layer (28) and the percolation layer = Xi layer (50), and form a person who can cover (= she learns vapor deposition;) (second layer (50) =:% phase deposition) Formed for the best, the thickness of the -N cut individual is between ⑽Angel and 2, ° 0 ° Angstrom. ^ &Quot; Λ ^ ce! 6; ^ ^ ^ ^ When the dielectric properties of the material :: ：:: Silicone 'but it can include suitable 坌-^ & jitter and & selective money carved into the dielectric layer (60), which can be formed in a dielectric layer called patterned dielectric layer to form First, check the width of the closed-pole structure (20) (as in No. 4; so ^ ', its width has a width by patterning a photoresist mask (54) without being patterned. Good hunting of the photoresist mask (54) and etching the second nitride (shown in the figure), and penetrate the first silicon nitride layer (50), including the f (52), the dielectric layer (⑼ For example, during the rest of the time, the discardable and discardable gate layer (50) was removed. Including how many layers: = layer will be able to communicate with the first-nitride stone, after removing the first After the silicon nitride layer 2 discard the gate layer (28) and discard the gate layer will remain, as shown in the fifth and the description of the invention (8) 4 See Figure 5, if available * ― dry etching (the gate layer (28) includes polycrystalline silicon, this selection is based on the selective polycrystalline silicon ratio ^ instead of HBr / CL2 / He—%, dry etching more / Polycrystalline stone is better than doped oxygen stone; ^ mixed oxide stone is at least 2: J,-= with -selectively doped oxygen 6 demulsified silicon layer (26) is used _ I: carved is preferably-a wet II; Γί Fossil Xi's engraving and the shifted / reduced silicon oxide ratio is undoped x ... Water Song ^ HF etching, and has the present invention-one important: Xi t at 5 °: 1. Etching in the infiltration layer (4 {)) = ^ highly selective doped oxidized oxidized etched bottom of the trench and exceeded; electricity. : Invasion of silicon, insects, which are exposed on Lingyue (Fig. 6A, a barrier exhibition). The barrier layers include; ... titanium, tungsten nitride, and nitride or nitride. Thickness between titanium and nitride. The current genus / percent reach—one in the range of 50 Angstroms to 2,000, in metal; polar layer (I◦ genus) :: (铭 Ming-copper) or copper or-one including two or = Ming alloy (ie It belongs to the combination of the gate layer (80) and the barrier layer (了 "), and the second gasification v layer is binary ^ formed in the trench (65) and self-aligns the width of Γ ' This series of narrow gates is easier to install on the contact window. Wang ~ Ji is more than the conventional technique on page 14 of the invention description (9) Refer to Figure 6B, a second dielectric band layer and a second nitride layer, Second: Acoustic 90 °) is formed by covering the gate with gold-doped silicon oxide or other suitable materials, ^ ^ = presence or absence of doped silicon oxide or metallization to form a metal open electrode contact window opening ^ (9〇) Pattern = 95), the source and non-contact contact openings are the first and second contact windows (90), the second silicon nitride layer (52), the first, the dielectric layer layer (50), and the infiltration layer ( 4〇)。 〇), the first silicon nitride [second preferred embodiment] Referring to Figure 7A and Figure ", the present invention-semiconductor structure ⑴) began, as; ::;:" system It should be understood that semiconductors should be described and Limited by half and two: The semiconductor structure (11) may include a semiconductor material (f = 1), such as silicon or other similar structures of known technology. U Take the substrate, still refer to Figure 7A and 7B In the figure, a gate dielectric layer (22), a silicide layer (24), a doped silicon oxide layer (26), and a gate electrode (28) are continuously formed to cover the semiconductor structure (n). The gate eight = layer (2 2) preferably includes a layer having a thickness between 丨 0 angstrom and 2000 angstrom, but may include a dielectric constant having a desired dielectric constant greater than 3 and 2 = ( For example, nitrided oxide, oxide group), gated oxide layer (2 4) may include / / Shi Xi (polycrystalline Shi Xi) or amorphous silicon (α-silicon), it is best to use an Lpcvd. ^ Crystalline Deposition reaches a thickness between 300 angstroms and 3,000 angstroms. The doping process and the layer (2B) is preferably composed of pSG or BPSG, and a chemical * gas emulsified stone product is best used ( For example, PECVD, HDP-CVE, or SACVD process), and ^ 二 ^ 沈 五, Invention Description (10) :: Thickness between m Angstrom and 2,0 0 0 Angstrom, the chemical vapor deposition ', / Diethyl Doping of an acid ester or triethyl phosphate. The polarizable layer m) preferably includes a nitride stone, and preferably has a thickness between 100 angstroms and 2,000 angstroms. As shown in Figures 7A and 7B, the gate layer (28), the L-doped layer (2mm), the gate stone layer (24), the gate dielectric layer (22), and (Semiconductor i: Pregnancy 21 ancient) is patterned to form an isolation trench (15), the isolation trench II === depth between U0 0 Angstroms to 5, Angstroms, and in half to two soil plates Under the top surface, the gate layer (28), doped silicon oxide layer, gate silicide layer (2 4), gate dielectric layer (2 2), and semiconductor beauty can be discarded: (口 1 1) 可Lithography technology is used to form an isolated etching mask (1 9) 彳 I on I :::: Urgent] (28) and patterned, if the gate layer (28) can be discarded by Xin gate, Divide two and two, and the remaining layer can be engraved by 1 insect carved in #etched by Kou: (T opening 'In this example, silicon nitride is used as a-hard mask π ^^ away from the etching mask (1 9 ) Can be removed after the isolation trench (15) is completed. The advantage of the present invention is that it provides more precise lithography control.勹 卞 -'s ridge 4M, Ϊ: Γ flat, 浅, shallow trench isolation (STI) structure (12) is a dielectric layer of SiO2 and is formed in the isolation trench ::: Good use of a chemical machinery The grinding process is flattened and stopped on the discardable gate layer (28). Refer to FIG. 9A, FIG. 10, and FIG. 10A. Gate layer (28), doped oxide layer 26), // 2. 5. Description of the invention (11) " Electric layer (22) is patterned The engraved mask (29) is formed in the discardable second structure (20), and a gate erosion is shown in FIG. 9B.极 极 刻刻 幕 ㈣ (㈣; (Package: No ....) Presentation :: Li Cheng: Photoresistance, and further 'During lithography imaging, increase the accuracy of the lithography imaging process and the gate of the result ... once the gate layer (28), the doped silicon oxide layer (2) can be discarded. (24), the gate dielectric layer (22) is etched through the "etching mask" = layer f Λ etch chemistry includes: SF, V, or: f / ο $ 2 6 / 〇2 / HBR (for etching of silicon nitride (28)), CF / (: 2Η C ^ (26)). HBR / CL2 / He? 〇 (L ΗϊI 3 layer (24) etching) and HF (Hr fluoride 2; A 1 pole etch). Tailu 51) Emulsion (for gate dielectric layer (2 2) an important advantage It is based on the doped silicon oxide layer m water HF_ and selectively kills it (12). The patterning and "β picture" partition wall (30) is formed at the gate = (2〇), STI ( On the side walls of the concrete, the gap wall is preferably made of nitrided silicon. The blanket deposition and vapor-anisotropic etching of siliconized silicon are shown in Figure 12, and an infiltration layer (40) is formed. The semiconductor structure layer is best covered with a flattening plane: stop on the discardable gate layer (28), and infiltrate the filler 有Silicon oxide, and it is best to use chemical mechanical polishing for planarization. Sensing ^ η Refer to Figure 12, a silicon nitride layer (50) is formed to cover the infiltration and gate structure (20), a The dielectric layer (60) is formed on the first 494482. V. Description of the invention (12) The nitride layer (50). The first silicon nitride layer (50) can be formed using ApCVD, PACVD, or Part is best to use an LpcvD process, and is preferably formed to a thickness between 100 Angstroms and 2,000 Angstroms. The dielectric layer (60) is preferably composed of undoped silicon oxide. During the CVD process, the dielectric layer preferably has a thickness between 500 and 5,000 Angstroms. "Refer to Figure 12, a photoresist mask (54) is formed using lithographic imaging. On the dielectric layer (60), the photoresist mask (54) has an opening covering the second gate = (20); the opening in #photoresist mask (54) has a large mine structure (20) The width of the width. One advantage of the present invention is that the dielectric g U0) has a flat surface as an accurate lithographic process.: See Figure 13 'Dielectric layer (60) series The trench (65) is formed by etching (: 0) through the opening in the photoresist mask (54), and the dielectric layer (60) is formed on the gas nitride layer (50). Using a squirrel of silicon and being photocopied by the imager, the photo-resistance of the photo-resistor is not greater than 10: 1. After the trench (65) is formed, the mask (54) can be used —Removed from the ashing process, # 第 13 图 所 (28);: 'Exposed to the bottom of the trench (65) and discardable gate layer height selection! · Diamond diamond 11 silicon layer (50) can be Using a gate selective etching of silicon nitride rather than silicon oxide, the charge is chemically removed by centering 〇2, or ch3f / 〇2; each has 臓 / CL2 / 〇2, ⑽ is preferably one and 1 +, Electro-water etching, or a hot phosphoric acid etching, the most gap wall (30) in the infiltration layer (4 (^^ =, because this will leave a part of the intermetallic gate metal diffusion. This will help prevent the subsequent formation of gold. Referring to Figure 14 again, the H L heteroemulsified silicon layer (2 6) uses a wet anhydrous

494482 The wet type is not greater than 50: 1. The exposed part of the water HFI engraved with a barrier layer is filled (40). The following ingredients are included in one of the barrier genus at 50 angstroms. 5. Description of the invention (13) HF It is removed by etching. The advantage of silicon over undoped oxide is that the wet type has no infiltration layer on the edge (40). See FIG. 15, the spacer (30), and one or more infiltrations. A plurality of tantalum, and preferably having a metal gate layer (80) system, includes various conductive gold or copper. The water HF etching system has a selectivity of doping oxidation. An important aspect of the present invention is that it cannot effectively etch the trench (65) portion to avoid the multi-winding effect. (70) formed on the exposed area of the metapolar petrochemical layer (2 4), the barrier layer (70) includes a silicon nitride, a silicon nitride, a short silicon nitride, or a nitride nitride thickness. On each gold (0), the metal gate layer (80) can be, for example, tungsten or aluminum (elemental or alloy). The first solid metal gate layer (80) and the resistance barrier are: Flattened and stopped: ::: = metal idler layer ⑽ extends beyond the pole :::: layer 0) formation-extended metal gate: bit ,,.体 (20) 'Metal width. This article shows that a larger area than the gate structure width is used as the gate:

Therefore: Effectively use the wheel or improve the pattern = set closer: Cha see Figure 16,-篦 二 介 帝 / metal layer (80) and dielectric layer ⑽ :::::: on gate silicon or doped Silicon oxide or other suitable "includes the presence or absence of doping oxidation to form the gate; contact = ohm ^ (95), the source and non-contact contact vapor ησ) and the source and drain contact windows open before contacting ® opening extension Through the dielectric layer (60),

494482 V. Description of the invention (14) Silicon nitride layer (50) and infiltration layer (40), the openings of the source and drain contact windows can be formed by silicon nitride formed on ST I (1 2) The partition wall (30) is self-aligned. Although the present invention has been particularly shown and described with reference to the preferred embodiments thereof, various changes in form and detail may be made without departing from the spirit and scope of the present invention, which can be done by those skilled in the art. understand.

Page 494482 The diagram briefly explains the characteristics and functions of the semiconductor element according to the present invention and further details of the process for manufacturing the semiconductor element according to the present invention will be clearly understood from the following description in conjunction with the diagram, where the same reference number means Identical or related components, regions, and parts, wherein: Figures 1 to 6B illustrate a continuous cross-sectional view of a first preferred embodiment of the present invention, illustrating a process for forming a self-aligned extended metal gate. Figures 7A to 11A are successive top views illustrating a second preferred embodiment of the present invention, and illustrate a process for forming a self-aligned extended metal gate.

Figures 7B to 11B and Figures 12 to 16 are continuous sectional views illustrating a second preferred embodiment of the present invention, where Figure 7B is an axis 7B as shown in Figure 7A A cross-sectional view of -7B ', FIG. 8B is a cross-sectional view of axis 8B-8B' as shown in FIG. 8A, and a 9B is a cross-sectional view of axis 9B-9B 'as shown in FIG. 9A, and FIG. 10B 10A-10B ′ are cross-sectional views as shown in FIG. 10A, and FIGS. 1B to 12 to 16 are cross-sectional views as shown on axis 1 IB-1 1B ′ in FIG. 11A.

Page 21

Claims (1)

A. Please search for profit. 1 The method of opening 20%, extending the metal idler, includes: a. /, Semiconductor structure, which has a gate structure on it. I] '! Structure side wall; the gate structure Including-gate dielectric on a bulk structure, a gate silicide layer on the gate dielectric: a doped silicon oxide layer on the gate silicide layer, and a polarizable layer on the doped silicon oxide On the layer, the gate has a gap wall on the side wall of the free pole structure; /, there is a gap b-shaped f a dielectric gap wall on the side wall of the inter pole structure; the sun umbrella; Thousands of times permeate the infiltration layer on the semiconductor structure and the gate structure, and stop on the discardable closed-electrode layer j a, "The silicon nitride layer covers the discardable gate layer; • ^ a: An electrical layer covers the first nitride layer; • a second silicon nitride layer is formed to cover the dielectric layer; g • a second pattern on the pattern is formed to form a trench to cover the gate electrode The trench has a width greater than the width h of the gate structure. The first silicon nitride layer at the bottom of the trench is removed ... Pole layer; 9 storm roads • the gate silicide layer is staggered; / layer,! Forms a barrier layer to cover the gate silicide layer; and 'forms a metal gate layer on the barrier layer and on The metal gate > 1 in the right ^ trench, the layer has a width greater than that of the gate structure of 494482. 6. The width of the patent application scope. The method described in item 1 of the patent application scope includes: Any one with a dielectric constant greater than 3. The method layer described in item 1 of the patent application scope includes polycrystalline silicon (polycrystalline silicon). The method layer described in item 1 of the patent application scope includes amorphous The method described in item 丨 includes the presence or absence of doped silicon oxide. The method described in item 1 of the scope of patent application includes a silicon-phosphorus glass (PSG). The method described in item 1 of the scope of patent application The method includes borophosphosilicate glass (BPSG). The method described in the scope of patent application item 1 includes oxidation; ^. The method described in the scope of patent application item 2 includes silicon nitride. The method described in item i of the patent scope (Polycrystalline stone) The method described in item i of the patent application, the silicon layer is removed using anhydrous HF vapor etching, and the method described in item 11 of the patent application, gas etching has a selective doping oxidation. Silicon at 50 ·· 1 〇 2 4 5 6 7 8 10 11 Which material is the gate dielectric. Wherein the gate is silicified, where the gate is silicified, where the infiltration layer is, where the doping is oxidized, Wherein the dielectric layer system, wherein the dielectric layer system, wherein the discardable gate, wherein the discardable gate removes it to cause the doping to oxidize it, the anhydrous HF tomb ratio is not doped with oxide oxide; 12 494482 VI. Patent application scope 1 3 · The method as described in item 1 of the patent application scope, wherein the disposable gate layer includes polycrystalline silicon, and the disposable gate layer is removed using a plasma assisted #etch, the Plasma-assisted money engraving has a selective polycrystalline silicon ratio of at least 2: 1 to undoped silicon oxide, and a polycrystalline silicon ratio of silicon nitride to at least 2: 1. 1 4. The method as described in item 1 of the scope of the patent application, wherein the disposable gate layer includes a nitride layer, and the first nitride layer is removed. 15 · According to the method described in item 1 of the patent application scope, a metal gate layer is subsequently formed, comprising the steps of: 1 · using a chemical mechanical polishing process to planarize the metal gate layer and the barrier layer, Stopping on the second silicon nitride layer; m. Forming a second dielectric layer covering the metal gate layer, the barrier layer and the second silicon nitride layer; and η patterning the second A dielectric layer to form a contact window opening of the gate structure, and pattern the second dielectric layer, the second silicon nitride layer, the first dielectric layer, and the fill layer to form a source electrode And the drain contacts the window opening. 16. The method as described in item 15 of the scope of the patent application, wherein the second dielectric layer includes undoped silicon oxide. 17. The method as described in item 15 of the patent application, wherein the second dielectric layer includes doped silicon oxide. 1 8 · A method for forming an extended metal gate and a self-aligned contact window, comprising: a. Providing a semiconductor structure; the semiconductor structure having a gate Page 24, 494482 ', the scope of the patent application of the polar dielectric layer on the ^ ^ layer on it :, the gate dielectric layer is coated on it. You should have closed-cell silicide layer-- The q4 hetero-silicon oxide layer has — # SiO2 layer in κ 'can discard the gate layer in the dragon b. The patterned pattern can be removed, called ,,,,,,,,,,,,,,, and, a dielectric layer. To form shallow trenches? Isolation: C. Formation of shallow trench isolation by depositing and flattening (STi) structure; η electrical layer. D • Patterning the discardable gate chip formation layer and the gate electrode, the dopant A mixed oxide sand layer and the gate structure are formed to form a gate electrode with a side wall, a dielectric gap is formed on the side wall of the cover structure, and an infiltration layer is formed on the side wall, and the permeation layer is flattened. A semiconductor structure and the interelectrode structure; a true layer stopped on the discardable idler layer 'to form a silicon layer on the discardable idler layer and the infiltration layer; h. Forming a dielectric layer overlying気 several 々 β μ · l pattern the dielectric dwell on the silicon layer, the structure of the trench; one: the formation-trenches benefit the width of the open electrode junction; The width of the pole structure: = the nitrided layer at the bottom of the trench;. The discardable gate layer is removed; thereby exposing the doped oxide layer -------- page 25 'Use a selective etch to the doped silicon oxide layer without the doped silicon oxide; the doped silicon oxide layer is removed from the layer to form a barrier layer overlying the gate polycrystalline silicon layer; and A metal gate layer is on the barrier layer. Layer ° 1. The method described in item 18 of the patent scope, wherein the gate dielectric 2 0 · ^ = = includes any material with a dielectric constant greater than 3. ^ Zuo, the method described in item 18 of the patent scope, wherein the gate is silicified 21. ^ The polysilicon (polysilicon) is enclosed. ° The method described in the scope of patent application No. 丨 8, wherein the gate electrode 22 •: is J including amorphous silicon ◦ The method described in the scope of patent application No. 丨 8, wherein the doped 23 ·: layer: includes There is Xixi Glass (PSG). The method described in item 18 of the scope of patent application of Emulsification II, wherein the doped oxygen layer 24 includes a layer of borophosphosilicate glass (BPSG). / The method described in item 18 of the scope of patent application, wherein the Kotowa gate 25 ·; layer: including nitrogen cutting. 'The method described in item 18 of the scope of Shenyue's patent, wherein the infiltrated reed system 26 · ^ includes non-doped silicon oxide. The method described in item 18 of the scope of patent application, wherein the dielectric layer comprises: undoped oxygen cutting. The method as described in claim 18, wherein the doped silicon oxide layer is removed by etching with anhydrous HF vapor. The method of patent claim No. 27, wherein the anhydrous H F is steamed 29 3〇, P. q. 31, 32. Scope of patent application of the emulsion etching has a selective doping of silicon oxide to 50 ··. "、, doped silicon oxide is large. • As described in the method of patent application No. 丨 0, the compound gate electrode layer is etched by using HBR / CL2 / Q, the silicon nitride and Μ. , Which has -nitriding; ratio ν: ν〇2, or selective etching between 10: 1 and 30, and U silicon oxide is selected between 10: 1 and 30: 1 in undoped oxide stone = For example, the method described in item 6 of the scope of patent application, dinitrium, is optional, = a metal gate layer, and the steps include the following steps: • After the tunnel has a tunnel shape, use a mechanical mechanical grinding process to flatten the surface. The metal gate axe Sx barrier layer 'stops on the dielectric layer; that is, a second dielectric layer is formed to cover the metal closed electrode layer and the dielectric layer; and ~ patterning the second dielectric layer, To form the contact structure of the gate structure, the mouth, and pattern the second dielectric layer, the dielectric layer, the first silicon nitride layer, and the infiltration layer to form a self-aligned source drain Contact window opening: Π: The method described in the item 29 of the range, wherein the second dielectric π G includes an undoped silicon oxide. The method described therein, wherein the second dielectric