TW494448B - A video bus for high speed multi-resolution imagers and method thereof - Google Patents

Abstract

A bus system and an imager for transferring signals from a plurality of signal streams to cm output includes a plurality of signal buses in parallel and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to the output. A method for transferring signals includes multiplexing signals on to two or more of a plurality of signal buses and allowing the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to an output.

Description

^ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494448 Description of Invention (1 / This case is the consecutive case of application No. 09 / 490,374 on the application date of January 24, 2000, and this case is US Patent No. 6,084,229 No. awarded to part of the serial case dated July 4, 2000. FIELD OF THE INVENTION The present invention relates generally to buses, and more particularly to video buses used in high-speed multi-resolution imagers. BACKGROUND OF THE INVENTION A device is a semiconductor device that can convert optical images into electronic clues. The imager can be arranged in a matrix and used to generate video signals for cameras, cameras, or any other place where it is necessary to quantify incident radiation. When incident radiation When interacting with the shutter, the charge carriers are released and can be collected for sensing. The number of carriers collected at the shutter represents the amount of incident light that hits the location at a specified time. There are two basic devices with multiple The change can collect and sense light-closed charge carriers. The two basic devices are a photodiode and a light gate. The changes of the photodiode include, but are not limited to: pins, p + N, gold Semiconductors, non-homogeneous junctions, and bursts. Light-to-light structures include electrical and electronic assembly (CCD), charge injection device (CID), and variations including virtual phases, embedded channels, and other changes using selective dopants. The dopant is selected to control the collection of charge, and to transfer under and between the shutter and the sensing node. The solid-state imager used so far has a lower noise than the photoelectric two-handle body and chirp, so the CCD is used as The main advantage of the low noise of the imager is that the charge generated by the photons collected at the pixel position is combined with the actual charge or shifted to the amplifier around the array. This eliminates the need for long polycrystalline stones ------- ------------ Order --------- (Please read the notes on the back before filling this page) -n n-

This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 Public Love 1 494448 Printed clothing A7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (2) and the metal bus will cause signals and their correlation The resistance and capacitance of the CCD are degraded. However, the low noise of the CCD requires that the imager be read in a fixed format and destroyed once the charge is read. It is required that the photon charge collected by the pixel is coupled to a peripheral amplifier (also known as CTE) Dedicated processing steps are required to be incompatible with industry standard CMOS or BiCMOS processing. The solid imaging device is developed in parallel with CMOS technology. As a result, imager manufacturers have developed their own dedicated processing to increase performance characteristics and wafer yield to The largest. Specialized silicon wafer processing has caused the imager price to be quite high. Linear King motion pixel sensors have been commercially manufactured since 1986. Since the early 1990s, continuous promotion of dedicated processing to the industry standard CMOS processing has been promoted. Use The advantages of industry-standard processing include the competitive price of wafer processing and the ability to provide on-chip timing, control, and processing electronic circuits.1 By the end of 992, a 612x512 CMOS compatible CID imager was manufactured with a set of amplifiers and CDS per line. The imager can be random access 5i2 X Η] CID operation, or each line is added up to form one Linear active pixel sensor operation. The area array using Wang moving pixel sensor, in which a photocoupler or shutter system is coupled to the output source follower amplifier, which in turn drives the cross-correlated double f sampling (CDS) circuit, which The second output of the processing lattice drives the second source / mover and it feeds into the difference amplifier. The area array is shown in US Patent No. 5,47U15 Ε and is described here for reference. A pole follower circuit, which typically has a gain less than i, varies with each source and follower. The change in the gain of the source follower is due to the change in Qiu Dingzheng. The change in the gain of the source follower results in pixels The gain of the pixel is not ^ -------- ^ --------- (Please read the precautions on the back before filling this page)

This paper ruler lays wealth (210 X 297 mm) 494448 Α7 Β7 5. Description of the invention (3) Matches. When the CDS uses a pair of source followers to drive its output, the active pixel sensor changes its gain due to the CDS circuit of each row. As a result, the CDS signal and its corresponding compensation have different gains and cannot be corrected by a differential amplifier. The source follower configuration of the active pixel is not allowed to be boxed. »--* ≪ + ·’-The prior art voltage operation mode does not allow boxing, that is, summing two or more pixel signals at a time. There is a need for an imager that has a low noise level for CCD, random access, CID boxing, and consistent gain and response from each pixel; while maintaining low power, ease of use, and high analog frame rate. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) In addition to finding an imager with a low noise level of CCD, random access, CID packing, and In addition to consistent gain and response, imagers suitable for industrial and / or scientific applications are also needed. In the past 30 years, the development of CCD sensors and camera electronics has met most of the needs of industrial and scientific applications. However, the resulting camera requirements The current state of the industry achieves this project with large pixels, multi-port CCD chips plus several additional chips and usually several circuit boards filled with electronic circuits. In this way, the camera cannot physically fit some application purposes, its power consumption is large, and the result The resulting cameras are too expensive for many uses. The need to reorganize video data from several ports further increases the complexity of video processing, and ultimately drives the cost and size of video systems. As in previous years, Discussion, as the design rules shrink, the use of sub-micron CMOS processing technology The image sensor becomes practical. Through the use of CMOS technology for the sensor array itself, additional circuits are integrated on the chip-6-This paper size is applicable to the national standard (CNS) 8 4 specification (21〇χ 297 mm) ~ ~ " '494448 A 7 B7 5. The problem of invention description (4) becomes direct. It is easy to add components such as A / D converter, timing generator, control circuit and interface circuit. In addition, the operation of CMOS imager can be controlled by Simplified by eliminating the need to drive multiple CCD-specific bulk capacitor transfer gates that require precise timing and level control of multiple clocks. Even with all these factors, including the extra speed of sub-micron processing and picosecond gate delays, over the past 20 years The analog video bandwidth of each port has not changed. Active pixel sensors (APS) have been proposed as a flexible effect of CMOS cameras on a chip. Unfortunately, there are performance issues with basic APS discrimination that limit their performance and functionality. Restricted to low-end consumer imaging applications, but so far scientific, professional, and industrial applications still require more than CMOS image sensors Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) Special industry and scientific imaging applications require far higher performance and functions than lower-end consumer imaging products. Multiple application uses Requires high readout speed or even faster imaging without sacrificing image quality. In addition to image quality, applications also require higher camera performance. It has various features such as flexible shutters and electronic trimming, random access, and Select the region of interest to obtain the maximum frame speed and minimize the storage of data (especially for tracking purposes). Reducing the development cost of machine systems is a major advancement in recent single-chip CMOS cameras. Newly developed CMOS cameras have all the previously listed Flexible, but the analog video bandwidth of each port is still the same as traditional CCD, CID or photoelectric diode technology. The maximum pixel rate of most half-megapixel image sensors including CCD imagers and APS imagers is still insufficient to meet the frame rate requirements in industrial and scientific imaging. The CCD device is subject to clock rate and cross-correlation double sampling (CDS). The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 494448 A7 B7. 5. Description of the invention (the speed of the circuit is limited. In addition, the Pixel rate requires higher amplifier bandwidth and noise. Due to the parallel parallel nature of CMOS imagers, amplifiers and CDS can operate at line rate instead of pixel rate. Video bandwidth limitation is limited by multiplexing speed. CMOS imager The signal is typically multiplexed to a common analog video bus. The more multiplexed or switched signals on the bus, the larger the capacitive load of the bus. Therefore, when there are more signals connected to the bus 'The bandwidth of the bus is reduced. In addition, a larger amount of power is required to charge and discharge the bus with the relevant capacitors to maintain the bandwidth. The aforementioned traditional bus structure involves switching N signals to one bus. With parallel parallel amplifier 100 An example of the cmos imager 98 driving the public video bus 102 is shown in Figure 5. In this example, the staff of the Central Standards Bureau of the Ministry of Economics Printed by the cooperative (please read the notes on the back before filling in this page) Most of the 102 are used as the capacitive load of the individual row amplifier 100. In order to make each amplifier 100 pixels present pixels to the public video bus 102 Each amplifier 100 must charge or discharge the bus 102 within a pixel time constant. The pixel signal must be a sample and hold circuit (or similar) circuit% for a long time. The stabilization time is long enough to accurately present The resulting signal is to an A / D converter (not shown in the figure). Typical requirements are at least 5τ (tau or time constant). The video bus 102 is accurately allowed to determine the video presented by the individual line amplifiers 100, but can be changed according to various applications At higher video bus speeds, each of the amplifiers 100 cannot properly charge or put the television signal bus 102, resulting in the loss of contrast ratio. At higher pixel element rates, when the contrast ratio is impaired here, the characteristics of individual amplifiers and Video exchange characteristics begin to affect the resulting video. Individual line amplifiers 100 have slightly different compensation and slightly different driving capabilities. And each video switch 120 has a slightly larger paper size and is applicable to Chinese National Standard (CNS) A4 specifications (210X297 Gongchu). Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 448 A7 ^ ~ ---- B7 V. Description of the invention (6 ) Slightly different resistances and slightly different thresholds. This combination of line amplifier and video switch characteristics results in different time constants for the charging and discharging of each row amplifier 100 compared to the video bus 102. Row amplifier 100 And the video switch 120 is common to each pixel of the row. Such changes in the characteristics of the video switch result in behavior-based fixed pattern noise (FpN). As more rows are added, each video switch 120 is due to a MOSFET or bipolar current. The source and drain of the crystal interface to add more associated capacitance 14. The greater the number of rows added to the hidden current bank 102, the higher the total capacitance. To overcome this limitation, CCD and APS sensors were previously designed in such a way that the imagers are grouped together into smaller groups of halves, 1/4, or sub-renderers. Such a previously designed solution is shown in FIG. 6, for example. In this example, the 'imager 80 is divided into four sub-imagers 80 (1) -80 (4). The signals from each of the sub-imagers 80 (1) -80 (4) are sent to its own port 82 (1) _82 (4). This structure or architecture also involves the signal flow of more N signals to a bus. This design is used to provide high frame rate devices and meet the standard frame rate of large megapixel imagers. Unfortunately, this design results in increased system size, complexity, and the power and cost required to handle multiple analog amplifier chains. In addition, fully balancing the amplifier chain at all possible pixel rates and temperatures is a challenging task. With the increase in the size of the imager in recent years, it has now become a full wafer size, and this issue is even more problematic. Process variations across an array result in further balancing issues, and even process variations across a wafer can cause changes in noise characteristics. SUMMARY OF THE INVENTION According to a specific embodiment of the present invention, transmission of letters from most signal streams __ 9- This paper size applies ^ 5 ^^ standard (〇 奶) 8 4 specifications (210 '/ 297 mm) --- ----------- (Please read the notes on the back before filling out this page) Order 494448 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Invention Description (7 / Bluff to Spoke Convergence The bus includes multiple parallel signal buses and a control system: the control system multiplies signals from two or more signal streams of most signal streams to two or more buses of multiple signal buses, and selects k Until the multiplexer is known, the signal is allowed to charge substantially two or more individual buses of the multiple signal buses. ^ The imager of another specific embodiment of the present invention includes most signals / melons. Parallel signal bus, one output and one control system. The control system is filled with signals from two or more of the digital signal stream and multiplexed into multiple signal H-machines—or two or more (that is, input multiplexers) ), And from the signal solution to the output multiplexer Allows the signal to substantially charge two or more individual buses of multiple signal buses. According to another specific embodiment of the present invention, a bus system that transmits L numbers from most signal streams to a lucky one includes multiple signals The bus is coupled to most of the signal streams, a plurality of first switches, a plurality of second switches, and a control system, and each one of the switches is integrated into one of the plurality of signal streams and the plurality of signal buses. One. Each of the plurality of second switches is coupled between one of the plurality of signal buses and the output. The control system is coupled to the first and second switches, and two or more of the plurality of closed first switches are coupled. Coupling signals from two or more signals from multiple signal cores to two or more of multiple signal buses' and one or more of the second switches of the closed-circuit output multiplexer Before output, the signal is allowed to substantially charge two or more individual buses of the k-th bus. In other words, the aforementioned system involves multiplexing N signals to two or more buses (or M buses). Row), and then multiplexed to a bus, or in other words, more than -10 · This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) (Please read the precautions on the back before filling in this Page)

ϋ i_l ϋ · ϋ w V I MM ΜΗ · Η ·· * · I MM Oh I and multiple outputs A7 V. Description of the invention (8) Industrialization into a two-stage multiplexer with—input. The two-stage multiplexing system allows for how rare it is-add multiple numbers or like "," the same operations, such as allow signal, and allow-select multiple signals or pixel signals. Pixel signals can be alternately selected individually, and Then the two-Duhuo can be selected, allowing the signal to be averaged or interpolated, effectively changing the pixel = resolution to obtain a higher or lower resolution. The present invention is coupled with the active row technology described in United States: Lidi No. 6,084,229 (and described herein for reference) to allow boxing or jumping of pixels in the heart row and / or row. According to yet another specific embodiment of the present invention, a method for transmitting a signal includes multiplexing a signal to two or more of a plurality of signal buses, so as to learn from the multiplexing of the selected signal. Previously, the allow signal was essentially two or more individual buses of the L L buses, also called input multiplexing. Yet this particular embodiment includes a reordering multiplexer that re-sequences signals to—or multiple outputs—from the output multiplexer. Brief description of the drawings Figure 1 is a prior art dual polysilicon active pixel sensor; Figure 2 is an active line sensor according to the present invention; Figure 3 is a pixel practice according to the present invention; Figure 4 is a pixel matrix connection combined with each pixel A schematic illustration of a complete operation to enlarge and form an active line sensor; A view of a conventional method for driving a common video bus on an imager; Figure 6 is a conventional CCD with multi-port video bandwidth and View of CMOS sensor method; 11- 1 x 297 mm) I ^ t --------- Ψ (Please read the precautions on the back before filling out this page) System 494448 V. Description of the invention (9) FIG. 7A is a schematic diagram of an imager with a high-speed, low-noise bus system according to a specific embodiment of the present invention; FIG. 7B is a decoder of the imager shown in FIG. 7A; An enlarged view of a circuit to be selected; FIG. 7C and FIG. 7A are image address counters and control views of the image; FIG. Is a schematic diagram of an imager according to another embodiment of the present invention and an imaging accessory with a bus system In pixels For improving the resolution; FIG. 8B is an enlarged view of the silly crying corpse μ 2 + powder from the elephant elephant device I address counting control and control circuit shown in FIG. 8A; and FIG. 9 is another example of the present invention-Mu Peng Cheng, aa 丨, I have another shirt. Example I Amplification of the square circuit of the bus system ----------- · t (Please read the precautions on the back before filling this page) Block The system is equipped with a separate video processing block, a watt tile output multiplexer, a control circuit, and printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. A detailed description is provided. Active line sensors (eight ⑶) Each package is useful for the construction of the typical dual polysilicon active pixel sensor of the prior art, not shown in Figure 1. In FIG. 1, each pixel 50 has a shutter 60, which has an output sequence 53 configuration: it is a source follower. The source follower is $ 53 to drive subsequent signal conditioning circuits, such as the cross-correlation double sampling circuit (CDS)%. The gain obtained through a source follower 53 is less than i. If the source k mover and fixed gain at the pixel position of 50 are set, other pixels and individual source movers in the same row may or may not have the same gain. This technology relies on all standards of the array -12- this paper size standard (α ^^^ 1〇χ 297 public issued ^-order ... I I--___B7 V. Description of the invention (10: ET: Wafer processing has the same threshold value. It is not uncommon for the operating period to vary by _ millivolts. = Technology ^ Wang moving pixel 50 includes shutter 60 and transmission shutter a. The second to: f electricity generation The charge is to the floating animation shooting node 52, which is Γ ::!: Indirect 5 6 of the follower 5 3. The output of F ε τ 5 3 is “to the% source supply rail VDD. The source is from The driver output is connected to the source 57 of the 2 access FET58. When the column access 酣 58 is selected, feT58 is turned on, allowing the output FET53 to connect to the load 18 and directly drive the CDS loop 55. Figure 2 shows According to the schematic diagram of the pixel 12 of the present invention, the 阙 値 variation between the pixels of the prior art is removed. All pixels 一 in a column or row are connected in parallel, for simplicity, only one pixel is shown. It is composed of any photosensitive device 10 The pixel 12 is coupled to the FET 15 to isolate the pixel from the readout loop. Qing 15 is a differential input pair I of the operational amplifier 3G including the FET 24. For simplicity, in Figure 2, the amplifier circuit 30 is configured as a positive feedback-body shaping gain amplifier. The feedback path 32 connects the amplifier I output to input 17, the input of this example is the gate of the FET 24. Amplifier 0 can be configured to have any operational amplifier configuration with increasing i, complete difference input or depending on the application. The fixed gain of amplifier 30 can avoid the gain change of the previous technology. The output of the integrated integrated gain amplifier is connected to the cross-correlation double sampler. (CDS), CDS is used to remove any fixed style noise of video. The current source 20 including FET 22 has its source connected to the power supply VDD and its non-polarity connected to the differential input sources of FETs 15 and 24. 13- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm A7 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (11) Fortunately ^ FET 15 and 24 drain connection To the current path formed by the FETs 26 and 28. The gates of TΓPT and 28 are connected in common and are connected to the input FE15'.p. <Source 18. The sources of FETs 26 and 28 are connected to the negative power source VCC . P E Ding 9 and Zunji 30 are differential pair outputs, and are connected to cds 34. & FET 15 can be N-channel or P-pass FET if necessary. Pixel 80 can be a light gate or a photodiode. Figure 3. "&quot; is a detailed illustration of the pixel 12 of the active line sensor shown in Fig. 2. In the male known example, the shutter 76 is used. The selection of the sensing node 72 and the re-energization are controlled by the FET 76. Such an active line sensor pixel eliminates the prior art V &lt; select / access FET 58. All bias signals and control signals are supplied from the periphery of the pixel array. The pixels can be operated in the following manner. With an N-type substrate, the substrate is biased to a maximum positive potential, such as 5.0 volts. The shutter 70 is preferably a layer of polycrystalline silicon and is biased to an integration level (e.g., 0.0 volts). The area 80 under the shutter 70 is exhausted and when light hits the immediate area, the area will collect (integrate) the carriers generated by the photons. The shutter is biased to 5.0 volts and no carriers generated by photons will be collected during the integration due to being biased to the same% position of the substrate. The shutter 72 is biased by selecting and controlling the FET 76 with a reset / selection control signal. In this configuration, the control FET 76 is a P-channel FET, which is selected by a negative signal, such as 0. 0 volts, relative to the substrate. During the selection of the integrating FET 76, the shutter is biased by a copy / select bias (preferably 5.0 volts). The pixel is read after a predetermined integration period. Reading pixels is preferably achieved in the following manner. Reset / selection control changed to -14- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) '---

494448 A7 B7 V. Description of the Invention (l2) 2.5 Volts, causing the area under the shutter 72 to be exhausted and the background level to be read. The reset / select FET 76 is turned off by setting the reset / select control to 5.0 volts. The potential of the shutter 70 is removed, which is 5.00 volts in this example. The reading of the signal will occur when the charge generated by the collected photons is transferred from the lower region of the shutter 70 to the lower region of the shutter 72. The transferred photon generates a charge to regulate the gate of the input FET 15 in accordance with the collected amount. Fixed pattern noise (FPN) can be removed from the video information using the CDS circuit 34. The first sample applied to the CDS circuit was the background level. The signal information is then applied to the CDS. The difference between the two signals provides a signal without fixed pattern noise. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Figure 4 is a schematic diagram of a pixel array according to the present invention. Multiple pixels 90a, 90b, 90c form the first row of the array, and similar rows 92a-c and 94a-c complete the array. Within each row, the pixels are connected in parallel with their output FETs. This combination forms the first pair of differential input pairs of the operational amplifier 30. In all other respects, the amplifiers 30a, 30b, and 30c are identical to those of FIG. Each amplifier 30 is connected to the CDS 34a, 34b, and 34c, respectively. The outputs of the CDS 34a, b, and c are connected via row selection switches 96a, 96b, and 96c, and the common terminal is connected to the output buffer 98. The output buffer 98 can be a source follower, or it can be more complicated according to the needs of specific applications. Signal conditioner. As discussed earlier, industrial and technological imaging applications require significantly higher performance and functionality than consumer imaging products typically require. In particular, many of these applications require high readout speeds for video rates, or even faster imaging without sacrificing any image quality. One of the advantages of the present invention is to provide high-speed confluence on the board. -15- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 494448 A7 B7 ___ 5. Description of the invention (Π) Row system 200 or PVS A bus that allows pixel rates to exceed previous single CCD or APS device rates and other previous analog bus rates. This bus system 200 combines CMOS sensors with highly parallel technology for each row of amplifiers, providing functions and high-speed performance required for scientific and industrial applications. This increase in speed can be achieved without increasing power consumption, while maintaining full video bandwidth even at higher speeds. In addition, the present invention can eliminate the picking up of common node noise by using a completely different process. Further, high-speed, low-noise, low-power analog PVS buses use standard sequential or random access decoders to select a particular row. In addition to selecting one row, the bus system 200 has additional loops to preselect the next multiple rows in the parallel access sequence. The number of rows to be selected can be enlarged to meet the needs of the application. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling out this page). With particular reference to FIG. 7A, a high-speed and low-noise bus system 200 according to a specific embodiment of the present invention will be described. 1) is a schematic diagram of the imager 202 (1), but the bus system 200 can be used for many different types of devices, such as video crosspoint switches, and for many different types of applications. In this specific embodiment, the imager 202 (1) includes a pixel array 204 with multiple rows of 206 (l) -206 (n) and multiple columns of 208 (l) _2008 (n) together with an image processing ring Path, as previously described with reference to Figures 2-4. A selective cross-correlation double sampling (CDS) circuit 210 is coupled to the ends of the rows 206 (l) -206 (n) in this example. Although the bus system 200 (1) is coupled to the ends of each row 206 (l) -206 (n) of the array 204 in this particular example, the bus system 200 (1) may also be coupled to other locations, such as to an array Each column of 204 ends at 208 (l) -208 (n). The multiplexer 212 is coupled to one of the ends 206 (l) -206 (n) of each row of the array 204, but the multiplexer 212 can be coupled to other positions and to other materials. -16- This paper standard applies to the Chinese National Standard (CNS ) A4 specification (210X297 mm) 494448 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, A7 B7____ V. Description of Invention (14) Source. In this specific embodiment, the multiplexer 212 includes a plurality of multiplexing buses 214 (1) -214 (4) and 216 (1) -216 (4), a plurality of switches 218 (1), 218 (8) And pre-selection or control circuit 220, but the multiplexer 212 may be made of other components. The multiplexer 212 selects multiple rows 206 (1) -206 (n) or multiple columns 208 (l) -208 (n) of the array 204, and then simultaneously multiplexes from these rows 206 (l) Signals of -206 (n) or columns 208 (l) -208 (n) to multiplexed buses 214 (1) -214 (4) and 216 (1) -216 (4). In particular, in this specific embodiment, each row of the array 204 is coupled to a plurality of multiplexing buses 214 (1) -214 (4) and 216 (1) via the CDS circuit 210. -216 (4). There are four pairs of multiplexed buses 214 (1), 216 (1); 214 (2), 216 (2); 214 (3), 216 (3); and 214 (4), 216 (4); Multiplexed video buses are coupled to the rows of arrays 206 (1) -206 (4), but the total number and type of buses and the number of buses coupled to each row or column of array 204 can be changed as needed or as scheduled . In this particular embodiment, a one-to-multiplex bus is coupled to each row of the array to allow for differential processing. The switches 218 (1) -218 (8) are each coupled to one of the rows 206 (1) -206 (4) of the array 204 and the multiplexed buses 214 (1) -214 (4) and 216 (1) -216 (4) One room. Each switch 218 (1) .- 218 (8) has an open position and a closed position. In the open position, switches 218 (1) -218 (8) move the rows 206 (l) -206 (n) of array 204 from multiplexing buses 214 (1) -214 (4) and 216 (1) -216 ( 4) Disconnect; and in the closed position, switches 218 (1) -218 (8) couple rows 206 (1) -206 (4) to multiplex bus 214 (1) -2H (4) ) And 216 (1) -216 (4) 〇-17- Zhang scale is applicable to China National Standard (CNS) A4 specification (210 x 297 mm) (Please read the note on the back S • Item before filling and writing this page ) Order --------- 494448 A7 B7___ V. Invention Description (15) (Please read the notes on the back before filling this page) Pre-selection circuit 220 (also shown in Figure 7B) is coupled to each Switches 218 (1) -218 (8), as well as controlling each switch 218 (1) -218 (8), are in open or closed position. Since the open and closed control circuits for controlling the switches are well known to those in the industry, the pre-selection circuit 220 will not be described in detail here. In this specific embodiment, the pre-selection circuit 220 includes a plurality of "OR" Bollinger logic function gates (Γ OR gates) 222 (l) -222 (n), each of which has four inputs and one output, but Other types of components with other numbers of inputs and outputs and other types of logic functions can also be used for the pre-selection circuit 220. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. A decoder 224 (also shown in FIG. 7B) with multiple inputs and multiple outputs is coupled to the pre-selection circuit 220. Many different types of decoders 224 can be used, such as a sequential decoder or a random decoder. The decoder 2 2 4 transmits the input signal to each OR gate 222 (l) -222 (n). The output of each OR gate 222 (1) -222 (n) is coupled to one of switches 218 (1) -218 (η); and based on the signal received through the inputs of OR gates 222 (l) -222 (n) It is determined that the signals from the outputs of the OR gates 222 (l) -222 (n) coupled to the switches 218 (l) -218 (n) will be open or closed switches 218 (l) -218 (n). In this specific embodiment, the decoder 2 2 4 and the pre-selection circuit are designed to couple multiple rows of the pixel array to different multiplexing buses 214 (1) -214 (4) and 216 (1) -216 ( 4). The output multiplexer 226 is coupled to each multiplexing bus 214 (1) -214 (4) and 216 (1) -216 (4), and is designed to match the configuration of the multiplexer 212. In this specific embodiment, the output multiplexer 216 (1) includes multiple multiplexing buses 214 (1) -214 (4) and 216 (1) -216 (4), and multiple switches 228 (1)- 228 (8) and a control circuit 230 (1), but the output multiplexer 226 can be used by other -18- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) &quot; 494448 A7 B7_ 5 、 Explanation (16) (please read the precautions on the back before filling this page). Switches 228 (l) -228 (n) remain closed, at least until signals from lines 206 (l) -206 (n) have changed the buses 214 (1) -214 (4) and 216 (1) of this particular example -216 (4). The timing of the output multiplexer 226 is generated by an external controller (not shown) such as an on-chip counter, a small shift register, or a controller. In this specific embodiment, the control circuit 230 (1) (also shown in FIG. 7C) includes multiple AND gates 232 (1) -232 (4), each of which has a pair of inputs and an output, but with other numbers of inputs Other types of components and outputs and other types of logic functions may also be used for the control circuit 230. The address counter 234 sends an input signal to each of the AND gates 232 (1) _232 (4). The output of each AND gate 232 (1) -232 (4) is coupled to one of the switches 228 (1) -228 (8); and based on the signal received through the inputs of the AND gates 232 (1) -232 (4), It is determined that the signals output from the AND gates 232 (1) -232 (4) will be open- or closed-circuit coupled to the switches 228 (1) -228 (8) of the AND gates 232 (1) -232 (4). In this example, the control circuit 2 3 0 (1) is used to select a signal from one row of the pixel array 204 206 (1), 206 (2), 206 (3), or 206 (4) at one time, but the control circuit 230 (1) Other components can be configured and controlled with other input signals. One or more signals 206 (1) -206 (4) are selected by one or more rows of the pixel array 204 at a time. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation. In this particular embodiment, the video processing circuit 236 is coupled to the output of the output multiplexer 226, but other types of processing circuits may be used. The video processing circuit 236 takes the difference video from two buses: 214 (1), 216 (1); 214 (2), 216 (2); 214 (3), 216 (3); and 214 (4), 216 ( 4) Coupling to video processing circuit 236 and providing gain, compensation chirp, filtering, and / or any other predetermined processing functions in a manner well known to those skilled in the art. -19- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 494448 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (I7) Another embodiment of the invention is an imager 202 (2) with a high-speed low-noise bus system 2000 (2). Figures 8A and 8B show how this particular embodiment is used to change the natural resolution of the imager. Since the imager 202 (2) and the bus system 200 (2) of FIG. 8A are the same as the imager 202 (1) and the bus system 200 (1) of FIG. 7A, the control circuit 23 (2) Except that, only the control circuit 230 (2) of FIGS. 8A and 8B will be described here. In FIGS. 8A and 8B, the control circuit 2 3 0 (2) includes a bit address counter 234 with multiple inputs and multiple outputs together with multiple AND gates 238 (1) -238 (4) and 24〇 (1) _24 〇 (4) and OR gates 242⑴_242 (4) and 244⑴_ 244 (sentences, each of which has a pair of input and an output node 5 connected to it. Since the control circuit for controlling the opening and closing of the switch is well known to the industry, the control circuit 230 (2 ) Will not be described in detail here. In this specific embodiment, the control circuit 23 (2) with the address counter 234 and the interpolation control signal 243 is configured to interpolate the pixels from the pixel array 204. The signals of lines 206 (l) -206 (n) are described in detail later. In this example, the address counter 234 sends an input signal to the control circuit 230 (2). The control circuit 23〇 (2) is coupled to the switch 228 ( 1) -228 (8), and based on the signal received by the control circuit 23〇 (2), the signal from the control circuit 230 (2) will open or close the switch 228 (1) -228 (8). The example provides line interpolation. Referring to FIGS. 7A-7C, by selecting 3 lines in advance, the line processing loop only needs to be at a quarter of the normal pixel reading rate ( One-bandwidth) drives the multiplexing buses 214 (1) -214 (4) and 216 (1) -216 (4). Only the demultiplexer is performed at the normal bandwidth. A processing circuit such as this is shown in Figure 2 The active line sensor technology described in -4 can be reduced in size and requires lower power. And because of the pixel array -20- this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) ------ ----- (Please read the notes on the back before filling out this page) Order V. Description of the invention (18) Only one row in the row 4 and the order 2 in the 206 are all the multiplexing points that are closed to this example. = 夕 工 汇流 # 214 (1 &gt; 214 (4) and 216 (1) -216 (4) have only four-wheel drive, because, only a quarter of the transmission gates need to be blocked, so it is used further In the present invention, the row selection order is maintained, and as the multi-imager requires, for example, as shown in Figure 6, post processing is required to reconstruct the original image. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs &amp; Another useful method for the parallel nature of 2G2 and the bus system is to select multiple lines at a time and find the average of the video image. This is possible. The reason is that the details of the row amplifiers in the processing loop of the pixel array 204 are exactly the same. When more than one row is selected at a time, the outputs from the various amplifiers try to drive each other, and the result is to obtain one or more signals. On average. This results in higher speed operation and a novel method of boxing or interpolation of pixels. The term boxing is used to group two or more pixels together. Higher-speed operation is due to two or more amplifiers driving the same video bus, resulting in twice the capacity (or more) of driving the same capacitance. Boxing is the result of combining two or more k numbers on the same bus 214 or 216 at the same time. The control circuit 23o (1) of the output multiplexer 226 (1) can be configured and coupled with two pairs of multiplexed buses 214 (1), 216 (1); 214 (2), 216 (2). 214 (3) '216 (3); and 214 (4), 216 (4) to the video processing circuit 236 for boxing. The multiple analysis capabilities of the bus status system 200 (1) can also be used to effectively increase the resolution by interpolation instead of reducing the resolution by just boxing as shown in Figures 8A and 8B. Figures 8A and 8B Imager 202 (2) -21 with bus system 200 (2) -21 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative 494448 A7 B7__ V. The description of the invention (19) is operated in the same manner as the imager 202 (1) with the bus system 200 (1) of Figs. 7A-7C, but using the control circuit of Figs. 8A and 8B 230 (2) makes row interpolation feasible. In this specific embodiment, the improvement in resolution is achieved by using the control circuit 230 (2) to selectively box adjacent signals between individual signals. In this way, the timing is to select the multiplexed buses 214 (1) and 216 (1) coupled to row 206 (1) for coupling to the video processing circuit 236 through the closed circuit of switches 228 (1) and 228 (2). And read signals. Secondly, row 206 (1) is selected sequentially, and the multiplexed buses 214 (2) and 216 (2) coupled to row 206 (2) are also selected through the closed-circuit selection of switches 228 (3) and 228 (4) for Coupled to video processing circuit 236. Reading the combined signal (boxing signal or average signal), and deselecting line 206 (1) by opening switches 228 (1) and 228 (2) will thus couple to the multiplexing bus of line 206 (1) Banks 214 (1) and 2 1 6 (1) are unlinked by video processing circuit 236 and only read from multiplexed buses 214 (2) and 216 (2) coupled to row 206 (2). In this way, for every two adjacent signals read, the third interpolated signal can be read, which effectively improves the resolution through interpolation. For example, an imager with a pixel array of 640 rows will have an effective resolution of 1279 pixels via interpolation; or an imager with a pixel array of 480 columns will have an interpolation resolution of 969 columns. In either case, for boxing or interpolation, row or column averaging is performed by the output multiplexer. Referring now to FIG. 9, a bus system 329 according to another embodiment of the present invention is provided with another output multiplexer, a control circuit, and a video processing block. The busbar system 200 (3) of FIG. 9 is the same as the busbar system 200 (1) shown in FIGS. 7A-7C or the busbar system 200 (2) shown in FIGS. 8A and 8B, but such a busbar system 200 ( 3) There is also a reordering multiplexer circuit 330. Re-22- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) &quot; 亀 ----------- install · --------- order --- -(Please read the notes on the back before filling this page)%

494448 5. Description of the invention (20) The sequencing circuit 330 is coupled to the output multiplexer circuit 226 of FIG. 9 and its function is the same as that of the output multiplexer circuit of FIG. 8A. The possible practical details of the reordering circuit 330 are shown in FIG. In particular, in this embodiment, the reordering circuit 330 is composed of switches, and the open relationship is implemented using a transmission gate 332 (u) as shown. The signals provided by the output multiplexers at nodes 226 and 227 can be controlled by the pixel sequencing logic device 342 to be switched into one or more of the video processing block circuits 343 (1-3). The details of the sequencing logic device 342 are not shown here, but it is obvious to those skilled in the art. The specific embodiment of the sequencing logic device 342 depends on the specific application and the predetermined sequencing of the signals. The control logic function provided by the sequencing logic device 3 4 2 combination reordering circuit 330 redirects signals to one or more locations. As for the signals at points 227 and 229 in FIG. 9, they can be redirected to the view of video processing block 34. 诏 i zoom in one or more of 342 (1-3). The difference signals are shown in Figs. 7A, 7B, 7C, 8A, 8B and 9, which can be described as signals for noise immunity and reference signals. A single terminal configuration or multiple input, output, and reordering buses can also be used for some applications. In this way, the basic concept of the present invention has been described, but it is obvious to those skilled in the art that the foregoing detailed description is for illustrative purposes only and is not restrictive. Although it is not explicitly stated here, it is obvious to those in the industry that many changes, improvements and modifications are intended. These changes, improvements, and modifications are intended to be used as a reminder only and are within the spirit and scope of the present invention. As such, the present invention is limited only by the scope of patent applications and their equivalents. (Please read the precautions on the back before filling this page) • t— n n- Patent application for Yinchuangyi, a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 23- 494448 No. 090101651. May) Meeting? 1st Article Correction / Correction / Supplement V. Description of the invention (2 as) Graphic component symbol description 5 Output node 10 Photosensitive device 12 Pixel 15 FET 17 Input 18 Load 20 Current source 22 FET 24 FET 26 FET 28 FET 30 operational amplifier 30a, 30b, 30c amplifier 32 feedback path 34 CDS circuit 34a, 34b, 34c CDS 50 pixels_-23a- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 494448 No. 090101651 Revised Page of Chinese Specification for Patent Application No. (May 91) A7 B7 V. Description of Invention (20b) 52 Floating Animation Node 53 Output FET 55 Interrelated Double Sampling Circuit (CDS) 56 Gate 57 Source 58 Column Access FET 60 shutter 62 transfer gate 70 shutter 72 sensing node 76 FET 80 imager 80 (1) -80 (4) sub-imager 82 (1) -82 (4) port 90a, 90b, 90c pixels_ 92a-c Line 94a-c line one 96a, 96b, 96c line selector switch-23b- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 494448 Amendment page of Chinese specification of patent application No. 090101651 (May 91) V. Invention Description (20c) 98 CMOS imager 100 with parallel and parallel amplifier 102 common video bus 120 video switch 140 capacitive load 200 on-board high-speed bus system 200 (1) high-speed and low-noise E-bus system 200 (2) high-speed Low Noise Bus System 200 (3) Bus System 202 (1) Imager 202 (2) Imager 204 Pixel Array 206 Rows 206 (l) -206 (n) Rows 208 (1 &gt; 208 (η) Column_ 210 Selective cross-correlation double sampling (CDS) circuit 212 Multiplexer 214 Bus-23c- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 494448 A7 B7 Patent Application No. 090101651 Revised page of the Chinese manual for the case (May 91) V. Description of the invention (20d) 214 (1) -214 (4) Multiplex bus 216 Bus 216 (1) -216 (4) Multiplex bus 218 (l) -218 (n) switch 220 Pre-selection or control circuit 222 (l) -222 (n) `` OR '' Forest logic function gate 224 decoder 226 output multiplexer 226 (1) output multiplexer 227 node 228 (l) -228 (n) switch 229 node 230 control circuit 230 (1) control circuit 230 (2) control circuit_ 232 (1) -232 (4) AND gate 234 address counter-236 video processing circuit-23d- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 494448 A7 B7 patent No. 090101651 Revised page of the Chinese specification of the application (May 91) V. Explanation of the invention (20e) 238 (1) -238 (4) AND gate 240 (1) -240 (4) AND gate 242 (1) -242 ( 4) OR gate 243 interpolates control signals 244 (1) -244 (4) OR gate 329 bus system 330 reorder multiplexer circuit 332 (1-6) transmission gate 340 video processing block 342 pixel sorting logic device 342 ( 1-3) Video amplifier 343 (1-3) Video processing block circuit-23e- This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm)

Claims (1)

Leaf Scope of patent application Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics 1.-A kind of transmission from most signal buses, the κ bus system includes: # 出 〈Bus bus is a plurality of parallel signal buses; and a control system, It is used for multiplexing or two or more signal streams to ^ bis h to multiple signal buses and more than one bus, and in one or two han ^ ^ was resolved to multiplex to turn out the signal is substantially charged Multiple # rules, allow ^^ on each of the two or two of the buses. Last 2 · If the patent application scope of the bus system, it is based on the signal from two or more of the multiple signal bus 』# buses are substantially simultaneously synchronized to the output, and so on: The signals on the rows are averaged together to provide boxing. "Tiger 3. If you apply for a bus system on page &quot;, the control system, the system, and the system respectively couple each signal from each of the multiple buses to the output, and Signal flow and adjacent paired 仏 streams &lt; each signal is coupled to the output at the same time to provide interpolation. 4. If the patent application scope item i bus system, one of the multiple address buses is coupled to each The majority signal stream. 5. If the busbar system of item i of the patent application scope, one of a plurality of signal buses is coupled to each signal stream of the majority signal stream for differential processing. 6 · For example, the bus system of the scope of application for item i, where the control system includes: a decoder; -24- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------ --Order --------- line (Please read the phonetic on the back? Matters before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494448 A8 B8 C8 D8 The control circuit is coupled to the Encoder; and a plurality of first switches which are coupled to the first control circuit, and each of the plurality of first switches is also coupled between one of the plurality of signal streams and one of the plurality of signal buses. Item of the bus system, wherein the decoder is a sequential decoder. 8. For example, the bus system of the sixth item of the patent application, wherein the decoder is a random decoder. 9. If the patent application of the sixth item of the bus, The system, wherein the control system further comprises: a bit counter, which is coupled to the decoder; a second control circuit, which is coupled to the address counter; and most second switches, which are coupled to the second control circuit, each The majority second open relationship is coupled between one of the plurality of signal buses and the output. 10. An imager comprising: a plurality of signal streams from a source; a plurality of parallel signal buses; an output; and a A control system for multiplexing signals from two or more signal streams of most signal streams to two or more of a plurality of signal buses, and Before the signal is demultiplexed to output, the signal is allowed to substantially charge each of the two or more buses of the multiple signal buses. -25- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ install -------- order --------- line (please read the precautions on the back before filling this page) A8 B8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, it is called the imager of item 10 of the patent scope, where the control system is composed of two or more signal buses from multiple signal buses. The signals are coupled to the output at the same time and the signals on these signal sinks are averaged together to provide boxing. 12. The imager as claimed in item 10 of the patent application range, wherein the control system divides each signal from each of the multiple signal buses to 5 fortunately, and separates the signals from most of the signal flows and postal signals. Each signal in a pair of sharp currents is simultaneously coupled to the output to provide interpolation. I 13. The imager of claim 10, wherein one of the plurality of signal buses is coupled to each of the plurality of signal buses. Note 14. If the imager of the scope of patent application No. 10, one of a plurality of signal buses is coupled to each signal stream 2 of a plurality of signal streams for differential processing. a The imager ... control system of claim 10 includes: a decoder; a first control circuit coupled to the decoder; and a plurality of first-switches coupled to the first control circuit, Each of the plurality of first switches is also connected to the majority of the signal flow—and one of the plurality of signal hiding streams. 16. For example, Cheng Jun, Gao Jian, and Gao Zhiming of the scope of application for patents, among them, the child decoder is a sequential decoder. 17. The imager according to item 15 of the patent application scope, wherein the de-mapping device is a production decoder. . i (Please read the notes on the back before filling this page) -26- 8888 ABCD patent application scope 18. If step i of the patent application scope is included; J imaging consultation, where the control :: address counter, which is connected to the decoder; the second "" way "is coupled to the address counter ; And the second switch in the evening, its _ 摇 人 教 #, the system is exposed. To the second control circuit, the majority-open relationship is coupled between the two. One of the evening buses and the output 19. If applied . The scope of the patent is 10. The imager further includes a video processing circuit that is coupled to the wheelout. 20 · If the scope of the patent application is 0th member imager, the video processing circuit k is used for differential processing. 21 · A A bus system that transmits signals from most 俨%, clouds, and a few yttrium bleeds (signal-to-output). The child bus system includes: multiple signal buses, which are coupled to the majority of signal streams; The first switch, each of which is related to Zhao Dibei, and the number of open loops, is coupled to the majority of the five tigers-between the multiple signal streams and the multiple hidden signal banks; most of the second switches, each of which is I π ^ A few switches on the side Is coupled between one of a plurality of stray currents and the turnout; and a 4-control system, which is connected to the first and second switch systems, the majority of the first switch, the first switch, and the second switch. Two or more switches are used to couple people from two or more of the majority of signal flows, δ Dream Fi, ^ t, ,, and the next one to the multiple signals # 汇 汇, 棑, and closed circuit diagnosis Either one of the second switch or the above switch turns the signal to the wheel: before the evening, the signal is allowed to substantially charge multiple signal buses, -27- (Please read the precautions on the back before filling this page } ▼ Shang -------- Order --------- line P Printed Paper Standard Outline (CNS) A4 Specification (21〇, 297 mm) 4V4448 A8 B8 C8 D8 3. Each of the above buses for patent application. 22. For the busbar system under the scope of patent application No. 21, in which the control system is based on the signals from two or more busbars in the Ueda Park No. area being substantially simultaneously smoothed to rotation. The signals on these buses are averaged together to provide packing. 『23. For example, the patent application No. 21jf bus system, wherein the control system is to 'couple to each output' each signal from each of a plurality of signal buses and to couple the majority of signal streams and adjacent pairs Each signal of the signal flow is smoothed to the output to provide interpolation. 24. In the case of the busbar system of claim 21, one of the plurality of busbars is coupled to each of the plurality of signal streams. For example, the bus system of the scope of application for patent No. 21, and many of them are used as the bus-to-bus system. Each stream of the signal stream from Hanhe to most of the signals is used for differential processing. See the bus system of item 21 in the scope of patent application, where the control system includes: No. Chain (please read the notes on the back before filling out this page) Male — — IIII · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative A decoder; a first control circuit coupled to the switch; the decoder and most first address counters coupled to the de-asser; and a second control circuit coupled to the bit The address counter is coupled to a plurality of second switches. 27. The bus system of claim 26, wherein the decoder is a sequential decoder. -28- This paper size applies to the Chinese National Standard (CNS) A4 specification (21 () χ Norwegian public love A8 Β8 C8 D8 of the Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperative prints the scope of patent application 28. %,, &Lt; Bus system, wherein the decoder is a random access decoder. 29 · —A method for transmitting signals, including: Xi Gonghua 'blame two or more of the multiple signal buses Buses; and for demultiplexing signals to 出 出 义 ®, the signal is allowed to charge substantially two or more of each of the multiple signal buses. 30 · If Application · Patent Scope No. Fourth, Wanfa, further including the fact that in the future = two rows <two or more neighboring signal bus signals are substantially simultaneously converted to the output, and the signals on these signal buses are averaged together for boxing. 31 According to the method of the scope of patent application No. 29, from each of the multiple signal buses: to the output, and to clip the Baixi material factory station, 〇 on the knife to open the rhyme and will come from multiple And signal flow simultaneously adjacent respective signals is coupled to the output port h -29- is carried out within this paper applies China National Standard Scale (CNS) A4 size (210 X 297 mm)