486777 6853twf.doc/002 A7 __ B7 五、發明說明（f ) 本發明是有關於一種半導體元件之製造方法，且特別 是有關於一種介電層之製造方法。 在半導體的製造過程中，導電結構之間通常是以介電 材料作爲隔離導電結構的絕緣體。其中，導電結構例如是 內連線(Interconnect)、聞極或是介層插塞(piUg)。隨著半導 體兀件的線覓不斷的縮小，相鄰之導線的間距亦隨之縮 小，因此’一般用於介電層的材料爲具有低介電常數之介 電材質’例如含氟玻璃(Fluorosilicate Glass，FSG)，以提高 介電層之絕緣功效。 而在導體結構上形成低介電常數之介電層，以高密度 電漿化學氣相沈積法（High Density Plasma-Chemical Vapor Deposition ’ HDP-CVD)形成，不但可降低反應所需之溫度， 以降低製程之熱預算，且可使此介電層形成較爲緻密，以 提高其絕緣之功效。然而，使用高密度電漿化學氣相沈積 法所形成介電層，電漿中所存在之電荷易聚集於導線結構 之周圍，而使得導線結構之間產生不正常導通，甚至電荷 將沿著導線而聚集於晶圓中導體結構例如源極/汲極周圍或 兩閘極結構之周圍，而使得導體結構間形成不正常導通。 習知解決高密度電槳化學氣相沈積法所造成電荷附著 在導線結構之問題，係利用在導線結構上先以電漿化學氣 相沈積法（Plasma-Enhanced Chemical Vapor Deposition， PECVD)形成一層氧化層，其中此電漿化學沈積法之溫度 約爲400°C，然後，再於此氧化層上以高密度電漿化學氣 相沈積法形成介電層，由於此氧化層之遮蔽，在後續進行 3 本紙張尺度適用中國國家標準（CNS)A4夫見格（210 X 297公釐） ---------------- (請先閱讀背面之注意事項再填寫本頁) 訂， 線· 經濟部智慧財產局員工消費合作社印製 486777 6853twf.doc/002 A7486777 6853twf.doc / 002 A7 __ B7 V. Description of the Invention (f) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a dielectric layer. In the semiconductor manufacturing process, dielectric materials are often used as insulators to isolate conductive structures between conductive structures. Among them, the conductive structure is, for example, an interconnect, an interconnect, or a piUg. As the wire search of semiconductor components continues to shrink, the distance between adjacent wires also decreases. Therefore, 'the material generally used for the dielectric layer is a dielectric material with a low dielectric constant', such as Fluorosilicate Glass (FSG) to improve the insulation effect of the dielectric layer. A dielectric layer with a low dielectric constant is formed on the conductor structure and formed by a high density plasma chemical vapor deposition method (High Density Plasma-Chemical Vapor Deposition 'HDP-CVD), which can not only reduce the temperature required for the reaction, but also Reduce the thermal budget of the process, and make the dielectric layer denser to improve the effectiveness of its insulation. However, using a high-density plasma chemical vapor deposition method to form a dielectric layer, the charges existing in the plasma tend to gather around the wire structure, causing abnormal conduction between the wire structures, and even the charge will follow the wire. And it is gathered around the conductor structure in the wafer, such as around the source / drain or around the two gate structures, so that abnormal conduction is formed between the conductor structures. It is known to solve the problem of the charge attached to the wire structure caused by the high-density electric paddle chemical vapor deposition method. The plasma structure is firstly formed by plasma chemical vapor deposition (PECVD) on the wire structure. Layer, in which the temperature of the plasma chemical deposition method is about 400 ° C, and then a dielectric layer is formed on the oxide layer by a high-density plasma chemical vapor deposition method. Due to the shielding of this oxide layer, 3 This paper size is applicable to China National Standard (CNS) A4 Fu Jiange (210 X 297 mm) ---------------- (Please read the precautions on the back before filling this page ) Order, printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 486777 6853twf.doc / 002 A7
五、發明說明（2 ) 筒密度電漿化學沈積法時，可減少電漿中之電荷聚集於導 線結構與晶圓中之導體結構周圍，然而，以習知之方法仍 無法完全避免電荷聚集之問題。此外，習知形成氧化層之 方法，在晶圓之周圍所沈積之氧化層較不均勻，且於噴管 下方之晶圓因噴管之遮蔽亦使此處之氧化層沈積較不均 勻，因而使得氧化層更無法發揮其防止電荷聚集之功能。 因此本發明提供-一種介電層之製造方法，可避免於利 用高密度電漿氣相沈積法時，電荷聚集於導線結構與晶圓 中之導體結構周圍，而導致導體結構產生不正常導通之現 象’且可使在晶圓邊緣與噴管下方之晶圓所形成之襯層較 爲均勻。 本發明提出一種介電層之製造方法，此方法係在半導 體晶圓上形成數個導線結構，之後，將半導體晶圓移入一 反應室，以形成襯層於半導體晶圓上並覆蓋住數個導線結 構’其中形成襯層是在低溫之條件下，先以反應室上方之 中央噴管由半導體晶圓之正上方向半導體晶圓輸入矽曱 烷，再由反應室周圍之數個噴管由半導體晶圓邊緣向半導 體晶圓中央輸入矽甲烷/氧，以形成較均勻且密度較高之襯 層，之後，以高密度電漿化學沈積法形成介電層於襯層上。 本發明形成密度較高之襯層於導線結構上，因此，於 後續進行高密度電漿化學氣相沈積法時，可有效防止電荷 聚集於導線結構周圍與晶圓中之導體結構周圍，而造成導 體結構間形成不正常導通之現象。 本發明先以反應室上方之中央噴管由半導體晶圓上方 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------- (請先閱讀背面之注意事項再填寫本頁) · 線· 經濟部智慧財產局員工消費合作社印製 486777 6853twf.doc/002 A7 R7 經濟部智慧財產局員工消費合作社印製 五、發明說明（,） 向半導體晶圓輸入矽甲烷，再由反應室周圍之數個噴管由 半導體晶圓之周圍向半導體晶圓中央輸入矽甲烷/氧，可在 整個晶片上形成均勻之襯層。 本發明形成之襯層溫度條件較習知方法低，因此可降 低製程之熱預算。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂’ 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖所示，爲依照本發明一較佳實施例之介電層之 製造流程剖面圖：以及 第2圖所示，爲依照本發明一較佳實施例之沈積過程 中之機台上視圖。 圖示標記說明= 1〇〇 :半導體晶圓 102 :導線結構 104 :襯層 106 :介電層 200 :晶片 204 :噴管 206 :中央噴管 實施例 第1圖所示，其繪示爲依照本發明一較佳實施例之介 電層之製造流程剖面圖。 5 ----------------- (請先閱讀背面之注意事項再填寫本頁) . --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 486777 6853twf.doc/002 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（^) 第2圖所示，其繪示爲依照本發明一較佳實施例之沈 積過程中之反應室上視圖。 請參照第1圖’首先，提供一半導體晶圓100，其中 此半導體晶圓1 〇〇上已形成有半導體元件（未繪示），例 如閘極結構、汲極/源極等，之後，於半導體晶圓100上形 成數個導線結構102。 乂 接著，在半導體晶圓100上形成襯層104並覆蓋住導 線結構102，而形成襯層104係於一反應室中形成如第2 圖所示，在低溫之條件下例如溫度約攝氏150度至攝氏400 度，先以反應室上方之中央噴管206由半導體晶圓100正 上方向半導體晶圓100輸入第一反應氣體，其中第一反應 氣體例如爲矽甲烷，其流量例如爲大於l〇sccm，之後， 再以反應室周圍之數個噴管204由半導體晶圓1〇〇之邊緣 向半導體晶圓100中央輸入第二反應氣體，其中第二反應 氣體例如爲矽甲烷/氧，且矽甲烷/氧之流量例如爲45/30 seem，以形成富含矽氧化材質之襯層1〇4於半導體晶圓100 上，而此襯層104之折射率例如爲1.6至1.8,且此襯層104 之厚度例如爲600埃至800埃。 所形成之襯層104覆蓋住半導體晶圓100與導線結構 102，且因襯層104之折射率約爲ι·6至1.8，使襯層104 之密度較高，因此，可有效避免於後續進行高密度電漿化 學沈積法時，電荷聚集於導線結構上而導致導線結構間與 晶圓之導體結構間形成不正常導通之現象。此外，因先以 中央噴管206對半導體晶圓1〇〇輸入矽甲烷，因此，可避 6 (請先閱讀背面之注咅？事項再填寫本頁) —麟 1 - 線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 486777 A7 B7 6853twf.doc/002 五、發明說明（夕） 免習知之方法中會在晶圓邊緣與中央噴管所遮蔽之處產生 不均勻之問題。 (請先閱讀背面之注音3事項再填寫本頁) 之後，以高密度電漿化學氣相沈積法形成介電層106 於襯層104上，以做爲內金屬介電層（Intei-Metal Dielectrics)，而介電層10ό之材質例如爲含氟玻璃。 以本發明形成襯層104,由於所形成之襯層104之折 射率約爲1.6至1.8，使得襯層104之密度較高，因此，於 後續進行高密度電漿化學氣相沈積法時，可有效防止電荷 聚集於導線結構102周圍與半導體晶圓100中之導體結構 周圍，而造成不正常導通之現象。 本發明於形成襯層104時，先以反應室上方之中央噴 管206由半導體晶圓100正上方對半導體晶圓100輸入矽 甲烷，再以反應室周圍之數個噴管204由半導體晶圓100 邊緣向半導體晶圓100中央輸入矽甲烷/氧，可使襯層104 均勻形成於整個晶片上，而可避免習知技術中，於晶圓周 圍與噴管下方之晶圓位置之氧化層有不均勻之情形。 本發明形成之襯層溫度條件比習知方法低，因此可降 低製程之熱預算。 經濟部智慧財產局員工消費合作社印製 雖然本發明以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技術者，在不脫離本發明之精神 和範圍內，當可做些許之更動與潤飾，因此本發明之保護 範圍視後附之申請專利範圍所界定者爲準。 7 本紙張尺度適ϋ國國家標準（cns)A4規格（210 X 297公釐）V. Description of the invention (2) In the case of tube density plasma chemical deposition method, the charge accumulation in the plasma can be reduced around the conductor structure and the conductor structure in the wafer. However, the problem of charge accumulation cannot be completely avoided by conventional methods. . In addition, in the conventional method for forming an oxide layer, the oxide layer deposited around the wafer is relatively uneven, and the wafer below the nozzle is also unevenly deposited due to the shielding of the nozzle, so As a result, the oxide layer cannot perform its function of preventing charge accumulation. Therefore, the present invention provides a method for manufacturing a dielectric layer, which can avoid the accumulation of charges around the conductor structure and the conductor structure in the wafer when the high-density plasma vapor deposition method is used, resulting in abnormal conduction of the conductor structure. Phenomenon 'and can make the liner formed by the wafer edge and the wafer below the nozzle more uniform. The invention provides a method for manufacturing a dielectric layer. This method forms a plurality of wire structures on a semiconductor wafer, and then moves the semiconductor wafer into a reaction chamber to form a liner on the semiconductor wafer and cover the plurality of semiconductor wafers. The wire structure 'in which the lining layer is formed under low temperature conditions, the central nozzle above the reaction chamber is first used to feed the silicon wafer from the semiconductor wafer directly to the semiconductor wafer, and then several nozzles around the reaction chamber are used to The edge of the semiconductor wafer is inputted with silicon methane / oxygen to the center of the semiconductor wafer to form a more uniform and denser lining layer, and then a dielectric layer is formed on the lining layer by a high-density plasma chemical deposition method. The invention forms a high-density liner layer on the wire structure. Therefore, when a high-density plasma chemical vapor deposition method is subsequently performed, charges can be effectively prevented from accumulating around the wire structure and around the conductor structure in the wafer, resulting in There is an abnormal conduction between the conductor structures. In the present invention, the central nozzle above the reaction chamber is used above the semiconductor wafer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------- ( Please read the precautions on the back before filling out this page) · Line · Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 486777 6853twf.doc / 002 A7 R7 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The silicon wafer is input to the semiconductor wafer, and then a number of nozzles around the reaction chamber are used to input silicon methane / oxygen from the periphery of the semiconductor wafer to the center of the semiconductor wafer to form a uniform lining on the entire wafer. The temperature condition of the liner formed by the present invention is lower than that of the conventional method, so the thermal budget of the process can be reduced. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible ', a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: Figure 1 shows Is a cross-sectional view of a manufacturing process of a dielectric layer according to a preferred embodiment of the present invention: and FIG. 2 is a top view of a machine during a deposition process according to a preferred embodiment of the present invention. Explanation of figure marks = 100: semiconductor wafer 102: wire structure 104: liner 106: dielectric layer 200: wafer 204: nozzle 206: central nozzle embodiment shown in FIG. 1, which is shown in accordance with A cross-sectional view of a manufacturing process of a dielectric layer according to a preferred embodiment of the present invention. 5 ----------------- (Please read the notes on the back before filling in this page). --- The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 486777 6853twf.doc / 002 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (^) Figure 2 shows the deposition process according to a preferred embodiment of the present invention Top view of the reaction chamber. Please refer to FIG. 1 'First, a semiconductor wafer 100 is provided, in which semiconductor elements (not shown), such as a gate structure, a drain / source, etc., have been formed on the semiconductor wafer 1000. A plurality of wire structures 102 are formed on the semiconductor wafer 100.乂 Next, a liner layer 104 is formed on the semiconductor wafer 100 and covers the wire structure 102, and the liner layer 104 is formed in a reaction chamber. As shown in FIG. 2, under low temperature conditions, such as about 150 degrees Celsius To 400 degrees Celsius, a central nozzle 206 above the reaction chamber is first used to input a first reaction gas from the semiconductor wafer 100 directly above the semiconductor wafer 100. The first reaction gas is, for example, silicon methane, and the flow rate is, for example, greater than l0. sccm, and then use a number of nozzles 204 around the reaction chamber to input a second reaction gas from the edge of the semiconductor wafer 100 to the center of the semiconductor wafer 100, where the second reaction gas is, for example, silicon methane / oxygen, and silicon The flow rate of methane / oxygen is, for example, 45/30 seem to form a silicon-rich lining layer 104 on the semiconductor wafer 100, and the refractive index of the lining layer 104 is, for example, 1.6 to 1.8, and the lining layer The thickness of 104 is, for example, 600 angstroms to 800 angstroms. The formed lining layer 104 covers the semiconductor wafer 100 and the wire structure 102, and the refractive index of the lining layer 104 is about ι · 6 to 1.8, which makes the density of the lining layer 104 higher. Therefore, it can be effectively avoided in subsequent processes. In the high-density plasma chemical deposition method, charges are accumulated on the wire structures, resulting in abnormal conduction between the wire structures and the conductor structures of the wafer. In addition, since silicon dioxide is input to the semiconductor wafer 100 through the central nozzle 206, 6 can be avoided (please read the note on the back? Matters before filling out this page) — Lin 1-Line · This paper size applies China National Standard (CNS) A4 specification (210 X 297 mm) 486777 A7 B7 6853twf.doc / 002 V. Description of the invention (Evening) In the conventional method, there will be inconsistencies between the edge of the wafer and the area covered by the central nozzle. The problem of uniformity. (Please read Note 3 on the back before filling this page.) Then, a high-density plasma chemical vapor deposition method is used to form a dielectric layer 106 on the liner 104 as the inner metal dielectric layer (Intei-Metal Dielectrics). ), And the material of the dielectric layer 10 is, for example, fluorine-containing glass. The liner 104 is formed according to the present invention. Since the refractive index of the liner 104 formed is about 1.6 to 1.8, the density of the liner 104 is relatively high. Therefore, in the subsequent high-density plasma chemical vapor deposition method, Effectively prevent charges from accumulating around the wire structure 102 and the conductor structure in the semiconductor wafer 100, causing abnormal conduction. When forming the liner 104 in the present invention, firstly, the central nozzle 206 above the reaction chamber is used to input the silicon methane from the semiconductor wafer 100 directly above the semiconductor wafer 100, and then the semiconductor wafer is passed through the nozzles 204 around the reaction chamber. 100 The edge of the silicon wafer 100 is fed with silicon dioxide / oxygen to the center of the semiconductor wafer 100, so that the liner 104 is uniformly formed on the entire wafer, and it is possible to avoid the oxide layer around the wafer and the position of the wafer below the nozzle in the conventional technology Uneven situation. The temperature condition of the liner formed by the present invention is lower than the conventional method, so the thermal budget of the process can be reduced. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Although the present invention is disclosed above in a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this technology should not depart from the spirit and scope of the present invention. With a few changes and retouching, the scope of protection of the present invention is determined by the scope of the attached patent application. 7 This paper is sized for the national standard (cns) A4 (210 X 297 mm)