TW486746B - Method of forming a metal wiring in a semiconductor device - Google Patents

Method of forming a metal wiring in a semiconductor device Download PDF

Info

Publication number
TW486746B
TW486746B TW89123263A TW89123263A TW486746B TW 486746 B TW486746 B TW 486746B TW 89123263 A TW89123263 A TW 89123263A TW 89123263 A TW89123263 A TW 89123263A TW 486746 B TW486746 B TW 486746B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
forming
copper
layer
plasma processing
Prior art date
Application number
TW89123263A
Other languages
Chinese (zh)
Inventor
Sung-Gyu Pyo
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW486746B publication Critical patent/TW486746B/en

Links

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

There is disclosed a method of forming a metal wiring in a semiconductor device using copper (Cu) as metal wiring material. The method according to the present invention removes, by a remote plasma and/or chamber plasma process, the interfacial impurity such as fine oxide, nitride, etc. existing on the surface of a barrier metal layer after the barrier metal layer is formed in an ultra-fine damascene pattern, when Cu is buried into an ultra-fine wiring structure into which Cu is difficult to be buried by PVD or electroplating method. Thus, the present invention can improve the adhesion characteristic of Cu.

Description

486746 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 B7 五、發明說明(/ ) 發明背景: 發明技術領域: 本發明係有_-種在-铸體裝置上形成金屬線路的 方法’尤指-種藉由化學氣相沈積(CVD)製程方法而 良銅之黏著特性之在-半導觀置上形成金屬線路的方法。 習知先前技藝之說明: 通常’在-半導體裝置上形成金屬線財,銅薄膜的炫 點高於銘薄膜的溶點。由於銅薄膜較耐電致遷移 (electro-migration, EM) ’所以半_裝置的可靠度可被辦 加。再者’由於銅薄膜的電阻率低至約17…咖,所以^ 遞速=可被增加。因此,對於高速率裝置及更高聚集度的裝 置而5,开>成銅薄膜的技術為—種重要的技術。 由於夂世代的半導體裝置趨向於更高的性能,所以基於 接觸尺寸的縮減以及縱橫比的增加,良好的階梯覆蓋及良好 的接,鎮埋為所需。目前的趨勢為使用一種在鈦薄膜被沈積 之後藉由物理氣相沈積(PVD)與化學氣相沈積(⑽)法 之沈積銘膜的方法’以及一種使用以物理氣相沈積法所沈積 氮化组作為抗銅擴散膜之藉由電鍍法沈積銅的方法。 2而’、在前者的狀況中’由於㉝細的電阻率高於銅薄膜的 7阻率’所以存在闕題為其細於更高性能的半導體裝置 寺I再者,在後者的狀況中,所存在的問題為基於接觸尺寸 遽縮減以及縱橫比的增加,在使用電鍍方法的銅沈積上 斤限制。因此’使用電鍍將鋁線路及銅線路施加於次世代 ---------------Μ-----------------Μ (請先閱讀背面之注意事項再填寫本頁)486746 Printed by A7 B7, Consumer Cooperative of Employees of Intellectual Property Bureau, Ministry of Economics 5. Description of the invention (/) Background of the invention: Field of the invention: The present invention has _-a method for forming a metal circuit on a cast body device, especially-a method A method for forming a metal circuit on a semi-conducting device by using a chemical vapor deposition (CVD) process method to improve the adhesion characteristics of good copper. Description of the prior art: Generally, the metal film is formed on a semiconductor device, and the dazzling point of the copper film is higher than the melting point of the film. Since the copper film is more resistant to electro-migration (EM), the reliability of the semi-device can be increased. Furthermore, since the resistivity of the copper thin film is as low as about 17 ... ca, the speed of ^ = can be increased. Therefore, for high-speed devices and devices with a higher degree of aggregation, the technology for forming copper films is an important technology. Since semiconductor devices of the next generation tend to have higher performance, based on the reduction in contact size and the increase in aspect ratio, good step coverage and good connection, buried is required. The current trend is to use a method of depositing a thin film by physical vapor deposition (PVD) and chemical vapor deposition (⑽) after the titanium thin film is deposited, and a method of depositing nitride by physical vapor deposition. A method for depositing copper by electroplating as an anti-copper diffusion film. 2 ”In the former situation,“ Since the thin resistivity is higher than the 7 resistivity of the copper thin film ”, there is a problem that it is finer than a higher-performance semiconductor device. Furthermore, in the latter situation, The problem is that based on the reduction in contact size and the increase in aspect ratio, there are limitations on copper deposition using electroplating methods. Therefore, 'plating is used to apply aluminum and copper circuits to the next generation --------------- M ----------------- M (Please (Read the notes on the back before filling out this page)

486746 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(> ) 的半導體裝置中係存在著諸多問題。 、再者,在以化學氣相沈積法將銅鑲埋於超細線路結構中 ^况下藉由化學氣相沈積法一直以來最大的問題為黏著 該薄膜。若黏著性極微弱,則其將在後續的製程中造成明顯 的門喊,而使彳于銅金屬線路不佳。因此,為將以化學氣相沈 積法所形成的__施加於—半導體裝置_,黏著性的^ ,必須被改良。通常,在_被軸前,諸她、氮化叙及 亂化鈦等材料被使用於形成—個阻障金屬層。此時,黏 的問題亦變為一個大問題。 、用於改良銅層黏著性問題的各種方法已被提出。這些方 下所示首先,第一個方法為在一個銅層以化學氣相沈 積开/成後在3〇〇〜45〇C的溫度進行一道熱製程。然而, 雖然該方法可降低界面雜質,惟其具有產能的問題。再者, 在使用低介電常數介電質的狀況中,其將有聚集度的問題。 因此,該第—個方法H縣最適化的解財法。其次,第 二個方法為在_以化學餘沈積法沈積前,附加1錄著 為新開發預製體的方法。然而,這些方法亦不能成 近來,所提出之解決方法為,藉由化學氣相 =積法沈積-個鋼層’以物理氣相沈積法形成—個銅種子 曰以及以化學氣相沈積法开i成-個銅層。 發明簡要說明: 因此’本發明之_目的在於提供— 形成金屬線路的方法,其可藉由僅以化學氣相 本紙張尺度適用中國國家標準(CNS)A4規格(21Q x 297公爱) -----*-----------------^--------- (請先閱讀背面之注意事項再填寫本頁) A7 五、發明說明( 的—個2層而改良銅的黏著特性。 由入t成上述目的’根據本發明之—種在半導體裝置中形 人方法’其特徵在於所包含的步驟有:形成—個 Η^二=於—基層被形成於其上的基板上;形成一個鑲埋 介層絕緣膜上,以及接著進行—道清洗製程;沿著 ^ 3二,、圖案之該介層絕緣膜表面,形成一個阻障金屬 二雜:s迢電漿巧程’而將形成於該阻障金屬層表面上的 埋图牵镱Γ移除’藉由以化學氣相沈積法所職的銅將該鑲 ’而形成—個銅層;以及進行-道氫氣還原熱製 t該靖’並接_卜道辨機觀絲職銅金屬線 圖式之簡要說明: 列月述特性及其他特徵將配合附圖而被說明於τ 列祝明中,其中: -猶圖係為用於說明根據本發明之較佳實施例之 種在-半¥體裝置中形成金屬線路的方法。 l·---!||||1 — — —· · I I I I I I I 訂 — 11!! 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 圖號說明: 12-基層 14-鑲埋圖案 16-界面雜質層 i3_介層絕緣膜 15-阻障金屬層 17-銅層 4 五、發明說明(4) 較佳實施例之詳細說明·· 本發魏將細參相_較佳實施例喊詳細說明, /、將相似畔考數字被使用於代表__似的部分。 第ία至m圖係為用於說明根據本發明之較佳實施例之 -種在-半導體裝置中形成金屬線路的方法。 =參考第认圖,一基層12被形成於一基板(用於形 成半導體裝置的各種組件被形成於其中)上。在一介層絕 緣膜13被形成於包含該基層u的整個結構上以後,-^由 介層鋪孔及溝渠驗成的__ 14細鑲麵刻製程 2槪/成〃 a在進行_清洗製程後,沿著包含該镶埋圖 ” 14之該"層纟B緣膜13表面,形成—個阻障金屬層此 時’基於製程上及外在的因素,—個由諸如氧化物、氮化物 ^質所組成的界面雜質層16被形成於該轉金屬層化表 經濟部智慧財產局員工消費合作社印製 在上述中’基層12為具有一個多晶石夕結構、一個多晶石夕 化物結構及-個金屬結構(諸如嫣、紹、銅等)的導電性圖 案。該介層絕緣層13使用具有低介電常數的介電材料所形 成。在該鑲糊案14形成後所進行的清洗製程可使用射頻電 漿^在基層12為諸如鎮、銘等金屬時),並可使用活性清洗 製程(在基層12為鋼時)。該阻障金屬層15係以離子化物理 氣相沈積氮化鈦膜、化學氣相沈魏倾膜、金屬有機化學 氣相,積氮化鈦膜、離子化物理氣相沈積组、離子化氣化纽、 化學氣相沈雜、化學氣相沈魏她及化學氣相沈積氮化 鑛膜之任何-種所形成。已知地是,當該靖以化學氣相沈 本紙張尺度綱中國國家標準(CNS)A4g^ 297公釐) 五 經濟部智慧財產局員工消費合作社印製 A7 B7 發明說明(f) 積法形成時,該界面雜質 現在夂老莖m 將化銅層的黏著性。 賴時,二:圖’為在銅層以後序的化學氣相沈積法 ㈣移除 著特性,該界峰魏16係以電漿 ::述:’該電漿加工方法可使用遠程電漿加工法、腔 二以及—種同時進行遠程電漿加卫與腔室電聚 加工的方法。其條件如下: 首先’遠程電漿加工法,條件為進行1〇秒至1〇分鐘, 5^至·瓦範圍喻爾裤,使㈣氣體錢氣、氮氣、 =及氦氣中之至少一種且其流速被維持在50至500 seem 的fc圍中’該晶圓的溫度被轉在15〇至3耽的範圍中, 該晶圓與喷頭間的距離為20至5〇職,以及該腔室的壓力為 0.3至2托耳。 在使用混合氣體作為所使用之氣體的狀況中,該遠程電 聚加工方法包含使用5至95〇/〇氬氣及5至95%氫氣的麟方 法。 同時,該遠程電漿加工法可使用一單獨步驟及多重步 驟。在使用單獨步驟的狀況中,其可使用一翔氣體或一混 合氣體。在使用多重步驟的狀況中,其可重複該製程,藉此 一單獨氬氣或一混合氣體被使用,而氫氣接著被使用,工至 10次。 第二,腔室電漿加工法,條件為進行10秒至1〇分鐘, 50至700瓦範圍的腔室電漿功率,使用的氣體為氫氣、氮氣、 鼠氣及乱氣中之至少一種且其流速被維持在50至500 seen* 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 486746 經濟部智慧財產局員工消費合作社印製 A7 -----— B7 _—___ 五、發明說明(() 的範圍中,该晶圓的溫度被維持在15〇至35〇。〇的範 該晶圓與喷頭間的距離為20 S 5〇咖,以及該腔室 0.3至2托耳。 7冷 在使用混合氣體作為所使用之氣體雜況中,該腔室電 漿加工方法包含使用5至95%氬氣及5至95%氫氣的濺鑛二 法。 第二,同時進行遠程電漿加工與腔室電漿加工的方法首 先進行腔室電漿加工,並接著進行遠程電漿加工,其中一單 獨步驟及多重步驟皆可被使用。此時,該遠程電聚加工與腔 室電漿加工的個別條件同上述之各電漿加工。 現在參考第1C圖’在該界_簡10以賴製程移除 後,藉由以化學氣相沈積法所形成的銅將該鑲埋圖案14鑲 埋,而形成一個銅層17。 在上述中,銅鑲埋可使用直接液態注入(dli)、cem以 及使用諸如 _c)Cu(VTM0S)系列、(hfac)Cu(TMvs)系列、 系狀所有銅雜體_之所有的銳孔型與 喷灑型⑧發。所有的。銅係以金屬有機化學氣相沈積 (MOCVD)法沈積。 金屬有機化學氣相沈積法的條件如下:銅預製體被維持 ,Ο.? 5.0 _的流速,傳輸氣體係使用氫氣、氮氣、氬 氣及氦氣中之至少—種且其流速被轉在5Q至5〇〇 seem 的 範圍中、反應腔至的溫度被維持與汽化器相同,喷頭的溫度 被維持為疋值,沈積溫度被維持在15〇至·。c的範圍中, 該感受器與噴頭間的距離為%至s〇mm,以及該腔室的壓力 f紙張尺度適时關雜準(CNS)A4規格⑽χ撕公&--- 1* 2. Μ--------訂---------^ (請先閱讀背面之注意事項再填寫本頁) 486746 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(^ y 為〇·5至5托耳之間。 、y見在參考第1D圖,在銅層以氫氣還原熱製程加工後 =于=化學機械拋光及—道後清洗,因而形成銅略 170於鑲埋圖案14中。 ^展略 在上述中,該氫氣還原熱製程為改變銅 貌的盤弟?,甘丄丄 日日粒表面形 緣其係猎由在室溫至45(TC範圍於氫氣中進行i八 f!\3小時的錄程’射域氣可使輯錢或諸如氫^ (0至95%)、氫氣加氮氣(0至95%)等氫氣混合氣 本發明之上述實施例係《於-種當鋼被鑲埋於超細線 構(銅難崎由物魏減積或電銳被馳於其中> 中時’在銅以化學氣相沈積法沈積前,將阻障金屬層表面上 的界面雜質層移除的電漿製程,以便改良在—單獨彳:學氣相 沈積腔室中之銅層的黏著特性。 -由上述说明可瞭解,本發明在銅被鑲埋於超細線路結構 (銅難以藉由物理氣相沈積或電鍍法被鑲埋於其中)中時, 改良銅層的黏著特性。因此,其可省略以慣用之物理氣相沈 積法形成-個銅種子層製程,並可藉由僅以化學氣相沈積法 形成銅金屬線路而將製程簡化。 本發明已參考配合特定應用的一特定實施例做說明。具 有本技藝中之一般技術並獲得本發明之教導的人士將瞭解落 於其範疇中的其他改良與應用。 因此,所附申請專利範圍希冀涵蓋落於本發明之範疇中 的所有該應用、改良及實施例。 本紙張尺度顧巾國國家標準(CNS)A4規格(210 X 297公髮- 11 » 裝--------訂---------線 (請先閱讀背面之注咅P事項再填寫本頁)486746 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 5. There are many problems in the semiconductor device of the invention description (>). Moreover, in the case of embedding copper in an ultra-fine circuit structure by a chemical vapor deposition method, the biggest problem by the chemical vapor deposition method has always been adhesion to the film. If the adhesion is very weak, it will cause obvious door shouts in the subsequent processes, and make the copper metal line poor. Therefore, in order to apply __ formed to a semiconductor device by a chemical vapor deposition method, the adhesion ^ must be improved. Usually, in front of the shaft, materials such as titanium, nitride and titanium are used to form a barrier metal layer. At this time, the problem of stickiness also became a big problem. Various methods have been proposed for improving the adhesion of copper layers. These are shown below. First, the first method is to perform a thermal process at a temperature of 300 ~ 45 ° C after a copper layer is deposited / formed by chemical vapor deposition. However, although this method can reduce interfacial impurities, it has the problem of productivity. Furthermore, in the case of using a low-dielectric constant dielectric substance, there is a problem of the degree of aggregation. Therefore, the first method H county's optimal financial solution method. Secondly, the second method is a method for newly developing a preform before deposition by chemical co-deposition. However, these methods can not be achieved recently. The proposed solution is to deposit by chemical vapor deposition—a steel layer 'by physical vapor deposition—a copper seed and by chemical vapor deposition. i into a copper layer. Brief description of the invention: "The purpose of the present invention is to provide-a method for forming a metal circuit, which can apply the Chinese National Standard (CNS) A4 specification (21Q x 297 public love) only in the chemical vapor phase of this paper scale-- -* ----------------- ^ --------- (Please read the notes on the back before filling this page) A7 V. Description of the invention ( -A two-layer to improve the adhesion characteristics of copper. From the above, the above purpose is achieved according to the present invention "a method for forming a person in a semiconductor device", which is characterized in that the steps involved are: forming-one ^^ ==- The base layer is formed on the substrate thereon; a buried interlayer insulating film is formed, and then a cleaning process is performed; along the surface of the insulating film of the pattern, a barrier metal II is formed Miscellaneous: Plasma is used to remove the buried pattern formed on the surface of the barrier metal layer. Γ is removed and formed by copper that is used by chemical vapor deposition. Layer; and the hydrogen-reduction thermal process of the channel, the Jing 'parallel connection _ ________________________________________________ The characteristics and other characteristics will be described in the τ column Zhuming with the accompanying drawings, in which:-the figure is for explaining a method for forming a metal circuit in a -half body device according to a preferred embodiment of the present invention. L · ---! |||| 1 — — — · · IIIIIII Order — 11 !! (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs: 12 -Base layer 14-Embedded pattern 16-Interfacial impurity layer i3_ Interlayer insulating film 15-Barrier metal layer 17-Copper layer 4 5. Description of the invention (4) Detailed description of the preferred embodiment Refer to the detailed description of the preferred embodiment, and / or use similar figures to represent similar parts. Figures α to m are for explaining the preferred embodiment according to the present invention. -A method of forming a metal circuit in a semiconductor device. = With reference to the drawings, a base layer 12 is formed on a substrate (in which various components for forming a semiconductor device are formed). A dielectric insulating film 13 is formed including After the entire structure of the base layer u,-^ After the __ 14 fine veneer engraving process 2 槪 / 成 验 a After the _ cleaning process, along the surface of the "" layer 纟 B edge film 13 containing the embedded pattern" 14, a resistance is formed At this time, the barrier metal layer is based on process and external factors. An interfacial impurity layer 16 composed of materials such as oxides and nitrides is formed in the metallization layer. The above-mentioned 'base layer 12 is a conductive pattern having a polycrystalline structure, a polycrystalline structure, and a metal structure (such as Yan, Shao, copper, etc.). The interlayer insulating layer 13 is used Formed from a dielectric material having a low dielectric constant. The cleaning process performed after the formation of the paste 14 can use RF plasma ^ when the base layer 12 is a metal such as a town, a Ming, etc., and an active cleaning process can be used (when the base layer 12 is steel). The barrier metal layer 15 is an ionized physical vapor deposition titanium nitride film, a chemical vapor deposition film, a metal organic chemical vapor phase, a deposited titanium nitride film, an ionized physical vapor deposition group, and an ionized gas. Formed by any of the following: chemical bonds, chemical vapor deposition, chemical vapor deposition, and chemical vapor deposition of nitride ore films. It is known that when the Jing used the chemical vapor deposition paper standard Chinese National Standard (CNS) A4g ^ 297 mm), the A5 B7 printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (f) the product method formed At this time, the impurities at this interface will now reduce the adhesion of the copper layer to the old stem m. Lai Shi, II: The picture shows the chemical vapor deposition method following the copper layer. The characteristics are removed by the plasma of the Weifeng 16 series. The plasma processing method can use remote plasma processing. Method, cavity two, and a method for simultaneously performing remote plasma guarding and cavity electropolymerization processing. The conditions are as follows: First, the "remote plasma processing method" is performed for 10 seconds to 10 minutes, and the range is from 5 to watts, and at least one of gas, nitrogen, and helium is used, and The flow rate is maintained within the fc range of 50 to 500 seem. The temperature of the wafer is turned in the range of 15 to 3 delays. The distance between the wafer and the showerhead is 20 to 50 jobs, and the cavity The pressure in the chamber is 0.3 to 2 Torr. In the case where a mixed gas is used as the gas to be used, the remote electropolymerization processing method includes a lin method using 5 to 95/100 argon and 5 to 95% hydrogen. At the same time, the remote plasma processing method can use a single step and multiple steps. In the case of using a single step, it may use a flying gas or a mixed gas. In the case where multiple steps are used, the process can be repeated, whereby a single argon gas or a mixed gas is used, and hydrogen is then used up to 10 times. Second, the chamber plasma processing method is performed under the condition that the chamber plasma power is in the range of 10 seconds to 10 minutes and 50 to 700 watts, and the gas used is at least one of hydrogen, nitrogen, rat gas and turbulent gas, and Its flow rate is maintained at 50 to 500 seen * This paper size is in accordance with Chinese National Standard (CNS) A4 specifications (210 X 297 public love) 486746 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 -----— B7 _— ___ 5. In the scope of the invention description ((), the temperature of the wafer is maintained at 150-350 °. The distance between the wafer and the shower head is 20 S 50 °, and the chamber is 0.3. To 2 Torr. 7 In the use of mixed gas as the gas miscellaneous condition, the plasma processing method of the chamber includes two methods of ore splashing using 5 to 95% argon and 5 to 95% hydrogen. Second, The method of performing remote plasma processing and chamber plasma processing at the same time first performs cavity plasma processing, and then performs remote plasma processing, in which a single step and multiple steps can be used. At this time, the remote plasma processing The individual conditions for the plasma processing of the chamber are the same as those of the above-mentioned plasma processing. After referring to FIG. 1C 'removing the process in the world_Jane 10, the embedded pattern 14 is embedded by copper formed by chemical vapor deposition to form a copper layer 17. In the above, Copper embedding can use direct liquid injection (dli), cem, and use all types of sharp holes and sprays such as _c) Cu (VTM0S) series, (hfac) Cu (TMvs) series, all copper complexes Sprinkle the hair. all. Copper is deposited by metal organic chemical vapor deposition (MOCVD). The conditions of the metal organic chemical vapor deposition method are as follows: the copper preform is maintained, the flow rate of 5.0 is 5.0, and the transport gas system uses at least one of hydrogen, nitrogen, argon and helium and its flow rate is turned to 5Q In the range from 500 mm, the temperature of the reaction chamber is maintained the same as that of the vaporizer, the temperature of the shower head is maintained at a threshold value, and the deposition temperature is maintained at 150 °. In the range of c, the distance between the susceptor and the printhead is from% to s0mm, and the pressure of the chamber f paper size timely closing miscellaneous precision (CNS) A4 size ⑽χTear male & --- 1 * 2. Μ -------- Order --------- ^ (Please read the notes on the back before filling in this page) 486746 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Invention Description ( ^ y is between 0.5 and 5 Torr., y See the reference figure 1D, after the copper layer is processed by the hydrogen reduction thermal process = = = chemical mechanical polishing and-after cleaning, thus forming copper slightly 170 inlay. Buried in pattern 14. ^ In the above, the hydrogen reduction thermal process is to change the appearance of the copper ?, the surface edge of the Gansu Rihi grain is hunted at room temperature to 45 (TC range in hydrogen) Performing an eight-hour recording of 3 hours' shooting range gas can make money or a hydrogen gas mixture such as hydrogen ^ (0 to 95%), hydrogen plus nitrogen (0 to 95%), and the like. "Yu-type when steel is embedded in ultra-fine wire structure (copper Nakazaki by Wu Wei deductive or electric sharp is chucked in it > '' before the copper is deposited by chemical vapor deposition, the barrier metal layer surface Plasma process for removing the interface impurity layer in order to improve the adhesion characteristics of the copper layer in a separate layer: learn the vapor deposition chamber.-As can be understood from the above description, the present invention embeds copper in ultra-fine lines When copper is difficult to be embedded in the structure by physical vapor deposition or electroplating, the adhesion characteristics of the copper layer are improved. Therefore, it can omit the formation of a copper seed layer by the conventional physical vapor deposition method, The process can be simplified by forming a copper metal circuit only by a chemical vapor deposition method. The present invention has been described with reference to a specific embodiment that matches a specific application. Those who have the general technology in the art and who have obtained the teachings of the present invention Other improvements and applications falling within its scope will be understood. Therefore, the scope of the attached patent application is intended to cover all such applications, improvements, and embodiments falling within the scope of the present invention. This paper is scaled to the National Standard (CNS) A4 specifications (210 X 297 public-11 »installed -------- order --------- line (please read the note on the back 咅 P before filling this page)

Claims (1)

τ〇υ/^〇τ〇υ / ^ 〇 ABCD 1驟種在—半導體裝置巾形成金麟路的方法,包含下列步 •幵乂成-個介層絕顧於—基層被形成於其上的基板 , 、,形成一個鎮埋圖t於該介層、絕緣膜上,並接著進 道清洗製程; 阻Γ觸埋_之齡舰緣絲面,形成一個 阻P早金屬層; ㈣^^道賴製程,⑽形成於該轉金屬層表面上 的界面雜質層移除; 糈由以化學氣相沈積法所形成的銅將該鑲埋圖案鑲 埋,而形成一個銅層;以及 行—道缝财鋪秘_層,並歸進行—道 化子機械拋光而形成銅金屬線路。 2. 專利範圍第W所述之_種在一半導體 的方法,其中該基層為具有一個多晶德構一 化物結構及-個金屬結構(諸 的導電性圖案。 j寻J 3. ^請專利範圍第1項所述之一種在一半導體裝置中料 金屬線路的方法,盆中呤入既 置甲开乂成 八中^,1層絕緣層係使用具有低介電常 數的介電材料所形成。 1包吊 4·如申請專利範圍第1項所述 金屬線路的方法,其中一半導體裝置中形成 "月,先製裎可使用射頻電漿(在基 ---------裝II ··* (請先閲讀背面之注意事項再填寫本頁) 、言 線 經濟部智总財4局Μ工消費合作社印製 太紙杀尺㈣财_ H家^^( CNS ) A4規 二'轉金麵),並可使黯性清洗製程(在 I層為鋼時)。 5·==專利範圍_所述之—種在—半導體裝置懷 =、ϊ路的方法,其中該轉金屬層係鱗子化物理氣相 相冲2鈦膜、化學氣相沈魏化鈦膜、金屬有機化學氣 二貝Τ鈦膜、離子化物理氣相沈積Μ、離子化氮化 相沈積!£ '化學氣相沈積氮她及化學氣相沈 積虱化鎢膜之任何一種所形成。 6 專利範圍第1項所述之—種在—半導體裝置中形成 霉、路的方法’其巾該電漿加卫可使用遠程電漿加工 腔室電漿加卫法,以及—種同時進行遠程電漿加工與 I至電漿加工的方法其中之一種。 經濟部智慧財邊局負工消費合作社印製 7. t申請專利範圍第6項所述之—種在—半導體裝置中形成 至屬線路的方法,其中該遠程電漿加工法,條件為進行10 ^至10分鐘,50至7〇〇瓦範圍的遠程電漿功率,使用的 f體為氫氣、氮氣、氬氣及統中之至少-種且其流速被 維持在50至500 _的範圍中,該晶圓的溫度被維持在 150至35(TC的範圍中,該晶圓與喷頭間的距離為2〇至5〇 ,以及該腔室的壓力為〇 3至〕托耳。 8·如申請專利範圍第6項所述之一種在一半導體裝置中形成 金屬線路的方法’其中該遠程電漿加工法可使用單獨步驟 進行,其使用-單職體或1合氣體作為被使用的氣 體。 9.如申請私m圍第6項所述之一種在一半導體裝置中形 瓜纸法尺度適用中國國家標準(CNS ) A4規格(2!〇x297> 486746 A8 Βδ C8 D8 申請專利範国 經濟部智总財是局§(工消費合作社印炎 路的方法,其中該遠程加工法可使轉複該製 用,而^ ^ 獨贼或一混合氣體被使 風乳接者被使用,1至10次。 位專利範圍第6項所述之一種在一半導體裝置中形 成孟屬線路的方法,其中該腔室電漿加工法,條件 打10秒至10分鐘,50至瓦範圍的腔室電裝功率, 使用的氣體域氣、氮氣、氬氣及氦氣中之至少一種且 被轉在50至職财,該晶_溫度 I、寺在150至350〇C的範圍中,該晶圓與喷頭間的距離 為2〇至50mm,以及該腔室的壓力為〇3至2托耳。 11’如申清專利範圍第6項所述之一種在一半導體裝置中形 2屬線路財法,其巾綱時進行遠程電漿加工與腔 至電漿加工的方法首先進行腔室電漿加工,並接著進行 遠程電漿加工。 12·如申請專利範圍第1項所述之一種在一半導體裝置中形 成金屬線路的方法,其中該銅鑲埋可使用直接液態注入 (DU )、CEM以及使用諸如(hfac)Cu(VTMOS)系列、 (hfac)Cu(TMVS)系列、_c)Cu(DMB)系列之所有銅預製 體種類之所有的銳孔型與喷灑型蒸發器,其中銅係以金 屬有機化學氣相沈積(M0CVD)法沈積。 13·如申請專利範圍第12項所述之一種在一半導體裝置中形 成金屬線路的方法,其中該金屬有機化學氣相沈積法的 條件如下··銅預製體被維持在0.1至5.0 seem的流速,傳 輸氣體係使用氫氣、氮氣、氬氣及氦氣中之至少一種且 閱 讀 北 · 月 面 意 事 項 再 寫 本 頁 裝 訂 線 木紙張尺度_ 準(CNSTI^ ( 2Η) !< 297公釐 486746 A8 B8 C8 D8 六、申請專利範圍 其流速被維持在50至500 seem的範圍中,反應腔室的溫 度被維持與汽化器相同,噴頭的溫度被維持為定值,沈 積溫度被維持在150至300°C的範圍中,該感受器與喷頭 間的距離為20至50 mm,以及該腔室的壓力為0.5至5 托耳之間。 14.如申請專利範圍第1項所述之一種在一半導體裝置中形 成金屬線路的方法,其中該氫氣還原熱製程係藉由在室 溫至450°C範圍於氬氣中進行1分鐘至3小時的熱製程, 其中該氫氣可使用純氫氣或諸如氫氣加氬氣(0至 95%)、氫氣加氮氣(0至95%)等氬氣混合氣體。 ----------------訂 線 ♦« (請先閱讀背面之注意事項再填寫本頁) 經濟部智总財4局員工消費合作社印製 _12- 戈紙張尺度適用中國國家標搫(CNS ) A4規格(210X 297公釐)ABCD 1 is a method for forming a golden circuit for semiconductor devices. It includes the following steps: • Forming an interposer—the substrate on which the base layer is formed, to form a buried pattern. On the interlayer, the insulation film, and then enter the cleaning process; the resistance Γ touches the burial surface of the aging rim, forming an early metal layer that resists P; ㈣ ^^ Dolay process, ⑽ is formed on the surface of the transition metal layer The interface impurity layer is removed; 将该 the copper pattern formed by the chemical vapor deposition method is used to bury the embedded pattern to form a copper layer; Sub-mechanical polishing to form copper metal lines. 2. The method described in the scope of the patent _ a method of a semiconductor, wherein the base layer is a conductive pattern having a polycrystalline germanium structure and a metal structure (see Figure 3.) The method described in item 1 of the scope of the present invention is a method for feeding a metal circuit in a semiconductor device. A pot is inserted into an existing substrate to form a middle layer. The 1-layer insulating layer is formed by using a dielectric material with a low dielectric constant. 1 package hanging 4 · As in the method of applying for the metal circuit described in item 1 of the scope of patent application, one of the semiconductor devices is formed " monthly, firstly, RF plasma can be used (in the base --------- Pack II ·· * (Please read the precautions on the back before filling out this page), the Ministry of Economic Affairs and the Intellectual Property Office of the 4th Bureau of the Industrial and Commercial Cooperatives printed the paper to kill the ruler_ H 家 ^^ (CNS) A4 Regulations 2 'to gold surface), and can make the dark cleaning process (when layer I is steel). 5 · == Patent Scope _ described-a method in-semiconductor device Huai =, Kuo Road, where the turn Metal layer system scaled physical vapor phase phase 2 titanium film, chemical vapor deposition of titanium film, metal organic chemical gas phase 2 Titanium film, ionized physical vapor deposition M, ionized nitride phase deposition! 'Chemical vapor deposition of nitrogen and chemical vapor deposition of tungsten film. —A method for forming mold and road in a semiconductor device—its plasma plasma guarding can use a remote plasma processing chamber plasma guarding method, and a remote plasma processing and I to plasma processing can be performed simultaneously One of the methods is printed by the Ministry of Economic Affairs and the Smart Finance Bureau's Consumer Work Cooperative, which is described in item 6. of the scope of patent application for t. A method for forming a subordinate circuit in a semiconductor device, wherein the remote plasma processing The method is to perform a remote plasma power in the range of 10 ^ to 10 minutes and a range of 50 to 700 watts. The f-body used is at least one of hydrogen, nitrogen, argon, and the system, and the flow rate is maintained at 50 to In the range of 500 °, the temperature of the wafer is maintained at 150 to 35 (in the range of TC, the distance between the wafer and the showerhead is 20 to 50, and the pressure of the chamber is 0 to 3) 8. The half of one of the items described in the patent application scope No. 6 is half. Method for forming a metal circuit in a bulk device 'wherein the remote plasma processing method can be performed using a separate step, which uses a single job or a 1-gas as the gas to be used. 9. As described in the application for the private m section 6 One type is in accordance with the Chinese National Standards (CNS) A4 specification (2! × 297 > 486746 A8 Βδ C8 D8 in a semiconductor device) for patent application. Method, in which the remote processing method can be used to re-use the system, and ^ ^ alone thief or a mixed gas is used by the wind-sucker, 1 to 10 times. A method for forming a Monsoon circuit in a semiconductor device according to item 6 of the patent scope, wherein the chamber plasma processing method is performed under conditions of 10 seconds to 10 minutes and a chamber electrical power in the range of 50 to watts. At least one of the gas domain gas, nitrogen, argon, and helium used is transferred to 50 to 10,000 yuan, the crystal temperature I, the temple is in the range of 150 to 350 ° C, the wafer and the shower head The distance is 20 to 50 mm, and the pressure in the chamber is 0 3 to 2 Torr. 11 'As described in item 6 of the scope of the patent application, a method for forming a semiconductor device in a semiconductor device is a circuit method. The method of remote plasma processing and cavity-to-plasma processing in the towel outline first performs cavity plasma processing. And then remote plasma processing. 12. A method for forming a metal circuit in a semiconductor device as described in item 1 of the scope of patent application, wherein the copper embedding can use direct liquid injection (DU), CEM, and use such as (hfac) Cu (VTMOS) series (Hfac) Cu (TMVS) series, _c) Cu (DMB) series, all sharp hole type and spray type evaporators of all types of copper preforms, in which copper is prepared by metal organic chemical vapor deposition (M0CVD) method Deposition. 13. A method for forming a metal circuit in a semiconductor device as described in item 12 of the scope of the patent application, wherein the conditions of the metal organic chemical vapor deposition method are as follows: The copper preform is maintained at a flow rate of 0.1 to 5.0 seem , The transport gas system uses at least one of hydrogen, nitrogen, argon, and helium and read the North and South Moon notes before writing this page gutter paper size _ 准 (CNSTI ^ (2Η)! 297 mm 486746 A8 B8 C8 D8 VI. Patent application range The flow rate is maintained in the range of 50 to 500 seem. The temperature of the reaction chamber is maintained the same as the vaporizer, the temperature of the nozzle is maintained at a fixed value, and the deposition temperature is maintained at 150 to 300. In the range of ° C, the distance between the susceptor and the sprinkler head is 20 to 50 mm, and the pressure of the chamber is between 0.5 to 5 Torr. A method for forming a metal circuit in a semiconductor device, wherein the hydrogen reduction thermal process is performed by a thermal process in an argon gas at a temperature ranging from room temperature to 450 ° C for 1 minute to 3 hours. Gas or argon mixed gas such as hydrogen plus argon (0 to 95%), hydrogen plus nitrogen (0 to 95%). ---------------- Order line ♦ «( Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the 4th Bureau of Intellectual Property, Ministry of Economic Affairs_12- Ge paper size applies to China National Standard (CNS) A4 (210X 297 mm)
TW89123263A 1999-11-05 2000-11-04 Method of forming a metal wiring in a semiconductor device TW486746B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990048752A KR100341849B1 (en) 1999-11-05 1999-11-05 Method of forming a metal wiring in a semiconductor device

Publications (1)

Publication Number Publication Date
TW486746B true TW486746B (en) 2002-05-11

Family

ID=19618644

Family Applications (1)

Application Number Title Priority Date Filing Date
TW89123263A TW486746B (en) 1999-11-05 2000-11-04 Method of forming a metal wiring in a semiconductor device

Country Status (3)

Country Link
JP (1) JP2001144094A (en)
KR (1) KR100341849B1 (en)
TW (1) TW486746B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9051641B2 (en) 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
KR20030051014A (en) * 2001-12-20 2003-06-25 동부전자 주식회사 Method of manufacturing via contact in semiconductor device
KR100445551B1 (en) * 2001-12-21 2004-08-25 동부전자 주식회사 Method of remove a residual metal-oxidation product of a semiconductor device fabrication process
KR101089249B1 (en) * 2003-09-22 2011-12-05 매그나칩 반도체 유한회사 Semiconductor device and a method of manufacturing the same
KR100723253B1 (en) * 2005-12-29 2007-05-29 동부일렉트로닉스 주식회사 Fabricating method of metal line in semiconductor device
KR20080113518A (en) 2007-06-25 2008-12-31 주식회사 동부하이텍 Method of manufacturing semiconductor device
KR101225642B1 (en) 2007-11-15 2013-01-24 삼성전자주식회사 Method for formation of contact plug of semiconductor device using H2 remote plasma treatment
US8227344B2 (en) * 2010-02-26 2012-07-24 Tokyo Electron Limited Hybrid in-situ dry cleaning of oxidized surface layers
KR101366367B1 (en) * 2013-01-25 2014-02-24 박종익 Method for forming copper layer of power semiconductor module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3287042B2 (en) * 1993-01-26 2002-05-27 日本電信電話株式会社 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
KR100341849B1 (en) 2002-06-26
JP2001144094A (en) 2001-05-25
KR20010045454A (en) 2001-06-05

Similar Documents

Publication Publication Date Title
KR100712168B1 (en) Forming a copper diffusion barrier
US20050124154A1 (en) Method of forming copper interconnections for semiconductor integrated circuits on a substrate
JP3793144B2 (en) Method for forming copper diffusion prevention film using aluminum
TW201028494A (en) Methods for depositing tungsten films having low resistivity for gapfill applications
TW486746B (en) Method of forming a metal wiring in a semiconductor device
TW444299B (en) Method of forming a copper wiring in a semiconductor device
KR100624351B1 (en) Method of chemical vapor deposition of metal films
US6670266B2 (en) Multilayered diffusion barrier structure for improving adhesion property
US20060276033A1 (en) Adhesion of tungsten nitride films to a silicon surface
KR100289515B1 (en) Barrier emtal layer and method of forming the same
US20030109133A1 (en) Process for fabricating an electronic component incorporating an inductive microcomponent
Smirnova et al. Atomic layer deposition of Ruthenium on different interfaces for an advanced metallization system of ICs
US6579793B2 (en) Method of achieving high adhesion of CVD copper thin films on TaN Substrates
JP2002057125A (en) Method of forming metal wiring
KR100710201B1 (en) Method for forming metal line of semiconductor device
JP2002190524A (en) Method for forming metal line of semiconductor device
TW478109B (en) A CVD/PVD/CVD/PVD fill process
US20060063379A1 (en) Forming a combined copper diffusion barrier and seed layer
TW465048B (en) Method of forming tungsten plugs in interlayer dielectrics using mixed mode deposition process
KR100800142B1 (en) Method of manufacturing semiconductor device
KR19990006061A (en) Metal wiring formation method of semiconductor device
KR100286253B1 (en) Selective deposit method of metal thin film using n2 plasma and it's application to multi-level metal interconnection
TW518712B (en) Manufacture method of low resistance barrier layer of copper metallization process
KR100430682B1 (en) Method of forming metal line of semiconductor device for restraining reaction between metal lines
TW392295B (en) Method for manufacturing barrier layers without volcano effect

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees