TW486633B - Bridge between parallel buses over a packet-switched network - Google Patents

Abstract

A method for bridging between first and second parallel buses (22, 34) having a common set of bus transactions and ordering rules governing execution of the transactions. The method includes receiving at a target address on the first bus a bus command, associated with one of the transactions in the set, which command is issued by an originating device (24) on the first bus for execution by a destination device (36) on the second bus. A data packet embodying the received bus command is sent from the target address on the first bus over a packet-switched network (30) to a master address on the second bus. Responsive to receiving the data packet at the master address, the bus command is delivered over the second bus to the destination device in accordance with the ordering rules.

Description

486633 V. Description of the invention (1) Cross-reference of related applications ... This application is related to another patent application. On the same day, please, titled π through the packet exchange module. The Heart Ten Order Bus Newsletter 丨 丨 also allows the client of the special and Shen Gu case, and also serves as the spring invention field: 1 The package is a general computer system, and more particularly, it relates to a system that uses a sealing blade to connect a computer host to the background of the invention. In the current generation of computers, the central processing unit (CPU) is connected to the system memory and peripheral devices through a sheep pole bus. 9 、 Color six six ΛΑ J. You are as straight as a thousand buses, such as ubiquitous peripheral parts. Interface (Peripheral C⑽pQnent Interface "PCI) bus. As the time-day path—the width—the pulse speed increases, in order to maintain the system demand, the parallel bus changes ‘the price is high and the price is complicated. The response to the rapid development of the computer industry, = In the input / output (1/0) bus structure, the host computer is set to ^: 开关 网络 连接 #, which generally means that some structures for the switching module have been proposed. , Including the "next generation I / 0," (NGI〇) and "future I / O (F 10), reaching the highest point of the" infinite frequency band "structure, which is composed of a single mr including Intel, Sun, Hewlett-Packard, International Business Machines, Compaq, Dell, and Microsoft) are leading the development. The Storage Area Network provides a similar, packetized-method for high-speed storage access using an infinite-band module. Only PG1. Regional bus will limit the number of different devices that can be connected to it

486633 V. Description of the invention (2) Any two devices connected to the busbar shall be allowed to be connected in a quantity and within the allowed physical distance. To overcome this & limitation, a Pdl-to-PCI (P2P) bridge is used to connect two or more PC I area buses. The bridge must be able to enable a device on one of these buses to write to and read from a device wiped on the other bus without violating the bus protocol and processing sequence rules. Failure to follow bus rules can result in death and errors. PC I bus communication protocol

The rules and regulations are detailed in the PCI Special Bus Group (Hillsboro, Oregon) PCI Area Bus Specification, Version 2 · 2 (1 998), which is also used as reference material, especially please refer to Section 3.2. 5 (Pages 40-44) π Processing Sequence and Declaration "and Appendix E (Pages 267-277), the system processing sequence π.

According to this description, there are 9 types of PCI bus processing that can be divided into two categories, declarative and non-declarative. They are based on how they are handled by an intermediate medium, such as a bridge. The declaration processing is when they reach their ultimate The destination device is completed before the source (main) device, so the main device can perform other tasks, including other bus processing, before the announcement process reaches the ultimate destination device. The main device receives the data of the actual destination device and is responsible for ensuring that the access to the destination device is correct Responsibility for completion, PCI bus specifications need to declare memory writes (including memory writes and memory writes to be invalid). The non-declaration processing on the P CI buses is only when they reach their ultimate destination device Completed at the source device, the main device cannot perform any other related work before the completion of the processing and return from the destination device. In the example of a read process, this means that it has returned from the destination device. For a write process, it is necessary to return Pass a write confirmation. Memory read according to PC I specifications

5019-3607-PF.ptd Page 7 486633 V. Description of the invention (3) Processing (memory reading, memory reading row and memory reading multiple rows), and structure processing (structure reading, structure writing ) And output / input (I / O) processing (I / O read and I / O write) are undeclared. Table 1 summarizes and identifies the PC I bus processing, which is based on the overall PC I address space allocation into memory, I / 0, and structural address space: Table 1 PCI bus processing processing name meaning declaration i / O read address space No 1/0 write write data to media map to 1/0 address space 吝 structure read from media read data map to 1/0 girl address space No structure write data into media map豺 To the structure pull address space & Ji Yiyun [Write the written data to the media map to the memory ship pull address space is a memory write and the invalid nested data to the media is mapped to the memory ship pull space, With a complete fast cache, the least transfer of storage area is the memory plating read from the media to read the data to reflect the memory of the ship's pull-out space. The data in the row of the area is mapped to the memory address space. Is it regretful to read the multiple rows? The media reads the multiple rows of the fast and slow storage area. The oblique mapping of the data to the memory address space. Confirmation, special cycle Dual address cycle, as described above PC I bus specifications, the use of dual address cycle is 32 yuan 64 yuan means to access the address space of the two phases, and must be supported by P2P bridges. Interrupt confirmation and special loop support are optional. Traditionally, a P2P bridge includes a bridge device on each of the two PCI buses. It is a logical and physical connection between the bridge devices to connect to the bus. When a main device on a first bus is to use a

5019-3607-PF.ptd Page 8 486633 V. Description of the invention (4) When a destination device on the second bus initiates a process, it sends an appropriate bus command to the first bus address space. One address of the destination device 'specifies the destination device when it is turned on. This address is within the address range of the bridge device on the first bus. The bridge device is set to claim all cycles of the destination device (Cl, aimr addressed to the second bus), and after this cycle (c 1 a 1 m), the bridge device on the first bus will Send to the bridge device on the second bus, and the bridge device on the second bus sends this cycle to the final destination device.

When this command is a declaration memory write command, the bridge device immediately recognizes the command and sends the data to be written to the destination device. The other write commands and read commands are regarded as Delayed Write Requests (DWRs) and Delayed Read Requests (DRRs) respectively. When the bridge device receives this delayed request , Which returns a retry response to the primary device and sends the appropriate command to the second bus via the bridge device. Then the bridge device waits for an appropriate delayed write completion (DWC), describing

Whether the write was successfully performed, or delayed read processing (DRC), returns the requested data, and returns it from the destination device via the bridge device. This process is done only when the bridge device returns DWC or DWR to the source (primary) device. In order to avoid errors and possible deadlocks, the bridge device must service all processing in accordance with the processing order rules of the PC I bus communication protocol. Appendix E of the above PC I bus specification must comply with the following order rules of the bridge device: 1 · One is transmitted to The PMW behind the bridge destination device cannot exceed one

5019-3607-PF.ptd Page 9 486633, Invention Description (5) First, the received PMW, that is, the PMW processing must be completed in the order in which they were received. 2 · — The delayed read request (DRR) must promote the declaration of the written data to maintain the order, and the read processing cannot exceed the PMW. '_ 3 · A non-declaration write (DWR) process must cause the declaration write data to be forwarded to maintain order, and DWR cannot exceed PMW. 4. Before completing a read process (DRC), any write data must be pushed back to the source bus of the read process, that is, the DRC cannot exceed the PMW (assuming that the write is completed before the read process is completed The order is accepted on the second bus). 5 · — The PMW must be allowed to exceed a DRR or DWR to avoid dead knots. 6. · Delayed completion (DWC or DRC) processing must be allowed to go beyond a delayed request (DWR or DRR) processing to avoid deadlocks. 7 · — PMW must be allowed to pass a DWC 4DRc to avoid dead knots. The other processes are not limited in order and can be processed by the bridging device in any convenient order. Since the PC I bus is a parallel bus, most of the known P2P bridge devices use a similar parallel architecture. However, the Texas Instruments Group in Santa Clara, California recently published a pci-t0_pci bridge / radio transceiver chipset. It claims that it can transmit serial PC I on twisted pair cable to reach the theoretical maximum PCI bus speed of 132MB / S. The design of this chip can extend and extend beyond the normal P C I parallel bus distance by connecting two separate Pc 丨 parallel buses with a twisted pair cable.

4 Lion V. Description of the invention (6) Summary of the invention: The purpose of the flow row ί :::: 3: points is to provide an improvement between the two parallel rows of two = r: devices, and the interface of the two peripheral parts of the special feature converges the present invention. Some of these views are even more—style network ^ $ τ / ”The purpose is to provide a method and equipment for bridging between two parallel-sink-flow buses through packet switching. Interface ::::: Some views are more-the purpose is to provide Map peripheral parts to sequence data packets and vice versa, and follow the order of peripheral parts "surface bus processing". 1 remote network is a preferred embodiment of L month, a bridge is exchanged through a packet =-parallel transfer of money to-a second, remote parallel bus. = Ben, Ming's principle is that other types of buses and networks are available;: μ soil is the first and second parallel buses including peripheral component interface buses = and packet-switched networks include-infinite band networks. The bridge receives the peripheral part interface bus read and write commands,-one of the main devices on the bus issues 1 they transfer "two K" via this network, and then transfers them back to the appropriate peripheral part interface bus The command is transmitted to one of the destination devices for execution on the second bus. The response of the destination device is similar to the transfer and return via the bridge to the main device (from the main device on the second bus and the first bus The commands issued by the destination device are preferably processed in the same way.) In transmitting and processing the IB packet, the bridge follows the order rule of the bus processing of all peripheral parts interface. The bridge is for each first and first peripheral part interface Included on the bus

5019-3607-PF.ptd Page 11 486633 V. Description of the invention (7): Each bridge device, each bridge device preferably includes a target channel transfer two (TCA), connected to each bus, and a network Road interface, connected to I b net =. Preferably, the network interface includes a switch, but in fact any interface that complies with the Iβ rule can also be used. The target channel adapter converts each PCI read, fetch, and write up command. The target channel adapter receives the read and write commands and enters the IB read and t write packets for transmission through this interface through the Iβ module. Preferably, the TCA assigns a respective IB network channel to the address space of the associated read and write commands, so that the PCI memory, structure, and processing f each obtain their own fixed channel from the network. The pass in this article =: Special: Path and-service (or priority) level, different types of memory read processing on the row are better ^ hunting by specifying an appropriate value to the corresponding Iβ read field to identify. c τ heartbeat length area The individual channels in the space above the row are pre-designated and the target sink TCA receives a read or write packet. When this target issues such an application on the target bus, a dagger-like channel is used, ^ Zhongwei 2; '”or 1 / 〇 command. Network services delay reading and writing ^ Hold packets Sequential means execution before transmission and service, such as PCI $, each κ fetches and writes to the command buffer memory, the best is to include-first again = to serve a request for the service. When the target on the target bus Channel transfer == FIFQ), buffer memory, transfer

486633 V. Description of the invention (8) Delay the read or write command, which places this command on hold and waits for execution. However, whenever the TCA receives a declaration write ^, Zhai Zhong believed that a write packet came from a channel / order (broken J) of this network 'It immediately placed this command on the target bus as: Delay command in upper body register. k. Backflushing germanium In some preferred embodiments of the present invention, three of them are bridged together through an ordinary IB network. These more practical busbars have a -bridge device to perform these functions. And network, network, each = read and write as a transmission between bridge devices; including J = known bridges, whether parallel or serial, can only be connected between known technology PCI buses (or other ^ Bridge-to-road junction (浠 xi Xi Ding a pole row), so when connecting multiple multiplex bridges. Because of the advantages of the present invention: Second, this limitation. ) As a bridge, so they will not be very close to the first and second parallel busbars according to the invention, providing a bridge

In order to control the execution of the sequence rule, the method includes: one of the processing combinations _ ^ destination address reception-bus command, a command issued by a source device is because the first bus goes up; because the second bus goes up One-purpose device

偟, 4 ^ Includes the E address on the first bus line on the switch network, including the received A " R on the ratio E bus one of the main I j E ^ 卩Order one of the data packets to the address of king il; and

V. Description of the invention (9) Rule bit: Secondly, the data packet received here, in order, preferably, the destination device transmits the bus command. Surface bus: The first bus driver of this package includes—the peripheral parts are introduced. As a parent switching network, it includes an infinite frequency band network. Basket one or two for receiving this bus command at this target address is included in row a to-bridge device-in the address space ί = :; Η is to specify this address ΐ :: This address range includes the target Address. The best, and mapping each of these = circumference = 诒 specify multiple address ranges to this bridge device to send this packet includes: t = to a respective channel in this network 'and its target address = = pass; send this The packet to include the mapped address range includes, set: surround / In a preferred embodiment, 'specify the plurality of addresses; two; this: connect the addresses of the device on the-bus The space includes memory :: In the address range, this multiple, ,,, and structure and output / input (I / 0) address space. Additional or another. A 43? ^ Bus command includes mapping; = send this bus through this second bus ^ ,,, the channel that receives this packet to one of several address spaces on this second bus An address space. Incidental or another option is that # 妾 Receive this command includes receiving multiple commands at one or more addresses within the target range of the specified range, and mapping this target address range includes mapping all of the addresses in this range One or more addresses have been transmitted to the same channel so far. + This packet is transmitted via this channel of this network in the order received by the bridge device. Preferably, 'receiving the streaming command includes receiving a read command for execution by a destination device, and wherein transmitting the data packet includes transmitting,.

The way to read the request is to combine this with the transmission and set a data as ‘to receive this packet. More preferably for this purpose this network length zone command reads one or more fast-attached two buses including received packets including received first delayed transmission packets in response to this additional write command including sending an order The purpose is to load data from this network owner or another to the second this second first or another device that is written at the primary address by the target network to read the request field in response to this read this to The cache is selected as', and thus the target address read command read command fetch command is selected as the device's incoming request packet and the address is transmitted once to receive this read memory read packet including a given amount. Quantitative includes the list of storage areas. It is preferably, and among them until transmission is included. Receive this sink to execute and package. It is preferred that Qiu Jin is retrieved by the second sink packet, and a given amount of data is received by the receiver. Here, an additional or another option is received in the read request packet to receive a command to be placed in the main address by the memory. Send a response packet at the address' receive this read command packet and send the data received by this bus command packet. This response stream command includes receiving a packet where the data packet is transmitted, and by executing this write bus, a cancer recognition is received. And it should be confirmed to the target address »Erhui, = 佺 for 'Receiving this bus command includes receiving a request to perform the 5th bead = row 5 delay processing, before continuing to complete this delay processing by 1¾ = ^ Perform one of the announcement processing on the second bus, and send the bus command line # 私 ^ L earth dagger to service this announcement processing before the delay processing. More preferably, 'transmitting the bus command includes placing the delayed processing request; to one of the addresses in the buffer memory and allowing the declaration to process the request

Page 15 486633 V. Description of the invention (π) Go over this buffer storage. Additionally or alternatively, a response to the delayed processing request is received at the primary address via the second bus, and a response including the response is sent by the primary address via the second bus before receiving the announcement processing request. The response packet is sent to the destination address, where serving this announcement processing includes placing the response in one of the buffers of this destination address and sending this response to the source device only after servicing this announcement processing. Additionally or alternatively, receiving the bus command includes receiving a request to perform a declaration process on one of the second buses, and performing a request to perform another process on the second bus before continuing to complete the announcement process. , And transmitting the bus command includes ensuring that this _ declaration processing is completed before servicing this other processing. According to a preferred embodiment of the present invention, the factory also provides a method for bridging between a source parallel bus and a first and second target parallel bus. All of these buses have a common combination of bus processing. The sequential rules of these processes are controlled and executed. The method includes: specifying the first and second address ranges from the source bus to an address space of a bridge device to converge with the first and second destinations, respectively. Bus communication; Receive bus commands at the first and second target addresses within the first and second ranges respectively. 'This bus command combines one or more processing in this combination_ and is due to this source bus The at least one source device sends out to execute by the first and second destination devices I on the first and second target buses respectively; and thus the bridge device transmits the received data including the received data through respective serial links.

486633 V. Description of the invention (12) " '~ "' ~~ — The data of the target and f are packaged to the first and second major addresses on the first and second buses respectively; and · Respond to the rules received at this primary address via this first and first item; ^ ying, ☆ 4, quotation, dagger 'in this order; Rank ... then the transmission path of the device for each destination, determine :: Γ] ίΓ includes the route of the packet-switched network, the address range of the two brothers to the individual shots on this network = brother-the sending of this packet includes separately After this, the first, the second, and the second data packet. Yi Yitong forced to transmit this first according to a preferred embodiment of the present invention, and the second peripheral part interface bus between the "; = a common combination that bridges to the-and the sequence of these processes. Brother magic control system, this method includes part 3 :: introduction: target address on the queue receive-peripheral "quote" command to capture the queue, this command is issued by the source device on the source : Piece :: The target device on the surface bus-iC zero for one week; the interface; the door processing order interface interface processing bus connection = the address of the address Η second; the edge parts interface bus package to this interface interface order by This second perimeter. 1 + 2, according to the perimeter zero η order; 丨 surface bus to this end

5019-3607-PF.ptd

Page 17 5. Description of the invention (13) The device transmits this bus command. Preferably, receiving the peripheral parts to intersect I ^ φ / inflow command includes receiving by, mouth structure β shell fetch, output / input (1 / 〇) read second read row is 9 engraved priests a, , Lu Jiyi ’s body reading, memory fetching 丨〗 and δ Ji Yi ’s multiple read failure command interface, vine, and six sisters come into the house ^ '^ take multiple types of peripheral parts' 丨Take the order, and it is said that DAO Cao's punishment is 5-? ^ D. This poor material packet includes a map that reads this more elegantly to an early one and reads it in 7 stoves & This sequence is connected to and from the port. It is better to map these multiple ^ round out / give Γ τ / η, > & t formula includes the specified structure read, ffi / Han input (I / O) read, memory path, in: i κ ^ π & +, and terms are taken from the different or additional-selected commands to be transmitted. ϋ Λ = | & ^ i + ^ ", such multiple types include the specified value Wang this. One of the request packets includes a printable area and a jitter length area in response to this command. Heart ordering or memory read multiple commands. Additional or alternative options include receiving by the structure to write this. Peripheral parts interface bus write and memory write and benefit input (1 / 〇) Enter, write down / record the interface bus write command ,,,,, ί = A Select multiple types of peripheral parts, etc. Multi-heavy to a single frame where transmitting this data packet includes mapping this node transmission. Write request packet to connect via this sequence

F Additional or another selection order includes receiving the structure command, receiving the peripheral parts interface, bus command, selecting multiple 7, output / input (I / O) commands, and memory, and transmitting i data. The peripheral parts interface bus command, so the in々dagger on the link maps each of these different types of commands J through forcing so that contains different types of commands

Page 18 486633 was transmitted. Merge these pass / roll-in (I / O) receive these multiple receive these sinks in their respective order. Send the peripheral parts of this bus to the main address to respond to this bus. This command should be packaged to this order. It is best to include the second peripheral zero-declaration memory. 5. The data packet of the invention description (14) is better on this channel. To specify, this command includes the structure of the part interface bus and the respective address ranges in the output room. Additionally or alternatively, receiving the bus command includes transmitting the data packets in a continuous sequence, including storing these bus commands between the data packets. Additionally or alternatively, transmitting the bus command in the form of The second response is to the channel that received the packet. Preferably, the destination device receives a response on the part interface bus, and this link sends a target address on the return bus containing the response. More preferably, the peripheral part receives a delayed processing request, and then completes the extended writing, and the service writes the announcement memory before transmitting the bus. This includes placing this deferred processing request in one of these buffer memories and allowing this memory. The channel and the peripheral and memory address are empty, different types of confluences> The IL command, these commands transmitted by the Weigan channel include the decision to transmit on this bus via this second peripheral command, and via the second 2. The peripheral part interface interface bus command includes receiving-if the processing is delayed, the memory is announced, the delay processing is completed, and the delay processing is sent to the bus command interface. The bus interface writes over the buffer according to a preferred embodiment of the present invention. Provide a device bridged between the first and second parallel busbars, with a common set of busbar processing

486633 V. Description of the invention (15) The order and control of the execution of these processes are controlled. The device includes: a target channel transfer benefit, a target address set on the first bus receives a bus command, and combines this In one of the processing combinations, the ^ command is issued by a source device on the first bus for execution by a destination device on the ^ = bus and generates a data packet containing the received bus command; and A network interface adapter configured to transmit this lean packet to a primary address on this second bus via a packet-switched network, so that the ^ t ^ ί address responds to the received data packet, & Follow this order! t 苐 The second bus to this destination device sends the bus command. Preferably, the one-bit address range includes one address space on the first bus, and the target address is assigned to the target channel adapter. More preferably, the device maps through: and each address clock ^% of this packet to the row containing the mapped target address r The multiple address ranges are included in the first confluent address space -Individual address ranges. Bus command, =, this bus command includes-the sent bus giant channel == packet includes-the data packet sent out, and one of the target star points, the bus command issued by Gan and Li, and is reflected; = received here This channel for sending packets on the first bus; and, the address of the u order to the one to send this ^ is suitable for receiving from this second bus on this

Page 20 V. Description of the invention (16) The packet transmitted by another channel of the network is applicable to the address that maps the first packet of this other channel and responds to this entry, and is applicable to the transmission-entry 2 this brother-bus Upper—The packet for positioning. ° 卩 7 This gives the location address in response to this entry. Additional or another option is used to install this for this purpose. The "row" command includes 1 fetch command adapter, which is suitable for generating-net, and responds to this read command. '; In the preferred embodiment, the request packet is fetched and in this network, the fetch request packet includes a read including: 1; the target communication adapter includes ... Among them, the private command is called early, and the read command that comes back is applicable to two: = This first stream is a key unit, which is suitable for ί: ;; :: 1 to fetch the request packet; to:-transfer on the bus- Enter: =: Read the packet. It is better to apply this command. This master ^ is a command. F This 3-input read command: :: f: The incoming read data is sent here as a reply. The second bus response packet contains the received: Dao-send out the write please write eight commands, this is known as including * · packet, and this target

5019 ^ 3607-PF.ptd Page 21 is executed by the destination device: Include the write command for the backflow command-write command 'applicable to generate-network write addiction; block J into the command in this target channel transfer example 'This write is transmitted on this network. In the description of the invention (17), a target unit writes a main one and enters a bus root in parallel. There are buses and second sources in the sequence space. The first and the buses and the second and the second are installed. The data is sealed so far and the second entry order and ασ are early. The writing envelope of the data is transmitted according to the invention. The bus and the bus control control the execution of the target channel—and the communication. The target address is one or more. The main address packet of the second network transfer data packet that is issued with a second purpose command is installed according to other purposes according to the present invention. The peripheral part is suitable for the package and is one of the first and the second one. OK, the second position of this adapter is suitable for receiving sink processing and is set by the device first and the first, respectively, so that the order is set for transmission, which is more used for receiving. The preferred embodiment of the write command, the second target advection processing device includes:, which specifies this address range to be divided into this second order command, because Separate in the first row, and apply the two data packets to the first and the first, respectively, so that the main rule is passed through this embodiment of the bus, and the packets on the first bus are installed between the buses. The write request packet; and the write packet transmitted by this second bus is applicable to this number. It also provides a device that bridges between the buses of a bank, the common combination and the source bus of these processes. One address category and the first and second destinations within the first and second ranges of the first and second bus commands combined with at least one and the second destination on the set of source buses to generate packets; and another sequence with two destinations The sink address returns the received bus on the bus with the received node to transmit the first and second target bus orders received on the first bus. It also provides a bridge to the _, including: interface sink

486633

V. Description of the invention (18) A target channel adapter, suitable for receiving a peripheral component interface bus command at a target address on the first peripheral component interface bus, 1 to 7 This command is due to the first A source device on a peripheral part interface bus issued this command to instruct a second item on the second peripheral part interface bus ^ μ 'Μ I set the pre-processing of a peripheral part interface bus, and it is suitable to generate Data packet for receiving confluence order from brother; and '^

A network adapter configured to send this data packet to a primary address on the second peripheral component interface bus through a serial link, so that this primary address responds to the received data packet in accordance with the peripheral component interface The order rule transmits the bus command through the bus of the second peripheral part interface to the destination device. In a preferred implementation, the bus sent out specifies the target unit, and the data packet sent out here, H5 — the single packet, the incoming packet, and the bus sent on the bus is sent on the bus. The figure is obvious and easy to match with the simple description: In order to make the present invention understand 'the attached figure', this data packet includes a data packet channel adapter including: it is suitable for receiving the first peripheral parts The interface bus peripheral part interface bus command is suitable for generating; and it is suitable for receiving packets from this second bus and responding to this entry, and is applicable to the peripheral part interface bus command entered here. And preferred embodiments to illustrate the invention.

^ The above and other purposes, features, and advantages can be explained as follows:

486633 V. Description of the invention (19) Figure 1 is a block diagram illustrating a system bridged between parallel buses on a multi-channel packet-switched network in a preferred embodiment of the present invention. Fig. 2 is a block diagram illustrating the detailed construction of a bridge device in the system of Fig. 1 in a preferred embodiment of the present invention. Fig. 3 is a flowchart illustrating a method for implementing a reading process on a bridge in a preferred embodiment of the present invention. FIG. 4 is a flowchart illustrating a method for transmitting a bus command via a packet-switched network in a preferred embodiment of the present invention.

FIG. 5 is a flowchart illustrating a method for serving a received bus read request via a packet-switched network in a preferred embodiment of the present invention. Fig. 6 is a block diagram illustrating a more detailed construction of the bridging device of Fig. 2 in a preferred embodiment of the present invention. Explanation of symbols 2 0 ~ network system; 28, 32, 38 ~ bridge device; 22, 34, 40 ~ peripheral component interface bus; 3 0 ~ infinite band packet switching network; 26 ~ peripheral and output / input ( I / O) device; 36, 42 ~ target peripheral device; 24 ~ central processing unit; 50 ~ target channel adapter; 52 ~ switch;

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^ OOOJJ

54 ~ PCI target unit (PCIT); 56 ~ PCI master control unit (pciM); 58, 60 ~ buffer memory; i3〇 ~ first-in-first-out (FIFO) queue; e ~ write request; 134 ~ ruler Father Jiaguan Example: An example of the peripheral part interface (periph㈣i c⑽p〇_t) that is widely connected to Xilu in the present invention-the preferred embodiment-is illustrated on the system diagram.

(PCI) bus block diagram of buses 22, 34, and 40. Each pci i is connected to an infinite frequency band by a bridge device 28, 32 or 38. 1 2 IB) packet-switched network 30, each pair of bridge devices and one bridge between the buses pci_t0_pci (p2p) bridge τπ, a better implementation example will refer to the PCI bus and the IB network The principle of the invention can be applied to bridges of other types of parallel exchanges, and it is applied to packet-switched networks that comply with different standards.

In the example shown in Figure 1, one of the main devices on the bus 22, taxi-central processing unit (cpu) 24, is to read from or write to the bus 34 taxi-target peripheral device 36, The main device issues an appropriate PCI: order an address located in the address space of the PCI bus 22, this address is allocated to the bridge device 28, and the remaining PCI bus 22 address space is allocated to the hidden bus Peripheral and output / input (ί / 〇) device 26 on 22. Another device 28 generates-16 commands based on the CPU request and transmits / communicates to the bridge device 32 via the network 30. The bridge device 32 decodes the β command and generates a report. The PCI bus command is transmitted to the peripheral device via the bus 34. ", Field dress

486633 V. Description of the invention (21) Return the appropriate response (data, the condition of a read command, one of the writer's order) to the bridge device 36. The bridge device 36 generates a 15f packet and sends the response packet back to the bridge device 28 through the network 30. The selection device 28 sends the response packet to the CPU via the bus 22. Coincidentally, according to the PCI standard, each device on the bus 22 may have multiple addresses " windows ", or sections, allocated to it in the address space of each memory and structure on the bus 22. It is preferably , 16 of these windows in each of the 3 address spaces are allocated to the bridge 2. More or fewer windows can be allocated. The configuration and definition of these sections are duplicated: Point is description In the title of the above patent application "Platform Bus Communication via Packet Switching Module", regarding the start and side of System 20: 36, this address is assigned to Erzhi, Inside the viewing tunnel. The KCPU therefore addresses all memory read and write commands to the device on 2 bus 34 to ρπ memory address empty J: the appropriate memory window of bridge device 28; all structures read and write to the PCI structure address The appropriate structure window 2 of the bridge device 28 in the space and all I / O read and write commands to the appropriate structure window of the bridge clothes 2f in the PCI structure address space. Optionally, in the 2 8 t window allocated to the bridge device, there is also a window combined with the channel through the network 30 to the bridge device 32 to address the peripheral device 42 on the bus 40, which is not shown in the figure. Additional PC I bus. The address windows assigned to the bridging device 28 are combined with a different channel, or a work queue pair (work queue, WQp) in the IB network 30. As described above, each channel in the IB network 30 passes through Network maps to a fixed road

V. Description of the invention (22) and service level, and the right way of the packet's right hand shake '+ + 丨 Zhen Xu, a similar method of holding the order of the packets carried in a given channel is a known technology, Known in other types of networks. This channel and the write request to the PCI bus 34 (彳 _Μ 4 ,, 'one of all 5 shells identified as 48 s / (hidden limb, structure or 丨 / 〇) address space here: by the bridge device In order to receive 32, they are transmitted by the bridge device 28. The response from the peripheral device db is similarly returned to $ 24 and returned to the CPU 24. The bridge is set to 32 and in the correct order, f is set to 2 and 8 Figure 2 shows an example of a block diagram of a bridge made of two in the preferred embodiment of the present invention. The structure of the devices 32 and 38 is also the same as shown in Figure Ch. Connector (Target device 5PγΓγ ^, Γ ΚΑ) 5! And a switch 52, the target channel is transferred to two for six secrets β a pen and row 22, the switch is coupled to the network 30. This purpose, ° Brother Ming in the above patent application numbers 60/1 52, 849 and 60/175, 339 'The design of the switch 52 is beyond the scope of this patent application, but 32! Packet exchange meets the infinite band specification, or at least -Pass = characteristics of packet sequence 'will be applicable to implement the function of switch 5 2 0 TCA 50 疋 as a conversion PCI command (or loop) to enter IB Package, and vice versa. The TCA includes a PCI target unit (pciT) 54 and a ρ (: ι master control unit = （(PCIM) 56, PCIT 54 responds to the second from the π bus μ. It is initialized by a bus master, such as CPU 24. In particular: PC 1 T receives read and write commands by PC I bus and generates appropriate IB read and write packets for transmission via switch 52. When transmitted by the target Bus receives back

486633 V. Description of the invention (23) 1 packet UCIT 24 receives these packets and generates a suitable response loop on the PCI bus 22 (returning data in response to a read request or a write request. On the one hand, PCiM 56 is In order to receive the IB Nito :: Λ packets from the network 30, 1 β read and write request packets are transmitted by the -remote source & master control device. PCIM 56 converts these requests to become appropriate on bus 22 Read and write commands, this example is the target bus. The response generated after PCIM is archived to return to the originating bus. Figure 3 illustrates the implementation on the ib network in a preferred embodiment of the present invention. A PC; [Flow chart of the method of reading processing. In a reading request step 70 ', the CPU 24 sends a reading command, which refers to the setting 36. As described above, the CPU sends a request to a bit address, This address is in an appropriate window within the address space of bus 22 allocated TCA 50—address 0

In a confirmation step 72, the PC IT 54 uses a PCI "to retry, and responds to the central processing unit (cpu) 24 on the bus 22 in response to the read request, informing the CPU that the requested data is not yet available, so the CPU should retry this later As mentioned above, ^ ▲ The CPU issues a declared memory write (pwm) command. PC IT immediately confirms this command. The CPU must continue to retry non-declared read and write requests until it receives a request from the target. The delayed response of bus 3 4 is ^. When it sends a retry response, PC IT records this read request in a buffer memory 58 and allocates space to receive the read response expected from device 36. Data. The read request is recorded in the buffer memory with sufficient confirmation information so PCIT will be able to contact the read response packet. The read response packet = the CPU received a special read request from device 36. Dagger

5019-3607-PF.ptd Page 28 486633 V. Description of the invention (24) As shown in Table 1 above, the CPU 24 can transmit 5 different types of PC I read requests. In step 74 of a packet transmission, according to the read The type and address of the request, the PCIT generates an appropriate IB Remote Direct Memory Access (RDMA) read request packet, and transmits the packet to the switch 52. The PCIT issues β RDMA in a precise sequence, in which it receives eight orders from the confrontation of the bus 22. Under the PCU fetch command, the PCI address is mapped to a fixed virtual address (and logical address), and the corresponding IB read request is marked to the bridge device 32 on the bus 34 and from there to the peripheral device 36. ^ The other point of view that the PCI command is mapped to the IB request and the network channel is to explain in the above patent application title | · Parallel bus communication via packet-switched module; The request packet is obtained by bridging the device 32. For the purpose, other designs of the heterogeneous device 32 are also possible. The second embodiment is generally consistent with the device 28. (In fact, the best implementation provided by the Taiyizhi 32i structure between the PCI address window and the IB channel is the best implementation of the different types of bridges on the bus. The advantage is- It is not specific or private to the bridging device. Furthermore, the information in the packet to any Iβ-accepted termination-points, such as the network 30, can be used to send packets, not just other bridging devices.) In the receiving-I / O controller, = 52 sends a packet to %% of this device, in the buffer memory 60 at the intersection of device 32, t correction, six ^ It places this request on one, t to the bus can Serving this request // on 486633 V. Description of the invention (25) The PCIM 56 of the device 32 maps the channel and virtual address of the IB packet to the physical address of the PCI peripheral device 36 of the bus 34. According to the channel and data length of the RDMA packet, the PCIM selects the appropriate type of the PCI read command to talk to the peripheral device, and receives the request data in accordance with the PC I bus process. The pC JM generates an IB read response packet to return to桥 装置 28。 The bridge device 28. In a response transmission step 80, the response packet is submitted to the switch 52 and transmitted by the switch 52 via the network 30. Before the next read or write request in the service buffer memory 60, the PCI M transmits a read response packet to complete a delayed read transaction (DRC), and a delayed write completion (DWC) ) Confirmation is equally given priority over newly outstanding requests. In a response receiving step 82, when the IB reads the response packet back to the bridge device 28, the switch 52 sends it to the pc IT 54, and the PC IT 54 buffers and stores this data. The PC IT compares the response information with the pending request in the buffer memory 58 and retries the currently completed delayed read request (DRR) from the buffer memory. In a data transfer step 84 ', when the CPU 24 next retries the read request, the pcn 54 transmits the received data via the bus 22 to cp [J. When any posted memory write (PMW) command is issued on the pci bus 22

While the response data is waiting in the buffer memory, pcIT 54 will not attempt to place the data on the bus until the PMW is completed to ensure compliance with the pci processing sequence rules. Figure 4 is a flowchart illustrating a method for converting a PCI bus command into an IB packet in a preferred embodiment of the present invention. This conversion is

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486633 V. Description of the invention (26) Step 74 of the second application], which enables the writing of 9 different types, please ask the stomach to seal the bag. Table 1 is mapped to the appropriate reading and packet exchange module on the 1B network for transmission. In the message agreement, the male jaw i < responds. This packet type is combined with the IB communication protocol to extend the transmission. Header Extended Transport

Header, ΕΤΗ) to specify, read and write operations are performed directly by a remote end = = ire :: M_y AcCesS, _) ΕΤΗ ;: The first message requested by the Lu address is written to include two RDMA ΕΤΗ designation — f iUi :, an access key (R-key) and the data buffer memory (which may be connected, A write packet) load. The receiver writes a response to a disc acknowledgement packet, and has a read acknowledgement ETH (Acknowiedge eth): ΑΕΤΗ also appears in the read response packet returned by an entity receiving the read request. This read response packet also has a payload containing the requested data. Techniques of known techniques will identify packet types and operations similar to these other techniques known to also occur in packet switched networks. In a loop receiving step 90, the bridge device 28 instead of 17 54 receives a read or write command on the PC I bus. In the address space determination step 92, the PC IT checks which of the three PC I address spaces is addressed by the command: memory, structure, or I / O cPCIT determines one of the on-channel packets on the channel by address space It is transmitted, therefore, in a 1/0 packet generation step 94, if the address is in the I / O space, an RDMA read or write packet is transmitted on the channel, such as ". In this example, the data buffer storage One of the length will not be greater than

5019-3607-PF.ptd Page 31 486633 V. Description of the invention (27) 32-bit 'conforms to the PCI agreement. (The number of channels and the number of other channels referenced below are arbitrarily selected for example.) In a structured packet generation step 96, on the other hand, if the address is in the structure space, the corresponding RDMA read or write The packet is transmitted on the channel ". In this example, the length of the data buffer will be no more than 4 bytes, as the main device (cpu 24) indicated by the Byte Enable (BE) bit The written bit conforms to the PCI protocol. In a memory packet selection step 98, if the generation 1 bus command address is in the PCI bus memory space, the corresponding "read or write packet is specified on the channel" C ". ] ^ A packet is generated depending on whether it carries a read or write request. As shown in Table 1, there are two types of memory write processing and write, and write without effect. In an invalid step 100, it is determined whether the current cycle is a write and an invalid cycle. If so, the MWI setting step 102, the dedicated memory write and invalid (MWI) bit is set in the structure part of the R]) MA write. In a write packet transmission step 104, one of the data J given by the actual data length specified by the pC 丨 耷 command is packed into the packet. Regarding the memory and I / O write commands, you do n’t want to use a private packet to translate the H packet, which does not explicitly specify one of the buses 34 1 to find the address 1 to the address. The bridge device w μ maps the PCI command generated to one of the destination devices 36 after the user places it on the other hand. On the other hand, the structure write command is better than # 玎 绪 廿.

1 Native use—IR enters the packet and specifies the bit of data to be written on the bus 34. KDMA write Yes' The PCI write command can be mapped to IB write or IB address. Another option depends on the interaction between the main device 24 and the destination device 36. Better mapping in each case

5019-3607-PF.ptd Page 32 V. Description of the Invention (28) The IB channel specified for the combination. Right reading] ^ Sealing command, an RDMa reading command, step 1 06, if a pci memory is encountered to read the data in the packet = the packet is transmitted on channel C. In this example, RDMA is determined. For the memory ^ ^, the PCI memory uses the read type and length to quickly store the read row. The data length is read by the main device 24 under the memory. ^ Of = the length of the memory to be read To decide. Yes The length of the data to be read is determined by the next page boundary in the memory.

P-IB RDMA read request encapsulation f Flow chart of conversion in a preferred embodiment of the present invention. This conversion 4. The packet becomes-the method of the PC1 bus read command. It is further explained in step 78 in the method of the above-mentioned patent 3, the bus communication. In a 3 'question', the packet is received by the PCIM 56 in parallel with the packet switching module. In the $ receiving step 1 10, the read request packet is the IB channel of the borrowed packet. First, the decision step U2, the PCIM checks the receiving When receiving, the PCIM sends step U4, if the packet is set on channel eight. Similarly, the -Make ^ fetch command to the appropriate device on the bus 1 to receive, the PCIM sends-: structure: take step 116, if the packet It is generated on the same side on channel B; the stomach fetch command ° 1 / 〇 and the structure write command are read commands if the RDMA read requests the county, animal, and Memories. Received on c, which corresponds to the data length determination of the packet: the second length check step 118, PCIM 56 according to IB eight yv λ. '' c I what kind of read command is issued on the bus. In a read step 12Q, I issued in '~ Jing fetch-simple PCI memory continued; in 4: where the group' is, take the command. Steps 1 2 2 in a read column,

5019-3607-PF.ptd Page 33 486633 V. Description of the invention (29) If the data length is greater than 4 bytes, but does not cross the column boundary, pc IM issues a memory to read the column can be determined The cache transfer entry takes step 124 if the data length is greater than 4 bits. In ~ more than the column boundary of a fast buffer storage area, pciM must; take 1 to buy data across read multiple columns command. Dandruff

16 read requests on channel C (not shown in this picture: 'ΡΓΤ 56 sends appropriate memory writes on the PCI bus 2 PClM Mm liters are set, and the packet information includes fast: punch = packet pair If there is a fast memory in one bit and one sub-m, the PCIM will issue a memory write and invalid command. The coincidence of the storage area is ordinary memory write command. Therefore, all different types' Then Jie issued ~ The write operation is mapped to the IB RDMA read and write request packet, and the target bus is converted back to the appropriate type of PC! Operation. After that, FIG. 6 illustrates an example in the present invention. A preferred embodiment of the PCIS control unit (PCIM) 56 and its associated buffer memory 60. = PCIM 56 receives any delay request (DRR or dwr) on the IB network 30 This request is placed in the buffer memory 60, preferably in a first (FIFO) queue 130. If this queue overflows, the PCIM preferably informs the sending PCIT that it has discarded additional RDMA request packets And pciT will then packetize. On the other hand, when PCIM 56 receives an announcement write When requesting 132, Α will not enter this request into buffer memory 60, but let it pass directly to transmit it to the PC I plaque stream. A arbiter 1 34 gives priority to request 1 3 2 ' This priority applies to all pending pending buffers

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486633 V. Priority of the claim of invention description (30). Therefore, when a PMW arrives at PCIM 56, it is always allowed to go over the pending commands waiting in the buffer memory with & DWRs. Similarly, if there are any outstanding PMWs waiting in PCIM 56, DRCs and DRWs are not allowed to cross to ^ 50. However, delayed completion packets are allowed to go over previous-arrival delayed request packets. In a nutshell, the reference table is listed in 7 of the background of the invention? (: 1 sequence rule, I see the operation of PCIM 56, especially the official mechanism listed in the i60, and ensure that the bridge complies with rules 5 and 6, that is, PMWs, DRCs and DWCs 2 may exceed DRRs and DWRS. In addition, because ρπτ 54 and 16 networks save the read and write commands received via the PCi bus, PMW will not surpass any basin # 彳 彳 + nq Λ "7 other processing 'therefore Will abide by rule 1. After the defect, the PCIT 54 buffer memory receives DRCs and DWCs from the destination bridge = f, and until any # candidate g is completed, the corresponding PCI bus will be listed on the rules 4 and 7. Therefore System 2. Compliant -P2P Bridge Part 2: Compliance 2 Extra obtained by bridging to the IB network 30. When anyone is familiar with this skill, the system 20 is obviously suitable for situations where the proper method can be used Where there is a need for network, processing, and ordering rules to replace it. Although the present invention has been limited to the present invention with a better implementation, anyone skilled in this technology will not use it within the scope. When it can be done a little bit more, and it will not depart from the spirit of the present invention Attachment of the following claims and the protection scope of this present invention ^ v ^ dead whichever piece goods sector.

Claims (1)

486633 Scope of patent application ^ An ordinary bridge that bridges the processing of a bus between the _th and second parallel buses. This method includes: The sequence rule controls the execution of the target address reception-bus command In combination with the line ", the output is used to transmit the data packet to the first bus by the destination device on the second bus—the destination device on the network transmits the target bit bus command on the first bus. The second king wants the address; and the rule passes you α α2 through the second bus. · The method as described in item 1 of the scope of patent application, wherein the first booklet bus includes a peripheral part interface bus. ^ 3 The method as described in item 2 of Shenjing's patent scope, wherein the transmutable network includes an infinite band network 12: bit ,: the data packets that should be received, in accordance with this order, the method is 6 μ s-α acknowledges that the bus command is not provided. The first and the packet are the method described in item 1 of Shenyan's patent scope, wherein receiving the bus command at the destination address includes specifying the first Bus up to one An address range in an address space of the bridge device to communicate with the second bus, the address range includes the target address. The method as described in item 4 of the patent application range, wherein the address is specified The range includes designating multiple address ranges: the bridging device, and mapping the respective address ranges to one of the networks, each of which is unique, and wherein transmitting the packet includes transmitting the packet through the channel, including the address. Map destination address 36th tribute 6. The scope of the patent application-the address range. β · As described in the application for the application of the faecal benefits, the multiple address ranges include the method described in Item 5 of Item 5, where 'specifies the respective address ranges in each of the plurality of address spaces. A method as described in claim 6 of the patent application, wherein the plurality is between. The address space includes memory, structure, and output / input (1/0) address space-8 The method as described in item 6 of the patent claim range, wherein transmitting the bus command via the f two bus includes mapping The pass-through receiving the packet is forced to an address space of a plurality of address spaces on the second bus. Ren-9 The method as described in item 5 of the scope of patent application, wherein receiving the: 7 includes receiving one or more addresses at one or more addresses within one of the specified ranges and mapping the The target address range includes mapping all one or more addresses in the range to the same channel so that the packets are transmitted through the channel of the network in the order in which they are received by the bridge device. 1 0. The method as described in any one of the above patent claims, wherein 'receiving the bus command includes receiving a read command for execution by a destination device' and wherein transmitting the data packet includes transmitting a network read Yan too seeking for packets. a 11. The method as described in claim 10 of the scope of patent application, wherein receiving the read command includes receiving a command to read a given amount of data by a recording medium combined with the destination device, and transmitting the The network read request packet ^ includes setting a data length area response in the read request packet ^ ^, 〇 疋 5019-3607-PF.ptd Page 37 The method described in the above item, wherein receiving a receive command to read a memory from a memory, please take it to the buffer store, send it back to the application, and send back the application, including receiving and delaying the packet, and receiving the execution of the application. package. 12 · If the command is sold by word or multiple quick catch 13 · If the device is transmitted at the main main address 14 · If the read command bus command data is returned 15 · If so, the destination device writes The amount of 1st $ 1 in the request for profit includes the deposit area. The benefit range 10 includes the second range response packet containing the profit range 1 3 and the first response and the late transmission of the first response range of the patent range bus command and the method described in the transfer item. The stream receives data, and the data received by the network goes to the destination address. The method described in item 2, wherein two read commands are received, and wherein the two read commands are transmitted until the received read command is transmitted. The party described in any of items 1 to 9 includes receiving a write command to transmit a network by the data packet —A '· The method described in claim 15 of the scope of the patent application, further comprising: The destination device that executes the write command receives a confirmation via the second bus at the main address' and the main position of the network A response packet sent back to the address should be confirmed to the destination address. 1 7 · The method described in any one of item 9 of the above-mentioned application patent scope where 'receiving' the bus command packet is received, a request is received to perform a delay processing on the second bus, and the delay processing is continued before completion of the delay processing. A "declaration process on the second bus is performed by a request, and wherein transmitting the bus command includes servicing the announcement process before completing the deferred process. 486633 VI. Declaring the patent scope 1 8 · The method described in item 7 of the patent application scope, wherein transmitting the bus command includes placing the delayed processing request in a buffer memory of the main address, and The announcement processing request is allowed to cross the buffer memory.口 19 • The method as described in item 7 of the scope of patent application, further comprising receiving a response to the delayed processing request via the second bus at the primary address, and by the primary bit before receiving the announcement processing request. The address sends a response packet containing the response to the target address via the second bus, wherein servicing the announcement processing includes placing the response in a buffer storage of the target address ^ and transmitting the response only after servicing the announcement processing Respond to the source device. °° 20 · The method according to any one of item 9 of the above-mentioned patent application scope, wherein receiving the bus command includes receiving a request to perform a declaration process on a second bus, and then continuing to complete the declaration process With = request to perform another process on the second bus, and its ^: command includes ensuring that the stream is completed before serving the other process. 2 1 · —An ancient bridge that bridges between a source parallel bus and the first parallel bus _ ^ ^ ^ ^ ^ 'The ordinary group of people who have only been shown at a glance for a long time and $ Zu, Jin ~ Xunli, Xi, L The bus has a bus processing including Yi ,, ', and the order rule control execution of this temple processing. This method package includes:-: Π: j from the original bus to an address space of a bridge; and Brother address range to communicate with the first and second target bus respectively 486633 Sixth, the scope of the patent application, order, the bus command combines one or more of the combinations and is processed by the at least / source device on the source bus to send the The first and second destination devices on the two target buses are executed; the bridging device transmits the first and second data packets containing the received bus command through the respective serial links to the first and second targets respectively The first and second primary addresses on the bus; and the data packets corresponding to the received data at the primary address, and the buses are transmitted through the first and second destination buses # to the respective destination devices in accordance with the sequence rule Row command. 2 2 · The method described in item 21 of the scope of patent application, wherein the sequence link includes a path through a packet-switched network. 23. The method as described in claim 22, wherein designating the first and second address ranges includes mapping the respective first and second address ranges to the respective first and second addresses on the Xuan network ^ __ And the second channel 'and transmitting the packet includes transmitting the first and second data packets via the first and second channels, respectively. 24 · Method —A common combination with a bus process and a sequence rule control of these processes bridged between the buses of the first and second peripheral parts interface. This method includes: a target position on the bus of the -peripheral parts interface The address receives a peripheral component interface hidden bus command. The μ command is issued by the-source device on the first-peripheral component interface bus. The command refers to the-target device on the second peripheral component interface bus to achieve 〆 peripheral components. Interface bus 5019.3607.PF.ptd Page 40 486633 6. Application scope of patent; The target address of the bus at the first peripheral component interface transmits a data packet containing one of the received bus commands to the first via a serial link. One of the main addresses on the peripheral device interface bus; and responding to the received data packet at the primary address, and transmitting the bus through the second peripheral device interface bus to the destination device according to the peripheral device interface order rule command. 25. The method according to item 24 of the scope of patent application, wherein the sequence link includes a channel via a packet-switched network. 26. The method according to item 25 of the scope of patent application, wherein the packet switched network includes an infinite frequency band network. 27. The method according to item 24 of the scope of patent application, wherein receiving the peripheral military interface interface bus command includes receiving a structure read, an output / input (I / 0) read, a memory read, a memory Read multiple read commands and select multiple types of peripheral component interface bus read commands from the multi-fetch command, and transmitting the data packet includes mapping the multi-types to a single-type fetch request packet to link through the sequence. transmission. a 2 8 · The method as described in item 27 of Shenjing's patent scope, wherein mapping the multiple types includes specifying structure reading, output / round-in (1 / 〇) reading, and taking memory items to the sequence The connected different channels on which the read request packet corresponds to the command to be transferred. & 29. The method as described in claim 27, wherein mapping the multiple types includes specifying a value to one of the data hand regions in the read request packet in response to whether the command includes, memory read Fetch, memory read 486633 6. Scope of patent application Multiple commands for reading columns or memory. 30. The method described in any one of claims 24-29 of the scope of the patent application 'wherein' receiving the peripheral part interface bus command includes receiving a structure write, a rotation out / input (I / 0) write, a memory Write and memory write and invalid commands select multiple types of peripheral part interface bus write commands', and transmitting the data packet includes mapping the multiple honey-spirit orders — $-type write request packets to pass The sequence is concatenated for transmission. 31. The method as described in any one of items 24-29 of the scope of patent application ^ ί 中 'Receiving the peripheral part interface bus command includes receiving a structure command, a wheel-out / roll-in (I / O) command, and a memory In the command, multiple / different types of peripheral parts interface bus commands are selected, and transmitting the lean packet includes mapping each command of the different types to different channels on the link so that it contains data of different types of commands Packets are transmitted on the respective channels. 'The method described in item 31 of the scope of patent application, wherein' refers to 疋 j π 7 including the combination of the channels and the busbars of the first peripheral part interface bus-out / roll-in (1/0) and Individual address ranges in the memory address space. The method as described in item 31 of the scope of patent application, wherein receiving the heavy and different types of bus commands includes receiving in a continuous order, waiting for the bus commands, and transmitting the data packet includes saving the Boy, the bus order between the data packets transmitted in the respective channels. Scope of patent application --- _. The bus command includes the 零件 l side parts interface 泣 零件The model responds to the channel receiving the packet by uploading a packet in the second week 3, A / Gua. In addition, please carry out any of the methods described in the patent scope Nos. 24-29. The interface interface method ^ Sang placed at the main address via the second peripheral component knot should be sent in response to the bus command, via the company's 3M The response packet is returned to the target address on the second peripheral device interface bus. Door, complex = · The method described in any of the items in the scope of the application for patents Nos. 24-29 侩 processing Xu electrical connection Ϊ = edge parts interface bus command includes receiving-delayed entry, Ming '' ## before the delay processing is completed Following the announcement memory write service, the communication of the bus command includes reading the announcement memory write before the delay processing is completed. The sink 2. The method as described in item 36 of the scope of patent application, wherein transmitting the mediation bus command includes placing the delayed processing request in a buffer memory of the second peripheral part I bus, and allowing the Declares memory writes across the buffer. There is a 38 · A device bridged between the first and second parallel busbars, a common joint with rod bus level processing and the order rule control of these processing 'This device includes: a target channel adapter , Which is set to the target person day on the first bus, a bus command 'combined with one of the processing in the processing combination, the command is ordered 1 :: Since one of the source devices on the * bus is issued, By means of:-the excavation-destination device executes and generates a lean packet containing one of the received 7; and Patent application scope 4-network interface: data packet to the main address back to the second sink 39 'as applied-and the second parallel sink 40 · as the application packet exchange 彳 1 ~ style network package ^ ^ • Rushen Gulu Road interface adapter package 40 address range application "said to reach the target 43 · Rushen Lun site Fan Yuan package decay Γ: Map to, f Xi Ge Lai 5 Hai network via the ii $ π / Communication address. If you apply for a solid address RA, this address is included—each address is 45. If you apply for an S address space package, please set up via a packet exchange network. The main address on the bus is uploaded on the road, so that the received data packet 'transmits the bus command according to the order of the destination device. The device described in item 38, wherein the enclosed peripheral part interface bus. The device described in item 39, wherein the poor frequency band network. The device described in item 38, wherein the network converter. V ... The device described in item 38, in which one The target address adapter in a address space on a bus, the second application Each of the listed patents includes a patent list, a patent-free list, and a patent-pass channel adapter. One of the patent-address address ranges encloses the device described in item 42, wherein the bit-range and Each address range uses a channel of the device, so that the network interface adapter to the device described in item 43 of the patent range that includes the mapped target address, wherein more than the first Each of a plurality of address space ranges on the bus. The device described in item 44 of the patent scope, wherein the comprehensive memory, structure, and output / input (1/0) address space Page 44 486633, Patent Application Scope 6 > 46 · The device as described in Item 44 of the Patent Application Scope, wherein the bus command is transmitted via the second bus to the Shanghai * place on the second bus An address space in the address space is to receive the envelope through a mapping: j to an address space of the second bus. μ 47 · The device as described in item 44 of the scope of patent application, wherein the platooner includes a bus command issued, and the data packet "two = outgoing greed = packet, and the target channel is switched The device includes: X- outgoing sink i; and ^ used to receive the channel of the packet sent on the first bus: and the address of the command to the network to which the packet is to be sent ΐ70, which is suitable for receiving packets coming in from one of the packets on the second bus and responding to the address, and for transmitting a channel to the second, bus-to-locating packets. ~ Enter Order to the given address in response to the access to the channel. Hi:;, the device described in item 3, "The target address receives one of a number of life-threatening and sacrifice—or multiple bits. The address to the same ^ ^ is suitable for mapping all one or more receiving orders in the range via the = to make these packets pass to be received at the bridge device. 49. The channel is transmitted as described above. Method, in which the sink: ΐίϋrange 3 "8 any-item device to execute, including a read command to generate a network read test by the purpose r buy command the target channel transfer The device is suitable for the production of monthly clothes packets and is used for this purpose. &Quot; Applicable patent scope 50 · If the order includes a given amount of information in the package 51 · If you want to read the storage area 5 2 · If the fetch command includes an out read, please send a target out fetch to one of the main buses to enter the first bus 5 3 · If you want to apply the unit and apply to the second bus 5 4 The fate-taking unit is the set of the data. 55. If you apply for materials and set the application for a given amount. The application will issue a packet request unit, order and suitable unit. The read row upload application is dedicated to receive and generate an application order. Including the device described in Item 49 of the above-mentioned claim range, wherein the reading is read by a memory combined with the destination device, wherein the target channel adapter is adapted to read data in the Length area The quantity of the device described in item 50, wherein the order is a read command that specifies that one or more fast buffers in the range M 4 to be read from memory ', and which is applicable to the Generate the package that is suitable for receiving packets and responding to the first entry. 5 2 Incoming read response packets as described in the packet item, the read request the target channel to retransmit the first received read receipt from The entry reads the read command. The installation information described in the item contains the received asset ', where the read request packet includes a transceiver including: the request packet on the bus; and the second bus The received packet is suitable for setting, in which the read reading data entered by the master should be transmitted to the device described in the item 53. In the middle, the incoming # = f7 and the second read command, and The master reads the second read command until the first read command is transmitted including the received response. Please refer to any one of the 38-48 patent scope. 5019-3607-PF.ptd page 46 A 'patent-applied device, which is set to perform,-network write 5 6 · If the write included in the A command, please send a target write to the main one Upon entering the first bus 5 7 · If the application is specifically applicable to the first bus, it is suitable for generating a second bus. 'The repatriation should request the application for the packet to be issued exclusively to the packet requesting unit, the ordering unit, and the writing of the unit, the stream is written to the packet, and the write in the profit range', and its application is used to produce its applicable packet and The order to send a packet into the profit range includes the order of the 55th order of the network and the order, and the 56th order of the project should be confirmed when the recipient should send it to the receiver. The write target channel described in the upload wheel ^ The first write in the target channel is from the line described in the incoming command. The write command is used to order the adapter for the purpose of generating a strike. The write request packet includes ~ the adapter includes: a read send request packet on the bus; and the write packet transmitted by the second bus, which is applicable to the 0 device, the main unit enters the command Confirmation and transmission to Zhuang B8 via the network. As described in any one of the 38-48 of the above patent application scope. 'Where' the target channel adapter is suitable for receiving One request to execute: one delay processing on the second bus, followed by completion of the delay processing = a clear request to execute one of the second bus's announcement processing, and it is applicable to serve the announcement before the delay processing deal with. ^ 59 The device according to item 58 of the scope of patent application, wherein the channel adapter includes a buffer memory in which the delayed processing request is placed, and the setting allows the announcement processing request to pass through the buffer storage. Device. 60. The device according to item 58 of the scope of patent application, wherein the item 5019-3607-PF.ptd Page 47 486633 6. The scope of the patent application includes the buffer memory in which the received packets come from the first series: the response packet to the delayed processing request, and Set to keep the response in the buffer memory until the announcement is processed. 61. The device according to any one of the above-mentioned application patent scope items 38-48, wherein the bus command includes receiving a request to perform a declaration process on a second bus, and then continuing to complete the declaration process by A request to perform another process on the first bus, and wherein the target channel adapter is set to service the other process after ensuring that the announcement process is completed. 62 · — A device that bridges between a source parallel bus and the first and second target parallel buses, all of which have a W-combination of bus processing and the sequential rule control of these processing, The device includes: a target channel adapter that specifies first and second address ranges in an address space on the source bus to communicate with the first and second target buses, respectively, and is applicable to A bus command is received at the first and second target addresses within the first and second ranges, respectively. The bus command combines one or more processing in the combination and is due to at least one of the source buses. The source device sends out to be executed by the first and second destination devices on the first and second target buses respectively, and is adapted to generate first and second data packets containing the received bus command; and A network adapter configured to transmit the first and second data packets to the first and second primary addresses on the first and second target buses respectively in respective sequence links, so that Data packet should be received by the return address, in accordance with the rules of the order through the first and second target bus 5019-3607-PF.ptd page 48 () 633 Bus on the first interface bus and applicable and one of the serial data envelope interface links to send the main address package, as described in the bus to item Device, one channel of the network. The device described in item, Internet. / 、、 Patent application scope 1 The device for each purpose transmits the confluence 6 3 · If the patent application scope No. 6 2 column link includes a packet exchange type 64 · If the patent application scope No. 63 The ticket channel adapter is suitable for two Map the respective first and second channels on the first, if the package is connected to the first and second devices via the first and second channels respectively, 65. One kind of bridge, including: a mesh channel adapter, suitable for row The purpose of receiving a peripheral zero at the address is through the first peripheral part interface sink command to instruct the second peripheral part interface peripheral part interface bus processing, the data packet of the bus command; with a network adapter, Set the bus to the second peripheral part interface bus at the main address and respond to the received surface order rule to send the bus command through the second peripheral zero. 6 6 · If the patent application scope, the 65th column link includes a packet exchange type β 7 · If the patent application scope, the 6th packet parent switching network includes an infinite frequency band ordering command. The device described in item, wherein the sequence is a network path. The device described in item 1, wherein the first and second address ranges to the network. This causes the first and second data to be transmitted in a sealed channel. One of the peripheral parts interface bus command. One of the commands is issued by the source device. The previous destination device is implemented to generate a packet containing the received data, so that the peripheral parts are introduced to the destination device. In the order, the seal Φ Φ 5019-3607-PF.ptd p. 49 486633, 'Applicable patent range edge dress $ 丄 The dress set as described in item 65 of the patent application range, wherein the weekly reading ^ ^ surface bus command includes reading from the structure, Rotate Out / Input (I / O) Qin, ^ Memory read, memory read line and memory multiple read command: ί: ίThe part interface bus read command, which makes the target pass 4 = = :: Shoot these multiple types of reading to -Single 1 type, please transfer them through the serial link. Biaotong 6 first 9 = The device described in the patent scope item, in the middle, the current item: the universal force adaptor is suitable for reading the specified structure, among which the j item and the memory are read to the sequence link. Rain In (I / O) 颉 Find the packet corresponding to the command to be transmitted. , ~, Please read 70 on it. If the scope of the patent application is 68, the suppression adapter is applicable to the specified value to the reading factory ", the length of this item is in response to whether the order includes a —: One of the commands is data retrieval or memory reading.... Memory reading, memory reading. For example, the scope of patent application ranges from 65 to 70. Among them, the interface of the peripheral parts converges to one of the eighth. The input / output (I / O) write and memory write 7 mentioned above are included, including the structure write, the command selects a peripheral part interface, the memory write, and the invalid channel adapter is suitable for mapping. The multiple 1-in orders, and in which the inbound request requests a packet to pass the sequence = end-of-input type to a single type of write 72. For example, the scope of application for patents 65 ~ 70, where 'the peripheral parts interface is merged and combined The device out / input (I / O) command and the memory command Pt | / included by Ren Renhe are included in the structure command and the input channel adapter. Each command to that link Observation 633 a. Different individual channels on the scope of patent application so that data packets containing different types of commands are transmitted through the respective channels. 73. The device according to item 72 of the scope of patent application, wherein the 4 channels combine the structure of the first peripheral part interface bus, output / input 1/0) and the individual bits in the memory address space Address range. 74. The device according to item 72 of the scope of patent application, wherein the two-way forcing adapter is suitable for receiving the bus commands in a continuous sequence and the target channel adapter is suitable for saving via the The order in which the bus commands between the data packets are transmitted by the respective channels. Wei, ..., 75. The device according to item 72 of the scope of patent application, wherein the bus combination order sent to the bus of the second peripheral part interface is decided to respond to the channel receiving the packet. ， Fu 76 · The device order Γ Γ f peripheral component interface bus command as described in any one of the 65th to 70th of the scope of the patent application includes a bus command issued, including a sent data packet, The target compulsion adapter includes: a target unit, which is suitable for receiving peripheral component interface bus commands issued on the first peripheral component interface sink, and is suitable for generating read and issued data Packets; and, a main unit, which is suitable for receiving packets from one of the second buses, and responding to the packets, and is suitable for transmitting on the second bus— Entering Peripheral Parts Interface® Streaming Command. ^ 77 For example, the device described in item 7 δ of the Ming patent, where the main text is written in response to the ㈣-Zhou 彡 parts ☆ face bus response 486633 6. Scope of patent application The bus command in response to the entry is applicable to generating a response packet containing the response transmitted to the second peripheral part interface bus through the link. 78. The device according to any one of claims 65-70 of the scope of patent application, wherein the target channel adapter is adapted to receive a delay processing request, and continue to announce a memory write before completing the delay processing, and Wherein the device is adapted to service the announcement memory writing before the delay processing is completed. 79. The device as described in item 78 of the patent application scope, wherein the target channel adapter includes a buffer memory in which it is placed. The delay processes the request and allows the announcement processing request to cross the buffer storage. 5019-3607-PF.ptd Page 52