TW482904B - Test method for wait line terminal of communication interface card slot - Google Patents

Abstract

A test method for wait line terminal of communication interface card slot includes the steps of forming a proper electrical connection between the voltage detector and control interface of communication interface card slot, further initializing the communication interface card slot and applying a predefined high voltage, mapping the control address of the communication interface card slot and one address of the voltage detector, then reading the voltage of the wait line terminal on the communication interface card slot and displaying the normal status of wait line if the voltage value is on high order and displaying the abnormal status of wait line if not. By means of the test method of the invention, the implementation of test circuit is simplified and the reliability is enhanced, thus significantly reducing the implementation cost for testing the communication interface card.

Description

482904 V. Description of the invention (l) Field of the invention: The present invention relates to a method for testing a waiting line terminal on a communication interface (PCMCIA) card slot, especially a method for testing a terminal terminal voltage by using external hardware. . Background of the invention: The PCMCIA card slot is a standard expansion slot on a notebook computer or similar device. Most expansion devices used to enhance the functionality of notebook computers

It is often necessary to connect to the hardware in the computer through this slot. Generally speaking, the expansion equipment used in the PCMCIA card slot is usually configured as a credit card size but with a larger thickness. Expansion devices include network cards, FAX / MODEM cards, MPEG cards, etc.

On the connection between the PCMCIA card slot and the expansion device, the problem that needs to be resolved is the consistency between the bus access rate of the card slot itself (that is, inside the computer) and the speed set outside the external expansion device. If the speed difference between the two is due to any factor or problem, the wrong data reception or transmission will be inevitable; therefore, in order to solve the aforementioned problem, a special PCMCIA card slot will include a special Wait line / Wait pin. When this line is set outside the expansion device at a speed lower than the bus capture speed, the bus capture cycle will be extended (Bus A ccess C yc 1 e), so that The acquisition speed of the bus is consistent with the speed set by the external expansion device, so that the card slot itself and the expansion device can successfully transfer data; on the contrary, when the speed is set outside the expansion device, it is higher than the bus acquisition speed , This connection will reduce the acquisition cycle of the bus

Page 4 482904 V. Description of the invention (2) period, so that the sink >: is the same. Generally, the first one is to measure the state of the periodic circuit before and after the low precision is used. This is accurate, but it tests the other test party to latch and read the waiting state. It is lower than the previous one, so the voltage at the line is pulled to death, so in fact It works effectively, and the former method is less predominant. Summary of the invention: The PCMCIA communication interface of the present invention controls the on-off state of the program logic, and the degree is greatly reduced.

There are two methods to set the speed of the external charging device and the speed of the external connection ^ = PCMCIA card slot in the waiting terminal state, there are two methods, the exact hardware time measurement q bearing *, ^ ^ circuit, the test waiting for high wiring voltage To determine the cost of using the on-off circuit of the waiting line: :: The water rule of up to nanosecond level is used-open '' $ 广 々 Τ 度 is also large. Ά Lt ^ ^ m ^ S circuit (Switch circuit), the two main lows in the evening, in order to determine the on-off power of the waiting line ...-After the implementation of the method is low, the benefit method is equal to !, but its disadvantage lies in its waiting time. Need to match: One solution: Bu '@Lock cycle leading to the reading cycle-Unlock circuit), the starting point,' Ran its hard ίί: The cost and difficulty of the application department is more complicated and relatively Dike noodles unveil u 1 疋 隹 provides a simple and effective test method for the terminal waiting, the retention Φ a formed by the straight device, the cloud eight series can be used to reduce electricity ^ f 浐, measuring card The implementation of waiting for wiring on the slot: the complexity of the implementation and improving its reliability. 482904 test method of waiting for the terminal on the slot of the communication interface card. 5. Description of the invention (3) The device combination includes a device with a waiting connection. Communication interface card slot, a voltage detector, and a resistor at the end; the connection between the voltage detector and the communication interface card slot at least includes a data connection line for data transmission and a parallel lead-out Communication interface card slot waiting for terminal voltage value Connecting cable; and a resistor, waiting lines for connecting between the slot and the detector voltage differences illustrating a series connection circuit ground, thereby providing a low voltage test for comparison of the time. The method for testing a terminal on a communication interface card slot of the present invention includes the steps of: (1) forming a suitable electrical connection between the voltage detector and the control interface of the communication interface card slot; (2) changing the communication interface card slot Initialize and apply a predetermined high voltage; (3) Correspond to the control address of the communication interface card slot with one of the voltage detector; (4) Read the communication interface card slot from the voltage detector (5) Determine whether the voltage at the terminal is at a high level equivalent to the predetermined high voltage value; if it is, the terminal is normal; if not, the terminal is abnormal; (6) Complete the test of the terminals on the communication interface card slot. In the present invention, the voltage detector may be a chip, a programmable logic controller, or other suitable voltage detection devices. In one embodiment of the present invention, the communication interface card and the voltage detector

482904 V. Description of the invention (4) The electrical connection between them also includes a grounded resistance circuit, including a resistor. The resistance value is preferably between 1 〇 and 3 3 ΙίΩ 〇 This resistance circuit can also contain 5 0 ΙίΩ In the meantime, in order to allow your reviewers to further understand and agree with the present invention, a detailed description is given below in conjunction with the drawings. ^ Detailed description of the invention: Please refer to FIG. 1 and FIG. 2, which are hardware configuration and circuit connection diagram of an embodiment of a test method of a Wait 1 ine terminal on a communication interface (PCMCIA) card slot of the present invention. Among them, the pcMCI A card slot shown in FIG. 2 only shows the interface line with the side of the waiting terminal; the test method of the present invention is connected to the PCMCIA card slot control interface 2'0 'through an external voltage detector 10 The connection line should include at least one data connection line and a waiting connection line 12. Among them, the data connection line 11 is used in the test, as the PCMC IA card slot control interface 20 and the voltage detector. For data transmission between 〇: The waiting connection line 12 is connected to the pc μ c IA card slot suppression interface 20 by the voltage debt tester 1 〇 The terminal is used to derive the voltage of the waiting terminal in parallel ^ As shown in the figure It is shown that in the waiting connecting line 12, a branch line 13 can be grounded through an electrical follower 30 to provide a low voltage for comparison. In the present invention, the voltage detector 10 can be an existing suitable voltage measuring device, such as a Ga 1 chip, a programmable logic controller, or other,

Similar installers. In the present invention, the resistance between the resistor 30 and the resistor ^ m is preferably 10 to 50 ΙΙΩ, and the most preferable value is 3 3 ΙΙΩ. ^ Read, three shown 'is a private picture of the method of measuring the terminal on the PCMcw slot of the present invention, the following is described item by item according to its implementation steps: Step 1 〇 1 Step 100: The test starts and the voltage detection is completed Connection between the controller and the PCMCIA card slot control interface. Initialize the PCMCIA card slot (Initialization), and set the output voltage f to be a predetermined high voltage. The range of the predetermined south voltage is preferably between 3 and 3 0 V, which can be 3V, 5V, 7V. Or any suitable voltage value that can be output by the controller of any PCMCIA card slot.

In a preferred embodiment, the power-on output voltage is 5V. Step 102: Step 103 Set the control of the PCMCIA card slot under the input / output (1/0) operation ’and set its mapping address to the address corresponding to the external line voltage detector.

Read the voltage at the terminal of the PCMC j A card slot at the wiring address behind the voltage detector. V step 1 0 4 · Judging by the voltage value read by the voltage detector whether the voltage at the candidate terminal is at a high level (Η I GH level)

On the other hand, if it is', then a message indicating that the connection is normal (for example, WAIT LINE 0K) is displayed (step 105); if not, a message that indicates that the connection is abnormal is displayed (for example, WA I T

Page 8 482904

5. Description of the invention (6) LINE ERROR) (step 106). Step 107: Turn off the power supply plant controlled by the PCMC I A card slot. Step 108: End the test. It is important that the above-mentioned step connection system includes a grounded resistor circuit. This resistor X ~ resistor is the same as described above. This resistor is used to provide -Z includes a good voltage, and its resistance value is preferably i 0 The better and better line is 33M. In the present invention, at least Ϊ 介绍 The above steps are introduced. Obviously, the test of the present invention 1 includes the following three advantages: Method 1 · No need for specially designed test hardware, only existing test equipment (such as Programmable logic control of model gal6v8; ^ Voltage monk enters its test work, so it is a lower test method compared to the conventional test method. ', It is more cost-effective. / Even-Γ7 ^. *. Ff equipment and circuits, so the overall test equipment is great = can be # degrees South 'the corresponding software is also relatively simple hardware' and because the use of detection; write the test judgment and The control is also relatively straightforward with Jane ’s true heart pressure. Using the method provided by the present invention, it is possible to use, for example, 4 ^ MC A communication; Qin Jinjin's preparation, forming a circuit connection, 以 μ, 丨, μ, μ, 间, 早, 汉, and 下 M ^ M u, 9 miles / three lines on the card slot on or off the circuit or power

Flat-shaped evil, hunting this can reduce the heterogeneity of the low circuit real circuit of the Thunder Circuit

482904 V. The reliability of the description of the invention (7) greatly reduces the cost of implementation. The above description uses a preferred embodiment to describe the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will understand that appropriate changes and adjustments will still be made without departing from the spirit of the present invention. It does not depart from the spirit and scope of the present invention. To sum up, the specificity of the implementation of the present invention has already met the requirements of the invention patent stipulated in the Patent Law. I invite your reviewing committee to review it and grant a quasi-patent as a check.

Page 10 482904 Brief description of the drawings Figure 1 is a hardware configuration diagram of an embodiment of a method for testing a terminal on a communication interface card slot according to the present invention; Figure 2 is a circuit diagram of the embodiment of FIG. 1 (that is, a communication interface card slot D 0 pi η); and FIG. 3 is a flowchart of a method for testing a terminal on a communication interface card slot of the present invention. Description of drawing number: 11 data connection line 1 3 branch line 30 resistor 1 0 voltage detector 1 2 waiting connection line 2 0 PCMCIA card slot control interface

Page 11

Claims (1)

-2j 482 Lesson i Pain 6. Scope of patent application 1. A test method for a terminal on a communication interface card slot, the steps of which include: (1) forming a voltage detector and a communication interface card slot control interface; Electrical connection; (2) initializing the communication interface card slot and applying a predetermined high voltage between 3 and 30 V; (3) controlling the communication interface card slot with one of the voltage detectors Corresponding to the address; (4) the voltage detector reads the voltage of the waiting terminal on the card slot of the communication interface; (5) judging whether the voltage of the waiting terminal is at a high level corresponding to the predetermined high voltage value (Η IG Η 1 eve 1); if yes, it shows that the waiting line is normal; if not, it shows that the waiting line is abnormal; and (6) complete the test of the waiting terminal on the communication interface card slot. 2. The test method of the terminal waiting on the communication interface card slot according to item 1 of the scope of patent application, wherein the voltage detector is a chip. 3. The test method of the terminal on the communication interface card slot according to item 1 of the scope of patent application, wherein the voltage detector is a programmable logic controller. 4. The test method of the terminal waiting on the communication interface card slot according to item 1 of the scope of patent application, wherein the electrical connection described in step (1) is between the communication interface card and the voltage detector and A grounded resistor circuit. 5. The test method for the terminals on the communication interface card slot as described in item 4 of the scope of the patent application, wherein the resistance value of the resistance circuit is between 48 rounds. Jquall I + 0 1_ VI. Application The patent scope is between 10 ~ 501ίΩ. 6. The test method for the terminals on the communication interface card slot as described in item 4 of the scope of patent application, wherein the resistance value of the resistance circuit is between 3 3 ΙΩ. 7. The test method for the terminal on the communication interface card slot as described in the first item of the scope of patent application, wherein the predetermined high voltage is 5 V. 8. —A test combination of waiting terminals on a communication interface card slot, which includes: a communication interface card slot and a waiting terminal; A voltage detector, which includes a data connection line for data transmission and a connection line for deriving the voltage value of the terminal in parallel between the communication interface card slot; and a resistor, which is used for In order to branch the waiting connection line into a ground circuit, a low voltage for comparison is provided. 9. The test combination of the terminals waiting on the communication interface card slot according to item 8 of the scope of patent application, wherein the voltage detector is a chip. 10. The test combination of the waiting terminals on the communication interface card slot as described in item 8 of the scope of patent application, wherein the voltage detector is a programmable logic controller. 1 1. The test combination of the terminals on the communication interface card slot as described in item 8 of the scope of patent application, wherein the resistance value of the resistor is between 10 and 50 0 Ι Ω. .1 2. According to the test combination of the connection terminal and terminal on the communication interface card slot described in item 8 of the scope of the patent application, the resistance value of the resistor is 3 3 η 48 ring mt} VI. Application The scope of the patent is ΙΩ.土 本 #No change Whether the substance is allowed to be amended. Members please be mentioned by t-