TW480813B - Miniaturized multi-layered ceramic low-pass filter - Google Patents
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480813 _案號88108249___午月曰 條正_ 五、發明說明（1) 發明領域 本發明係有關於多層陶瓷低通濾波器。特別利用在諸如行 動及無線電話通信設備上。 相關先前技術： 下列文獻提供了完整之有關低通濾波器之背景資料： [1] D· Swanson,丨’Thin - Film Lumped- Element480813 _ Case No. 88108249 _ Wuyue Yuezheng Article V. Description of the Invention (1) Field of the Invention The present invention relates to a multilayer ceramic low-pass filter. It is particularly used in communication equipment such as mobile and radiotelephones. Related prior art: The following documents provide complete background information on low-pass filters: [1] D · Swanson, 丨 Thin-Film Lumped- Element
Microwave Filters'1, 1 9 8 9 IEEE MTT-S Digest, pages 671-674, 1989.Microwave Filters'1, 1 9 8 9 IEEE MTT-S Digest, pages 671-674, 1989.
[2] J. Helszajn， "Microwave Planar Passive[2] J. Helszajn, " Microwave Planar Passive
Circuits and Filters11, Chapter 15, John Wiley & Sons, 1 9 9 4.Circuits and Filters11, Chapter 15, John Wiley & Sons, 1 9 9 4.
[3] M· Miyazaky, et al·， "A Broad Band Dielectric D i p lexer Using a Snake Strip-Line, f, 1991 IEEE MTT-S Digest, pages 551-554， 1991· [4] U.S. Patent No. 5,357,227 to Tinegawa, et al., 1 9 94. 根據渡波器之實作方式，渡波器又可區分為三大類，即 所謂的集總式濾波器，分佈式濾波器及半集總式濾波器（部 分採用集總式電路元件，及分佈式電路元件）。一般而言分 佈式電路元件往往是由一些傳輪線構成，而傳輸線節之尺 寸則相關於操作頻率下之波長，亦即越低頻之分佈式電路 兀件具^越大之尺寸，因此頻率小於2〇〇MHz(百萬赫兹）時， 不論疋半集總式或分佈式濾波器皆由於分佈式電路元件之[3] M. Miyazaky, et al., &Quot; A Broad Band Dielectric D ip lexer Using a Snake Strip-Line, f, 1991 IEEE MTT-S Digest, pages 551-554, 1991 · [4] US Patent No. 5,357,227 to Tinegawa, et al., 1 9 94. According to the implementation of the wave filter, the wave filter can be divided into three categories, the so-called lumped filter, distributed filter and semi-lumped filter ( Some use lumped circuit elements and distributed circuit elements). Generally speaking, distributed circuit components are often composed of transmission lines, and the size of the transmission line section is related to the wavelength at the operating frequency, that is, the lower the frequency of the distributed circuit components, the larger the size, so the frequency is less than At 200 MHz (million hertz), whether it is a semi-lumped or distributed filter is due to the
第5頁 480813 __案號 88108249__^ 月 9. 修正_ 五、發明說明（2) 過大尺寸而不適合使用。然而在較高的微波（microwave) 頰段或毫米波（millimeter_wave)頻段，則由於分佈式電路 元件有較小之尺寸及優於集總式電路元件之電路性能，所 以往往採用分佈式濾波器。雖然集總式濾波器具有尺寸微 小之特點[1 ],但由於能量損耗過大及高頻寄生效應難以掌 握之故，在操作頻率高於數百MHz之應用很少，近年來由於 高溫超導（superconductor)的使用，集總式電路元件之損 耗可被加以改善，但由於要維持高溫超導操作下之低溫環 境之故，除非將濾波器置於太空中之衛星上，或基地站上， 否則這樣的應用非常有限。 如前所述，在濾波器之操作頻率介於數百MHz至數 GHZ(十億赫茲）之間，由於具低介電係數之分佈式電路元件 =過大尺寸，及集總式元件之能量損耗及寄生效應之故，使 得分佈式^集總式濾波器皆不適合實際應用於行動通訊設 備上。目前通信設備之設計考量主要在於縮小體 功率損。一般而言有二種方式可用以設計高性能 ί Ϊ t ί 土 Ϊ，，一種為使用半集總式設計方式，第二種則 &二i ί係數材料。高介電係數材料型，為利用高介 ;，數Λ枓田縮小操作波長。而半集總式渡波器之設計理 3在於使用低損耗之晶片式 容，而避免使用古電谷，以及多層式之平行板（MIM)電 線式電感，並且ΐ片式電”者平面式及多層繞 配設計。另外半隼_ 、逐小於1 / 4操作波長之傳輸線來搭 具有控制週期性| 3产波器除了具備縮小化能力外，並 瑪頻▼(spurious passband)產生的能力Page 5 480813 __ Case No. 88108249 __ ^ Month 9. Amendment _ V. Description of the invention (2) It is too large to be suitable for use. However, in the higher microwave (milliwave) buccal or millimeter_wave bands, distributed filters are often used because of the smaller size and better circuit performance of lumped circuit components. Although the lumped filter has the characteristics of small size [1], due to excessive energy loss and high-frequency parasitic effects, it is difficult to grasp applications at operating frequencies above hundreds of MHz. In recent years, due to high temperature superconductivity ( With the use of superconductor, the loss of lumped circuit elements can be improved, but because the low temperature environment under high temperature superconducting operation is maintained, unless the filter is placed on a satellite in space or a base station, otherwise Such applications are very limited. As mentioned before, the operating frequency of the filter is between several hundred MHz and several GHZ (billion hertz), because the distributed circuit elements with low dielectric constant = oversized, and the energy loss of lumped elements Due to parasitic effects, distributed lumped filters are not suitable for practical application in mobile communication equipment. At present, the design consideration of communication equipment is mainly to reduce the body power loss. Generally speaking, there are two ways to design high-performance ί Ϊ t ί soil 一种, one is to use a semi-lumped design method, the second is & two i coefficient materials. High dielectric constant material type, in order to make use of high dielectric constants, the number of Λ puta to reduce the operating wavelength. The design principle of the semi-luminous ferrule 3 lies in the use of low-loss chip capacitors, while avoiding the use of ancient electric valleys, and multi-layer parallel plate (MIM) wire-type inductors, and chip-type electricity. Multi-layer winding design. The other half of the transmission line is used to control the periodicity of the transmission line that is less than 1/4 of the operating wavelength. In addition to the reduction capability, the 3 wave generator has the ability to generate spurious passbands.
480813 曰 ^^JB108249 五、發明說明（3) :種週期性偽頻帶產生的問題，往往出現在 中。 ®現在分佈式濾波器480813 ^^ JB108249 V. Description of the Invention (3): The problems caused by periodic pseudo frequency bands often appear in. ® Now Distributed Filter
最近，高介電係數型的陶瓷濾波器註1 m L (coaxiai)及單體式（m〇n〇_bl〇ck)由於它老:同軸線式 優異之性能，非常廣泛受到使用。這類淚_小^尺寸及 自於傳輪結構下金屬之橫截面為圓弧：或皮二之為高二能之： ^结構，導致金屬損耗^二一般帶狀線（stripline)或微帶 線（mlcros trip 1 me)那麼大。而這類濾波器之微小尺寸 特性則來自於高介電係數材料所導致之微小波長之故。但 這種濾波器一般皆應用在帶通及帶拒濾波器之靡用。 圖一所示為文獻[2]中所描述之傳統高°頻渡^皮器。圖 :中較窄之微帶線節4a，4b為等效之串接式電感，而較寬之 線郎5a，5b，5c為等效接至接地面3之電容。更清楚說明為， 個第一個電谷性開路線截5 a形成一個接地電容，而電^ 6a則形成輸入端，此輸入端6a之另一端點與微帶線“相連， 而微帶線4a之另一端點與第二個電容性開路線截讣接上， 並與另一微帶線4b —端相連，而微帶線几之另一端點則接 上第三個電容性開路線截5c，並與電極讣相接，而電極6b ，形成輸出端，這個傳統高頻低通濾波器之等效電路如圖 —所示0 上以下為上述濾波器之缺點。這型濾波器之集總式模型 =衰減極點全位於頻率為無限大時，所以在一般應用時所 f階數較高，造成了較大電路尺寸。一般而言，濾波器之階 數定義為集總等效電路中所使用之分支數目。一個單一電 感，一個單一電容，一個串接電感及電容，或一個並接之電Recently, ceramic filters with high dielectric constants (Note 1 m L (coaxiai) and monolithic (móno_bloc)) have been widely used due to their superior performance: coaxial type. This type of tear _ small size and the cross section of the metal from the wheel structure is an arc: or leather is high energy: ^ structure, resulting in metal loss ^ two general stripline or microstrip line (Mlcros trip 1 me) so big. The small size characteristics of this type of filter come from the small wavelength caused by the high dielectric constant material. However, these filters are generally used in the bandpass and rejection filters. Figure 1 shows the traditional high-frequency skinning device described in [2]. Figure: The narrower microstrip lines 4a and 4b are equivalent series inductors, while the wider lines 5a, 5b, and 5c are equivalent capacitors connected to ground plane 3. It is more clearly explained that the first electrical valley opening line cuts 5 a to form a ground capacitor, and electrical ^ 6 a forms an input terminal, and the other end of this input terminal 6 a is connected to the microstrip line, and the microstrip line The other end of 4a is connected to the second capacitive open line and connected to the other end of the microstrip line 4b, and the other end of the microstrip line is connected to the third capacitive open line. 5c, and is connected to the electrode ，, and the electrode 6b forms the output terminal. The equivalent circuit of this traditional high-frequency low-pass filter is shown in Figure-0. Below and below are the disadvantages of the above filters. General model = the attenuation poles are all located at the infinite frequency, so the f order is higher in general application, which results in a larger circuit size. Generally, the order of the filter is defined as the lumped equivalent circuit The number of branches used: a single inductor, a single capacitor, a series inductor and capacitor, or a parallel connection
1聲，‘ 〜電办各\。都相專於一個分支數。在圖二中各分支皆由單 皆在單一電感所構成。且這些分支所產生之衰減極點 點4 = f ί無限大時。上述衰減極點意指在極點所在頻率 限大日i號元全無法通過濾波器。一個串接電感在頻率為無 率為I相當於開路（〗wLR #，當“"）。一個接地電容在頻 到開^限大時相當於短路（1/jwCR #，twR # )。當信號遇 逯故时或^路則會發生全反射，而無法通過濾波器。一個 抑止=之衰減極點若皆在頻率無限大處，則在抑止帶處之 斜率鉞線斜率將由衰減極點之數目決定，極點數目越多，則 下，^陡_。另外，假如圖一之濾波器應用在射頻（RF)頻帶 之^圖二中之所示電容往往有大的數值，這會造成圖一中 板i線5a，5b，5c必須佔據大的面積，因為一般所用單層基 因二了維^有基本之機械強度而使得基板不至於太薄。也 4 圖_這型濾波器在低頻之應用時尺寸往往太大，而且 欲將圖一之寬線節5a’ 5b, 5c之長度縮小，則為了達到 二本的須要電容值，則寬線節5 a，5 b，5 c之寬度則會變大。 這個現象意味著這型濾波器在縮小尺寸上之困難度。在另 一方面，5a，5b，5c在射頻應用時尺寸並未遠小於波長，這些 線在高頻會產生共振現象，造成高頻出現偽頻帶及抑止效— 果變差。 圖三所示為文獻[2 ]中之濾波器。其等效電路則如圖 四所示，在圖三中，窄的微帶線34a，34b被使用為等效串接 電感，寬線3 5a，35b，35c被使用為等效電容接至接地金屬 面，而另外三條窄線3 4 c，3 4 d，3 4 e則被使用為串接式電感各 別連至上述電容35a，35b，35c電極，36a，36b則被使用為輪1 beep, ‘~ Electrical office each. Both are specialized in one branch number. Each branch in Figure 2 consists of a single inductor. And the attenuation poles generated by these branches 4 = f ί infinite. The above-mentioned attenuation pole means that at the frequency limit where the pole is located, the i-th element cannot pass through the filter at all. A series inductor is equivalent to an open circuit at a frequency of I (〗 wLR #, when “"). A ground capacitor is equivalent to a short circuit when the open-to-frequency limit is large (1 / jwCR #, twR #). When When the signal encounters a failure or ^ channel, total reflection will occur and the filter will not pass. If the attenuation poles of a suppression = are all at infinite frequency, the slope of the slope at the suppression band will be determined by the number of attenuation poles. The more the number of poles, the lower the steep. In addition, if the filter shown in Figure 1 is applied to the radio frequency (RF) frequency band, the capacitor shown in Figure 2 tends to have a large value, which will cause the plate i in Figure 1. The lines 5a, 5b, and 5c must occupy a large area, because the single-layer gene used in general has two dimensions, and has a basic mechanical strength, so that the substrate is not too thin. 4 Figure _ The size of this type of filter in low frequency applications is often Too large, and if you want to reduce the length of the wide line sections 5a '5b, 5c in Figure 1, in order to achieve the required capacitance value of the two books, the width of the wide line sections 5a, 5b, 5c will become larger. This phenomenon means that it is difficult to reduce the size of this type of filter. On the one hand, the dimensions of 5a, 5b, and 5c are not much smaller than the wavelength in RF applications. These lines will generate resonance phenomenon at high frequencies, which will cause pseudo frequency bands and suppression effects at high frequencies—the results are worse. 2]. The equivalent circuit is shown in Figure 4. In Figure 3, narrow microstrip lines 34a and 34b are used as equivalent series inductors, and wide lines 3a, 35b, and 35c are used. The equivalent capacitor is connected to the ground metal surface, and the other three narrow wires 3 4 c, 3 4 d, and 3 4 e are used as series-connected inductors connected to the capacitors 35a, 35b, 35c electrodes, 36a, 36b, respectively. Is used as a wheel
480813 _ 案號88108249_年月日 修正_ 五、發明說明（5) 出，輸入端點。比較圖二及圖四之等效電路，唯一不同在圖 二中之接地電容分支被改成電感及電容互相串接之分支。 這些由串接電感及電容所構成之分支可以產生有限頻率之 衰減極點，在這些衰減極點處，上述分支相當於短路。這意 味著圖四中之濾波器可利用有限頻率之衰減極點增加抑止 帶之抑止曲線斜率，而改善圖二濾波器在應用時須要高階 次之缺點。然而雖然圖三濾波器可以改善高階次之缺點， 但由於單層式之應用，其尺寸仍嫌太大，且高頻特性也不 佳。 圖五為文獻[3]中之蛇形濾波器。其等效電路如圖六 所示，圖五中窄線54a〜54g被使用為等效電感，而寬線 55a〜55d為等效之電容接至接電金屬面，這些電容被並排安 置在一起，因此其彼此間亦產生串接式耦合電容，且與上 述等效電感54b-5 4f並接在一起。電極56a，56b則為輸出， 輸入之端點。在圖六中有一些並聯式電感及電容分支，這 些分支在其共振頻率處相當於開路，雖然這型濾波器可以 產生衰減極點在有限頻率點，但由於與電感並聯之電容太 小（由邊緣耦合造成），以至於這些有限頻率之衰減極點，很 難被設計在通頻帶附近，也因此這型濾波器對減少遽波器 階數改善程度不大。 發明目的丄 本發明之目的為提供一個具有很寬抑止帶及偽頻特性 佳之低通淚波器。 本發明之另一目的為提供一個適合射頻應用之縮小化480813 _ Case No. 88108249_ Year Month Day Amend _ V. Description of the invention (5) Out, enter the endpoint. Comparing the equivalent circuits in Figure 2 and Figure 4, the only difference between the ground capacitor branch in Figure 2 is the branch of the inductor and capacitor connected in series. These branches composed of series-connected inductors and capacitors can generate attenuation poles of limited frequency. At these attenuation poles, the above branches are equivalent to short circuits. This means that the filter in Figure 4 can increase the slope of the suppression curve by using the attenuation poles of the limited frequency, while improving the disadvantage of the filter of Figure 2 that requires a higher order. However, although the filter in Figure 3 can improve the disadvantages of higher orders, its size is still too large and the high-frequency characteristics are not good due to the single-layer application. Figure 5 shows the serpentine filter in [3]. The equivalent circuit is shown in Figure 6. In Figure 5, the narrow lines 54a to 54g are used as equivalent inductors, and the wide lines 55a to 55d are equivalent capacitors connected to the metal surface. These capacitors are placed side by side. Therefore, series coupling capacitors are also generated between them, and are connected in parallel with the equivalent inductors 54b-5 4f. The electrodes 56a and 56b are output and input terminals. In Figure 6, there are some branches of parallel inductors and capacitors. These branches are equivalent to an open circuit at their resonance frequency. Although this type of filter can generate attenuation poles at a finite frequency, because the capacitance in parallel with the inductor is too small (by the edge Caused by coupling), so that the attenuation poles of these finite frequencies can hardly be designed near the passband, and therefore this type of filter has little improvement in reducing the order of the chirper. OBJECTS OF THE INVENTION 目的 The object of the present invention is to provide a low-pass tear waver with a very wide stop band and excellent pseudo-frequency characteristics. Another object of the present invention is to provide a miniaturization suitable for RF applications.
第9頁 480813 _案號88108249_年月日 修正_ 五、發明說明（6) 滤波器。 本發明提供一個小尺寸且具有很寬抑止帶，並且適合 利用多層陶瓷架構來製作之低通濾波器。本發明之濾波器 屬於半集總式，由集總式電容，及傳輸線所組成，這個集總 式電容為多層式架構，利用兩片金屬片，及一個絕緣層組 成，這種電容可藉由使用較薄絕緣層以增加所須電容值，又 能擁有很小之尺寸。因為在多層陶瓷架構下，單一陶瓷層 之厚度可以很小，因此可以有很大數值之電容，使得能設計 有限頻率之衰減極點位於通頻帶附近，於是濾波器之階數 可以被大量減低且濾波器之尺寸可以被大量縮小，也因為 Μ I Μ式電容之尺寸可以很小，因此這類電容，可以被當成理 想電容及使用在更高之頻率，使得高頻之抑止帶可以延伸 至更高之頻率範圍。 圖七為本發明之集總式等效電路，圖七中之小截傳輸 線被使用當成電感性元件。這些傳輸線可以被安排成鋸齒 狀或螺旋狀於單一或多層架構中以縮小電路尺寸，而pi型 電容組〇11-11，11-11+1，〇11+1-11+1(11 = 1，2，3".)為多層式陶瓷架 構，這些電容被使用為理想集總式電容，利用多層式架構來 實現這些電容可以改善先前技術之缺點。首先介質層之厚 度可以很小，因此可以產生大數值電容但小電路尺寸。而 且在多層架構下與電感並聯之電容可以有很大之數值，使 得衰減極點之位置可以非常靠近通頻帶邊緣，造成濾波器 之階數減少，並且由於大電路尺寸造成之高頻共振現象亦 可以被以被改善。 本發明之第一個實施例為一個低通濾波器包含第一個Page 9 480813 _Case No. 88108249_Year Month Day Amend_ V. Description of the invention (6) Filter. The present invention provides a low-pass filter with a small size and a very wide stop band, and which is suitable for making a multilayer ceramic structure. The filter of the present invention belongs to a semi-luminous type, which is composed of a lumped capacitor and a transmission line. The lumped capacitor is a multilayer structure, which uses two metal sheets and an insulating layer. Use a thinner insulation layer to increase the required capacitance and have a small size. Because in the multilayer ceramic structure, the thickness of a single ceramic layer can be very small, so it can have a large value of capacitance, so that the attenuation pole of a limited frequency can be designed near the passband, so the order of the filter can be greatly reduced and filtered. The size of the capacitor can be reduced a lot, and because the size of the MIMO capacitor can be very small, this type of capacitor can be used as an ideal capacitor and used at a higher frequency, so that the high frequency stop band can be extended to higher Frequency range. Fig. 7 is a lumped equivalent circuit of the present invention, and the small-cut transmission line in Fig. 7 is used as an inductive element. These transmission lines can be arranged in a zigzag or spiral shape in a single or multi-layer structure to reduce the circuit size. The pi type capacitor group is 〇11-11, 11-11 + 1, 〇11 + 1-11 + 1 (11 = 1 2,3 ") are multilayer ceramic architectures. These capacitors are used as ideal lumped capacitors. Using multilayer architectures to implement these capacitors can improve the shortcomings of the prior art. First of all, the thickness of the dielectric layer can be small, so it can produce large value capacitance but small circuit size. In addition, the capacitance in parallel with the inductor in the multilayer structure can have a large value, so that the position of the attenuation pole can be very close to the edge of the passband, resulting in a reduction in the order of the filter, and the high-frequency resonance phenomenon caused by the large circuit size. To be improved. A first embodiment of the present invention is a low-pass filter including the first
第10頁 480813 _案號88108249_年月日 修正_ 五、發明說明（7) 介質層有上下兩面，一個第一個接地金屬層被置於下表面， 上表面則為第一個金屬板，並包含了電容性元件及一個端 點；一個第二個介質層疊於第一個金屬板上並有上下兩面， 下表面接第一個金屬板，上表面則為第二個金屬板，並包 含了電容性元件及端點；一個第三個介質層疊於第二個金 屬板上，並有上下兩面，下表面接第二個金屬板，而一個金 屬隔絕層則位於第三介質層之上表面，一個第四個介質層 疊於i述金屬隔絕層之上，並有上下兩面，下表面接於金屬 隔絕層，一個被當成電感性元件之帶狀線則位於第四介質 層之上表面，並有第一及第二端點，一個第五個介質層疊於 帶狀線層之上，並有上下兩面，下表面接於帶狀線層，第二 個金屬接地層則疊於第五個介質層之上表面，第一個邊電 極則置於上述整個疊層之第一邊，第二個邊電極則置於上 述疊層之第二邊，第一個金屬板之端點及帶狀線之第一個 端點連接於第一個邊電極，第二個金屬板之端點及帶狀線 之第二個端點則連接於第二個邊電極，上述之第一及第二 個邊電極即為低通渡波器之輸出輸入端點。 本發明之第二個實施例為一個低通濾波器包含第一個 介質層有上下兩面，一個第一個接地金屬層被置於下表面， 上表面則為一個被當成電感性元件之第一條帶狀線，並有 第一及第二端點；一個第二個介質層疊於第一條帶狀線層 上並有上下兩面，下表面接第一條帶狀線層，上表面則為 第一個金屬隔絕層，一個第三個介質層疊於第一個金屬隔 絕層上並有上下兩面，下表面接第一個金屬隔絕層，上表 面則為第一個金屬板，並包含了電容性元件及一個端點；Page 10 480813 _Case No. 88108249_ Year, Month and Day Amendment_ V. Description of the Invention (7) The dielectric layer has two sides, one first ground metal layer is placed on the lower surface, and the upper surface is the first metal plate. And includes a capacitive element and an end point; a second dielectric is laminated on the first metal plate with two sides, the lower surface is connected to the first metal plate, and the upper surface is the second metal plate, and contains Capacitive elements and terminals; a third dielectric is laminated on a second metal plate with two sides, the lower surface is connected to the second metal plate, and a metal insulation layer is located on the upper surface of the third dielectric layer A fourth dielectric layer is laminated on the metal insulating layer, and has upper and lower sides. The lower surface is connected to the metal insulating layer. A strip line used as an inductive element is located on the upper surface of the fourth dielectric layer. There are first and second endpoints, a fifth dielectric layer is stacked on the strip line layer, and there are upper and lower sides, the lower surface is connected to the strip line layer, and the second metal ground layer is stacked on the fifth medium. Surface above layer, first edge The pole is placed on the first side of the entire stack, and the second side electrode is placed on the second side of the above stack. The end of the first metal plate and the first end of the strip line are connected to the first One side electrode, the end point of the second metal plate and the second end point of the strip line are connected to the second side electrode. The above first and second side electrodes are the output of the low-pass wave filter. Enter the endpoint. A second embodiment of the present invention is a low-pass filter including a first dielectric layer with upper and lower sides, a first ground metal layer is placed on a lower surface, and an upper surface is a first treated as an inductive element. A strip line with first and second ends; a second medium is laminated on the first strip line layer with two sides, the lower surface is connected to the first strip line layer, and the upper surface is The first metal insulation layer, a third dielectric layer is stacked on the first metal insulation layer and has two sides, the lower surface is connected to the first metal insulation layer, and the upper surface is the first metal plate, which contains the capacitor Sex element and an endpoint;
第11頁 480813 _案號88108249_年月曰 修正_ 五、發明說明（8) 一個第四個介質層疊於第一個金屬板上並有上下兩面，下 表面接第一個金屬板，上表面則為第二個金屬板，並包含 了電容性元件及一個端點；一個第五個介質層疊於第二個 金屬板上，並有上下兩面，下表面接第二個金屬板，上表面 則為第三個金屬板，並包含了電容性元件及一個端點；一 個第六個介質層疊於第三個金屬板上，並有上下兩面，下表 面接第三個金屬板，而第二個金屬隔絕層則位於第六介質 層之上表面，一個第七個介質層疊於上述第二個金屬隔絕 層之上，並有上下兩面，下表面接於第二個金屬隔絕層，一 個被當成電感性元件之第二條帶狀線則位於第七介質層之 上表面，並有第一及第二端點，一個第八個介質層疊於第二 條帶狀線層之上，並有上下兩面，下表面接於第二條帶狀線 層，第二個金屬接地層則疊於第八個介質層之上表面，第一 個邊電極則置於上述整個疊層之第一邊，第二個邊電極則 置於上述疊層之第二邊，第三個邊電極則置於上述疊層之 第三邊，第二個金屬板之端點及第二條帶狀線之第一個端 點連接於第一個邊電極，第三個金屬板之端點及第一條帶 狀線之第二個端點則連接於第二個邊電極，第一個金屬板 之端點，第二條帶狀線之第二個端點及第一條帶狀線之第 一個端點則連接於第三個邊電極，上述之第一及第二個邊 電極即為低通濾波器之輸出輸入端點。 本發明之第三個實施例為一個低通濾波器包含第一個 介質層有上下兩面，一個第一個接地金屬層被置於下表 面，上表面則為第一個金屬板，並包含了電容性元件及一 個端點；一個第二個介質層疊於第一個金屬板上並有上下Page 11 480813 _Case No. 88108249_ Year and month amendment_ V. Description of the invention (8) A fourth medium is laminated on the first metal plate with two sides, the lower surface is connected to the first metal plate, and the upper surface It is a second metal plate, which includes a capacitive element and an end point; a fifth dielectric is laminated on the second metal plate, and has two sides, the lower surface is connected to the second metal plate, and the upper surface is Is a third metal plate, and includes a capacitive element and an end point; a sixth dielectric layer is laminated on the third metal plate, and has two sides, the lower surface is connected to the third metal plate, and the second one The metal insulating layer is located on the upper surface of the sixth dielectric layer. A seventh dielectric layer is stacked on the second metal insulating layer, and has two sides. The lower surface is connected to the second metal insulating layer. One is regarded as an electrical layer. The second strip line of the inductive element is located on the upper surface of the seventh dielectric layer, and has first and second ends. An eighth dielectric layer is stacked on the second strip line layer, and has two sides. , The lower surface is connected to the second strip line Layer, the second metal ground layer is stacked on the upper surface of the eighth dielectric layer, the first edge electrode is placed on the first side of the entire stack, and the second edge electrode is placed on the first layer of the above stack. The second side, the third side electrode is placed on the third side of the stack, the end point of the second metal plate and the first end point of the second strip line are connected to the first side electrode, and the third The end of each metal plate and the second end of the first strip line are connected to the second edge electrode, the end of the first metal plate, the second end of the second strip line and The first end of the first strip line is connected to the third side electrode. The first and second side electrodes are the input and output ends of the low-pass filter. A third embodiment of the present invention is a low-pass filter including a first dielectric layer having upper and lower sides, a first ground metal layer placed on a lower surface, and an upper surface being a first metal plate, and including Capacitive element and one end; a second dielectric is laminated on the first metal plate with top and bottom
第12頁 480813 _案號88108249_年月日 條正_ 五、發明說明（9) 兩面，下表面接第一個金屬板，上表面則為第二個金屬 板，並包含了電容性元件及一個端點；一個第三個介質層 疊於第二個金屬板上，並有上下兩面，下表面接第二個金屬 板，上表面則為第三個金屬板，並包含了電容性元件及一 個端點；一個第四個介質層疊於第三個金屬板上，並有上下 兩面，下表面接第三個金屬板，而一個金屬隔絕層則位於第 四介質層之上表面，一個第五個介質層疊於上述金屬隔絕 層之上，並有上下兩面，下表面接於金屬隔絕層，一個被當 成電感性元件之帶狀線則位於第五介質層之上表面，並有 第一端點，第二端點及一個中間端點，一個第六個介質層 疊於帶狀線層之上，並有上下兩面，下表面接於帶狀線層， 第二個金屬接地層則疊於第六個介質層之上表面，第一個 邊電極則置於上述整個疊層之第一邊，第二個邊電極則置 於上述疊層之第二邊，第三個邊電極則置於上述疊層之第 三邊，第二個金屬板之端點及帶狀線之第一個端點連接於 第一個邊電極，第三個金屬板之端點及帶狀線之第二個端 點則連接於第二個邊電極，第一個金屬板之端點及帶狀線 之中間端點則連接於第三個邊電極，上述之第一及第二個 邊電極即為低通濾波器之輸出輸入端點。 本發明之第四個實施例為一個低通濾波器包含第一個 介質層有上下兩面，一個第一個接地金屬層被置於下表 面，上表面則為第一個金屬板，並包含了電容性元件及第 一與第二個端點；一個第二個介質層疊於第一個金屬板上 並有上下兩面，下表面接第一個金屬板，上表面則為第二 個金屬板，並包含了電容性元件及一個端點；一個第三個Page 12 480813 _Case No. 88108249_ Year, Month, and Day Article _ V. Description of the Invention (9) On both sides, the lower surface is connected to the first metal plate, and the upper surface is the second metal plate, which contains the capacitive element and One end; a third dielectric is laminated on a second metal plate with two sides, the lower surface is connected to the second metal plate, and the upper surface is the third metal plate, which contains the capacitive element and a End point; a fourth dielectric layer is stacked on the third metal plate, and has upper and lower sides, the lower surface is connected to the third metal plate, and a metal insulation layer is located on the upper surface of the fourth dielectric layer, and a fifth The dielectric is laminated on the above metal insulating layer and has two sides, the lower surface is connected to the metal insulating layer, and a strip line used as an inductive element is located on the upper surface of the fifth dielectric layer and has a first end point. The second endpoint and an intermediate endpoint, a sixth dielectric layer is stacked on the strip line layer and has two sides, the lower surface is connected to the strip line layer, and the second metal ground layer is stacked on the sixth Above the dielectric layer, the first The electrode is placed on the first side of the entire stack, the second side electrode is placed on the second side of the stack, the third side electrode is placed on the third side of the stack, and the second metal plate The end point of the strip line and the first end point of the strip line are connected to the first side electrode, and the end point of the third metal plate and the second end point of the strip line are connected to the second side electrode. The end point of each metal plate and the middle end point of the strip line are connected to a third side electrode, and the first and second side electrodes are the output and input ends of the low-pass filter. A fourth embodiment of the present invention is a low-pass filter including a first dielectric layer having upper and lower sides, a first ground metal layer being placed on a lower surface, and an upper surface being a first metal plate and including Capacitive element and first and second endpoints; a second dielectric is laminated on the first metal plate with two sides, the lower surface is connected to the first metal plate, and the upper surface is the second metal plate. And includes a capacitive element and an endpoint; a third
第13頁 480813 案號 88108249 Λ_Β 曰 修正 五、發明說明（10) 介質層疊於第二個金屬板上，並有上下兩面，下表面接第二 個金屬板，上表面則為第三個金屬板，並包含了電容性元 件及一個端點；一個第四個介質層疊於第三個金屬板上，並 有上下兩面，下表面接第三個金屬板，而一個金屬隔絕層則 位於第四介質層之上表面，一個第五個介質層疊於上述金 屬隔絕層之上，並有上下兩面，下表面接於金屬隔絕層，一 個被當成電感性元件之第一條帶狀線則位於第五介質層之 上表面，並有第一端點及第二端點，另一個被當成電感性元 件之第二條帶狀線亦位於第五介質層之上表面，並有第一 端點及第二端點，一個第六個介質層疊於帶狀線層之上，並 有上下兩面，下表面接於帶狀線層，第二個金屬接地層則疊 於第六個介質層之上表面，第一個邊電極則置於上述整個 疊層之第一邊，第二個邊電極則置於上述疊層之第二邊，第 三個邊電極則置於上述疊層之第三邊，第四個邊電極則置 於上述疊層之第四邊，第二個金屬板之端點及第一條帶狀 線之第一個端點連接於第一個邊電極，第三個金屬板之端 點及第二條帶狀線之第二個端點則連接於第二個邊電極， 第一個金屬板之第一端點及第一條帶狀線之第二端點則連 接於第三個邊電極，第一個金屬板之第二端點及第二條帶 狀線之第一端點則連接於第四個邊電極，上述之第一及第 二個邊電極即為低通遽波器之輸出輸入端點。 本發明之第五個實施例為一個低通濾波器包含第一個 介質層有上下兩面，一個第一個接地金屬層被置於下表 面，上表面則為第一個金屬板，並包含了電容性元件及第 一與第二個端點；一個第二個介質層疊於第一個金屬板上Page 13 480813 Case No. 88108249 Λ_Β Revision V. Description of the invention (10) The medium is laminated on a second metal plate with two sides, the lower surface is connected to the second metal plate, and the upper surface is the third metal plate. And contains a capacitive element and an end point; a fourth dielectric is laminated on a third metal plate with two sides, the lower surface is connected to the third metal plate, and a metal insulation layer is located on the fourth medium On the upper surface of the layer, a fifth dielectric layer is laminated on the above-mentioned metal insulating layer, and has two upper and lower sides. The lower surface is connected to the metal insulating layer. The upper surface of the layer has a first end and a second end, and the second strip line, which is regarded as an inductive element, is also located on the upper surface of the fifth dielectric layer, and has a first end and a second end. At the end point, a sixth dielectric layer is stacked on the strip line layer and has two sides, the lower surface is connected to the strip line layer, and the second metal ground layer is stacked on the upper surface of the sixth dielectric layer. One side electrode is placed above The first edge of the entire stack, the second edge electrode is placed on the second edge of the stack, the third edge electrode is placed on the third edge of the stack, and the fourth edge electrode is placed on the stack. The fourth edge of the layer, the endpoint of the second metal plate and the first endpoint of the first stripline are connected to the first edge electrode, the endpoint of the third metal plate and the second stripline The second endpoint is connected to the second edge electrode, the first endpoint of the first metal plate and the second endpoint of the first stripline are connected to the third edge electrode, the first metal The second end point of the board and the first end point of the second strip line are connected to the fourth side electrode. The first and second side electrodes are the output and input ends of the low-pass chirp. A fifth embodiment of the present invention is a low-pass filter including a first dielectric layer having upper and lower sides, a first ground metal layer being placed on a lower surface, and an upper surface being a first metal plate and including Capacitive element and first and second terminals; a second dielectric is laminated on the first metal plate
第14頁 480813 _案號88108249_年月日 條正_ 五、發明說明（11) 並有上下兩面，下表面接第一個金屬板，上表面則有第二 個金屬板及第三個金屬板，分別包含有電容性元件及一個 端點；一個第三個介質層疊於第二及第三個金屬板上，並有 上下兩面，下表面接第二及第三個金屬板，而一個金屬隔絕 層則位於第三介質層之上表面，一個第四個介質層疊於上 述金屬隔絕層之上，並有上下兩面，下表面接於金屬隔絕 層，一個被當成電感性元件之第一條帶狀線則位於第四介 質層之上表面，並有第一端點及第二端點，另一個被當成電 感性元件之第二條帶狀線亦位於第四介質層之上表面，並 有第一端點及第二端點，一個第五個介質層疊於帶狀線層 之上，並有上下兩面，下表面接於帶狀線層，第二個金屬接 地層則疊於第六個介質層之上表面，第一個邊電極則置於 上述整個疊層之第一邊，第二個邊電極則置於上述疊層之 第二邊，第三個邊電極則置於上述疊層之第三邊，第四個邊 電極則置於上述疊層之第四邊，第二個金屬板之端點及第 一條帶狀線之第一個端點連接於第一個邊電極，第三個金 屬板之端點及第二條帶狀線之第二個端點則連接於第二個 邊電極，第一個金屬板之第一端點及第一條帶狀線之第二 端點則連接於第三個邊電極，第一個金屬板之第二端點及 第二條帶狀線之第一端點則連接於第四個邊電極，上述之 第一及第二個邊電極即為低通濾波器之輸出輸入端點。 本發明之第六個實施例為一個低通濾波器包含第一個 介質層有上下兩面，一個第一個接地金屬層被置於下表 面，上表面則為第一個金屬板，並包含了電容性元件及一 個端點；一個第二個介質層疊於第一個金屬板上並有上下Page 14 480813 _Case No. 88108249_ Year, Month, and Day Article _ V. Description of the Invention (11) There are two sides, the lower surface is connected to the first metal plate, and the upper surface is the second metal plate and the third metal. Plate, which contains a capacitive element and an end point respectively; a third dielectric layer is laminated on the second and third metal plates, and has upper and lower sides, the lower surface is connected to the second and third metal plates, and a metal The isolation layer is located on the upper surface of the third dielectric layer. A fourth dielectric layer is stacked on the above metal insulating layer and has two sides. The lower surface is connected to the metal insulating layer. One is used as the first strip of the inductive element. The shape line is located on the upper surface of the fourth dielectric layer, and has a first end point and a second end point. The second strip line, which is regarded as an inductive element, is also located on the upper surface of the fourth dielectric layer, and has At the first and second endpoints, a fifth dielectric layer is stacked on the stripline layer, and has two sides, the lower surface is connected to the stripline layer, and the second metal ground layer is stacked on the sixth layer. The top surface of the dielectric layer, the first edge electrode is placed on The first side of the stack is described, the second side electrode is placed on the second side of the stack, the third side electrode is placed on the third side of the stack, and the fourth side electrode is placed on the above. The fourth edge of the stack, the end of the second metal plate and the first end of the first strip line are connected to the first edge electrode, the end of the third metal plate and the second strip The second end of the line is connected to the second edge electrode, the first end of the first metal plate and the second end of the first strip line are connected to the third edge electrode, the first The second end point of the metal plate and the first end point of the second strip line are connected to the fourth side electrode. The first and second side electrodes are the input and output ends of the low-pass filter. A sixth embodiment of the present invention is a low-pass filter including a first dielectric layer having upper and lower sides, a first ground metal layer being placed on a lower surface, and an upper surface being a first metal plate and including Capacitive element and one end; a second dielectric is laminated on the first metal plate with top and bottom
第15頁 480813 _案號88108249_年月日 條正_ 五、發明說明（12) 兩面，下表面接第一個金屬板，上表面則為第二個金屬 板，並包含了電容性元件及第一與第二個端點；一個第三 個介質層疊於第二個金屬板上，並有上下兩面，下表面接第 二個金屬板，上表面則為第三個金屬板，並包含了電容性 元件及一個端點；一個第四個介質層疊於第三個金屬板上， 並有上下兩面，下表面接第三個金屬板，而一個金屬隔絕層 則位於第四介質層之上表面，一個第五個介質層疊於上述 金屬隔絕層之上，並有上下兩面，下表面接於金屬隔絕層， 一個被當成電感性元件之第一條帶狀線則位於第五介質層 之上表面，並有第一端點及第二端點，另一個被當成電感性 元件之第二條帶狀線亦位於第五介質層之上表面，並有第 一端點及第二端點，一個第六個介質層疊於帶狀線層之上， 並有上下兩面，下表面接於帶狀線層，第二個金屬接地層則 疊於第六個介質層之上表面，第一個邊電極則置於上述整 個疊層之第一邊，第二個邊電極則置於上述疊層之第二邊， 第三個邊電極則置於上述疊層之第三邊，第四個邊電極則 置於上述疊層之第四邊，第三個金屬板之端點及第一條帶 狀線之第一個端點連接於第一個邊電極，第一個金屬板之 端點及第二條帶狀線之第二個端點則連接於第二個邊電 極，第二個金屬板之第一端點及第一條帶狀線之第二端點 則連接於第三個邊電極，第二個金屬板之第二端點及第二 條帶狀線之第一端點則連接於第四個邊電極，上述之第一 及第二個邊電極即為低通濾波器之輸出輸入端點。 上述之任何實施例可以不同電路諸如功率放大器相結合而 成縮小化之射頻模組。Page 15 480813 _ Case No. 88108249_ Year, month, and year article _ V. Description of the invention (12) Two sides, the lower surface is connected to the first metal plate, and the upper surface is the second metal plate, which contains the capacitive element and The first and second endpoints; a third medium is laminated on the second metal plate, and has two sides, the lower surface is connected to the second metal plate, and the upper surface is the third metal plate, and contains Capacitive element and one end point; a fourth dielectric layer is laminated on the third metal plate and has upper and lower sides, the lower surface is connected to the third metal plate, and a metal insulating layer is located on the upper surface of the fourth dielectric layer A fifth dielectric layer is stacked on the above-mentioned metal insulating layer, and has upper and lower sides, the lower surface is connected to the metal insulating layer, and a first strip line used as an inductive element is located on the upper surface of the fifth dielectric layer. And has a first end point and a second end point, and a second strip line, which is regarded as an inductive element, is also located on the upper surface of the fifth dielectric layer, and has a first end point and a second end point, one Sixth dielectric layered on top of the stripline layer There are two sides, the lower surface is connected to the strip line layer, the second metal ground layer is stacked on the upper surface of the sixth dielectric layer, and the first edge electrode is placed on the first side of the entire stack. Two side electrodes are placed on the second side of the stack, a third side electrode is placed on the third side of the stack, a fourth side electrode is placed on the fourth side of the stack, and a third The end of the metal plate and the first end of the first strip line are connected to the first edge electrode, and the end of the first metal plate and the second end of the second strip line are connected to The second edge electrode, the first endpoint of the second metal plate and the second endpoint of the first strip line are connected to the third edge electrode, the second endpoint of the second metal plate and the second The first end point of the strip line is connected to the fourth side electrode. The first and second side electrodes are the output and input ends of the low-pass filter. Any of the embodiments described above can be combined with different circuits such as a power amplifier to form a reduced RF module.
第16頁 480813 --案號 88〗0奶仙 五、發明說明（13) 月 Β 修正 發明之詳細説明 圖八為本發明之等效電路，節點0η(η=1，2, 3，···· k)代 表接地，臂On-n，n-n+l(n=l，2,3，."k)代表集總式電容，而 條狀線m ( m = 1，2，3，….j)代表傳輸線卽。在圖八中j = k - 1， 本發明低通渡波器之典型性能圖如圖九（k = 2，j = 1 )及圖十 (k = 3，j = 2)所示。以下將詳述圖八之等效電路各種之實際 作法。圖八之等效電路，不僅可以微帶線電路，帶狀線電 路，更可利用混合微帶線及帶狀線之多層陶瓷電路來製 作。由於本發明可以有各種不同型式之作法，在此為避免 太過冗長之描述各種可能實施例，將只對等效電路中之各 元件，如傳輸線，p i型電容組之作法作--描述。 首先描述本發明中所使用之pi型電容Page 16 480813-Case No. 88〗 0 Milk Fairy 5. Description of the invention (13) Detailed description of the revised invention in month B Figure 8 is the equivalent circuit of the invention, node 0η (η = 1, 2, 3, ... K) represents ground, arm On-n, n-n + l (n = l, 2, 3,. &Quot; k) represents lumped capacitance, and the strip line m (m = 1, 2, 3 , .... j) stands for transmission line 卽. In FIG. 8, j = k-1, the typical performance chart of the low-pass ferrule of the present invention is shown in Fig. 9 (k = 2, j = 1) and Fig. 10 (k = 3, j = 2). Various practical methods of the equivalent circuit of Fig. 8 will be detailed below. The equivalent circuit in Fig. 8 can not only be a microstrip line circuit, a strip line circuit, but also a multilayer ceramic circuit with a mixed microstrip line and a strip line. Since the present invention can have various types of methods, in order to avoid too long description of the various possible embodiments, only the components of the equivalent circuit, such as the transmission line, the p i type capacitor bank will be described. First, the pi-type capacitor used in the present invention will be described.
On-n，n-η+1，〇η+ι 一 η+ι (如圖七，圖八中位於節點（n〇de) 間之電容01-1，1-20及2-2)。 圖十一為利用一耦合微帶線節11，33(如圖八中介於節 及節點2之部分）放置在一具有接地面66之介質層55上， $個介質層一般而言指為陶瓷層，但其他材料系統亦可。 當渡波器須要使用到大數值電容n-nH時，可使用如圖十二 =示之父又指狀式之安排，亦即將2個交又配置之微帶線放 置於一具有接面88之介質層77上。 圖十二及圖十四為利用帶狀線來實現pi型電容組之圖 例，其與微帶線電路系統之實施例之差異在於須在圖十一 中之介質層55上加一層介質層56及一上接地金屬板5 7，及 在圖十二中之介質層77上加一層介質層76及一上接金屬板On-n, n-η + 1, 〇η + ι-η + ι (see Figure 7 and Figure 8 for capacitors 01-1, 1-20, and 2-2 located between nodes). Figure 11 shows the use of a coupling microstrip line section 11, 33 (as shown in Figure 8 between the section and the node 2) placed on a dielectric layer 55 with a ground plane 66. The $ dielectric layer is generally referred to as ceramic Layer, but other material systems are also possible. When a large value capacitor n-nH is required for the wave traversing device, the arrangement of the father and fingers as shown in Figure 12 can be used, that is, two microstrip lines arranged in an alternating configuration are placed on a junction 88. On the dielectric layer 77. Figures 12 and 14 are examples of implementing pi-type capacitor banks using strip lines. The difference from the microstrip circuit system embodiment is that a dielectric layer 56 must be added to the dielectric layer 55 in FIG. And a ground metal plate 57, and a dielectric layer 76 and a metal plate on the dielectric layer 77 in FIG.
第17頁 480813Page 17 480813
t號 88108249 五、發明說明（14) 78 〇 另外在多層架構下，則可利用交叉放置平 層間去實現具有大數值電容且小面積之丨 ；" 五⑴及圖十五⑻所示。圖十五(Α)積之二巧組如圖十 系統中之實現方式，為將二組交又放置之平，、二=線電路 8』置：：質82中並且上下各有接地金屬板心 此P1型電容組實現於多層微帶線電路季， 右要將 十之上接地金屬板83及線介=^^^ 之最上層板之間之介質移除即可。另外 、、’ 中之平行金屬板組84及85之板個數及Pi型雷— 认（） 輸入方向及位置，肖Τ依實際須要作冑整。電谷、、且之輸出 圖十六所示為將圖十五（B)中之平行板組等電位之方 ίτ依P眘利⑼用//186將平行板組84相連接，λ中穿孔86之個數 可Ϊ Ϊ f 作增減。另外若平行板組接近基板邊緣，亦 矛J用如圖十七所示之側面電極來等電位。 一〜十五之以型電容組之輸人輸出方向可為任意， 人電路佈局須求而定。如圖十八中所示，只是平行耦 σ綠11，33之方向作了 90度之改變。 微嫌ί著描述圖八中之傳輸線m之實現方式，圖十九為習知 地X、麗傳輸線架構’為將信號線5〇3置於介質層502及下接 帶镱接Ϊ5 01上，圖二十為習知帶狀線傳輸線架構，為將微 十九ίϊ線架構加上一介質層504及上接地金屬板5 0 5。圖 面積=t十中之傳輸線可依須要作曲折或螺旋狀以縮小 —及円i傳輸線m亦可以多層化之方式來實現，如圖二十 一十一所示，圖二Η 為多層帶狀線架構圖二十二t. No. 88108249 V. Description of the invention (14) 78 〇 In addition, in a multi-layer architecture, you can use cross-placement between layers to achieve a large-value capacitor with a small area. " Figure 15 (A) The product of the two-prong group is shown in the system of Figure 10. In order to place the two groups in a flat position, two = line circuit 8 'is placed: in the mass 82 and there are ground metal plates on the top and bottom. The P1 type capacitor bank is realized in the multi-layer microstrip line circuit season. To the right, the dielectric between the ground metal plate 83 and the uppermost layer of the wire = ^^^ can be removed. In addition, the number of plates of the parallel metal plate groups 84 and 85 and Pi-type mines in ，, ’—recognize () the input direction and position, Xiao T needs to be adjusted according to the actual situation. The output of the electric valley, and is shown in Fig. 16. The parallel potential of the parallel plate group in Fig. 15 (B) is shown in Figure 16. Using the // 186, the parallel plate group 84 is connected, and the perforation is in λ. The number 86 can be increased or decreased by Ϊ Ϊ f. In addition, if the parallel plate group is close to the edge of the substrate, use the side electrode as shown in Figure 17 to equipotential. The input and output directions of one to fifteen-type capacitor groups can be arbitrary, and the layout of the human circuit must be determined. As shown in Fig. 18, the direction of parallel coupling σ green 11,33 has been changed by 90 degrees. The description of the implementation of the transmission line m in Figure 8 is described slightly. Figure 19 is the conventional X and Li transmission line architecture. 'The signal line 503 is placed on the dielectric layer 502 and the lower connection tape 501, FIG. 20 is a conventional stripline transmission line architecture, which is a micro-nineteen-line architecture plus a dielectric layer 504 and an upper ground metal plate 505. The transmission line in the area of t = ten can be reduced to zigzag or spiral shape-and the transmission line m can also be realized in multiple layers, as shown in Figure 21, and Figure 2 is a multi-layered belt. Line architecture diagram 22
第18頁 480813 ±_3 曰 修正 案號 88108249 五、發明說明（15) - 為多層微帶線與帶狀線混合架構。圖二十_為將信 6 0 6及6 0 7插入接地金屬板601，6 0 2, 6 0 3間之介質6〇5 而不同層之信號線6 0 6及6 0 7則利用穿孔6〇8經過^祕今屬 ^2^:〇】^連接。圖二十二為將信號線4 0 6罝 ;二晉二二in:4°4上(微帶線架構)，及將信號 狀線架構）而信號線40 6,40 7之連接則藉由穿孔/ 地金屬板之無金屬區409來作連接.上述圖二 ^為利用圖式之實施例對多層化傳輸線作實^ 層間之電容組及傳輸線之連接亦可如圖十七之方另式卜來 圖二十四（k = 2，j=：i)及圖二十五（k · 電路之兩種實施例。 ，：I = 2 )為圖八等效 圖二十三為圖二十四之低通漁浊哭々隹綠4松 電路，圖二十三（B)為圖二十五至圖二^皮器之集總式等效 集總式等效電路。 十九之低通濾波器之 以下將说明圖二十四實施例與圖二 之相對應關係，在圖二十三（A)之0型=t(A)等效電路 至圖十五之方式來製作。在圖二十四谷、、且可以如圖十一 及⑻之方式來製作，但只 I，為利用圖十五（A) 為如圖二十之帶狀線’亦可為如圖二^作，廷截傳輸線可 :十九之微帶線，及圖二十二之多層=多狀士’或 中，一條曲折過之帶狀線211( 在圖二十四 ^方式）即被用為電感Page 18 480813 ± _3 said amendment No. 88108249 V. Description of the invention (15)-It is a mixed architecture of multilayer microstrip line and strip line. Figure 20_ is for inserting the letters 6 0 6 and 6 0 7 into the grounded metal plate 601, 6 0 2, 6 0 3, and the signal wires 6 0 6 and 6 0 7 in different layers use perforated 6 〇8 is connected through ^ SEC this genus ^ 2 ^: 〇] ^. Figure 22 shows the signal line 4 0 6 罝; the second and second in: 4 ° 4 (microstrip line structure), and the signal line structure) and the signal lines 40 6, 40 7 are connected by The perforated / ground metal plate has no metal area 409 for connection. The above figure 2 ^ is the implementation of the multi-layered transmission line using the embodiment of the figure ^ The connection between the capacitor group and the transmission line between the layers can also be changed as shown in Figure 17 The blue figure twenty-four (k = 2, j =: i) and the twenty-five (k · two embodiments of the circuit. :: I = 2) are the equivalent of FIG. 8 and the twenty-third are the twenty The fourth low-pass fishing turbid cry green green 4 pine circuit, Figure 23 (B) is the lumped equivalent lumped equivalent circuit of the leather device of Figure 25 to Figure 2. The following will describe the corresponding relationship between the embodiment of FIG. 24 and the embodiment of FIG. 2 in the nineteenth low-pass filter. In FIG. 23 (A), the type 0 = t (A) equivalent circuit to the manner in FIG. 15 To make. In the twenty-four valleys in Fig., And can be produced in the manner shown in Fig. 11 and ⑻, but only I, in order to use Fig. Fifteen (A) is a strip line as shown in Fig. 20, it can also be as shown in Fig. 2 ^ For example, the cut-off transmission line can be: the nineteen microstrip line, and the multi-layer of Figure 22 = polymorphism 'or medium, a zigzag strip line 211 (in the twenty-fourth method of Figure) is used as inductance
第19頁 480813 案號 88108249 Λ_Β 曰 修正 五、發明說明（16) ^元件，而介於電感及電容組間之連接點5〇 3, 5 〇4(圖二十 三（Α))在圖二十四中則是以邊電極2 〇9及2 10來製祚。而違 電極之作法則與圖十七同。另外在應用上邊 被使用為輸出，輸入接點。在圖二十四中，2〇1 2Q2 203為 接地金屬板，2 0 4, 2 0 5, 2 0 6, 2 0 7, 2 0 8為介質基板或陶竞體\ 金屬板2 0 2不僅被當成接地面，也被當成電磁隔絕板 絕傳輸線節21丨及電容組212,213之電磁耦合。έ板用以^ 以下將说明圖二十五至圖二十九之實施例與圖二十三 (B )之等效電路間之相對應關係。 在圖二十三（B)中介於601，6 0 2, 6 0 4, 6 0 5間之pi型電 ^組是以圖二十五中之金屬板3 18, 32〇來製作。而圖二十 二（B)中介於602，603，605，606間之pi型電容組是以圖二十 五中之金屬板3 2 0, 3 1 9來製作，而在圖二十三（B)中介於^〇4 及6 0 5間之電感則是以圖二十五之帶狀線317來製作。圖二 十二（B)中之連接點604 ,605,606,在圖二十五中則是以邊 電極313 ,314,315來製作。圖二十五中之邊電極gig us亦 被使用為輸出，輸入接點。另外在圖二十五中 ’ 301,302 ,303 ,304為接地金屬板，而302 ,303則亦被使用為 電磁隔絕層。而在圖二十五中，3〇5〜312則為介質層或陶瓷 體。 在圖二十五，被用為電感性元件之帶狀線316, 317被放 置於不同介質層306及3 12上，而在圖二十六中帶狀線 413, 414則被置於同一介質層4〇5之上。將帶狀線放置於不 同層之優點為濾波器面積有限制或帶狀線太長時，可以縮 小使用面積，這樣安排一方面可使電路更微小，並且可避免Page 19 480813 Case No. 88108249 Λ_Β Revision V. Description of the invention (16) ^ components, and the connection points between the inductor and capacitor groups 503, 504 (Figure 23 (A)) in Figure 2 In the 14th Middle School, the side electrodes 209 and 2 10 are used to make dysprosium. The violation of the electrode is the same as in Figure 17. In addition, it is used as an output and input contact in the application. In Figure 24, 201 2Q2 203 is a grounded metal plate, 2 0 4, 2 0 5, 2 0 6, 2 0 7, 2 0 8 is a dielectric substrate or ceramic body \ metal plate 2 0 2 is not only It is regarded as the ground plane, and is also used as the electromagnetic coupling between the transmission line section 21 丨 and the capacitor groups 212,213 for electromagnetic coupling. The board is used ^ The following describes the corresponding relationship between the embodiment of FIGS. 25 to 29 and the equivalent circuit of FIG. 23 (B). In FIG. 23 (B), a pi-type electric circuit between 601, 6 0 2, 6 0 4, 6 0 5 is made by using metal plates 3 18, 32 0 in FIG. 25. The pi-type capacitor bank between 602, 603, 605, and 606 in FIG. 22 (B) is made of the metal plates 3 2 0, 3 1 9 in FIG. 25, and in FIG. 23 ( B) The inductor between ^ 〇4 and 605 is made by the strip line 317 in Fig. 25. The connection points 604, 605, 606 in Fig. 22 (B) are made with the side electrodes 313, 314, 315 in Fig. 25. The edge electrode gig us in Figure 25 is also used as an output, input contact. In addition, in Fig. 25, 301, 302, 303, and 304 are grounded metal plates, and 302, 303 are also used as electromagnetic insulation layers. In Figure 25, 305 ~ 312 are dielectric layers or ceramic bodies. In FIG. 25, strip lines 316, 317 used as inductive elements are placed on different dielectric layers 306 and 31, and in FIG. 26, strip lines 413, 414 are placed on the same dielectric. Above layer 405. The advantage of placing strip lines on different layers is that when the area of the filter is limited or the strip line is too long, the use area can be reduced. This arrangement can make the circuit smaller and avoid
第20頁 480813Page 20 480813
案號 88108249 五、發明說明（17) 帶狀線間互相耦合效應。 在圖二十三（B)中介於601，6〇2, 6〇4, 6〇5間之 容組是以圖二十六中之金屬板415, 417來製作。 二（B)中介於602, 603，605, 606間之p i型電容組是 六中之金屬板417, 416來製作，而在圖二十三（B) 及6 0 5間之電感則是以圖二十六中之帶狀線414來於。604 二十三（B)中之連接點604, 605, 606,在圖二十六中則0 邊電極4^4^02來製作。圖二十六中之邊電極^^斗^ 亦被使用為輸出，輸入接點。另外在圖二十六中 ’ 40 1，40 2, 4 0 3為接地金屬板，而4〇2則亦被使用為電磁 層。而在圖二=六中404〜400則為介質層或陶瓷體。、、 —，圖二十三（B)中介於601，6 0 2, 6 0 4, 6 0 5間之pi型電 ，組是以圖二十七中之金屬板718,72〇來製作。而圖二 三（B)中介於6 0 2, 6 0 3, 6 0 5, 6 0 6間之pi型電容組是以回圖^二十 金屬板Γ0,719來製作，而在圖二十三（B)中介於“4 間之電感則是以圖二十七中之帶狀線7 1 7來製作。而 f圖二十三（B)中介於6〇5及6〇6間之電感則是以圖二十七 ^ =帶狀線716來製作。圖二十三（B)中之連接點6〇4,6〇6, 圖二十七中則是以邊電極71 3, 715來製作。圖二十七中 t邊電極7 13, 715亦被使用為輸出，輸入接點。圖二十三 來制中之連接點605，在圖二十七中則是以邊電極714a，714b 7 ^作。71 4a用以連接帶狀線7丨6，而7 14b用以連接帶狀線 。、另外在圖二十七中7〇丨，7 0 2, 70 3為接地金屬板，而？〇2 八二被使用為電磁隔絕層。而在圖二十七中7〇5〜71〇則為 質層或陶瓷體。Case number 88108249 V. Description of the invention (17) Mutual coupling effect between strip lines. The contents between 601, 602, 604, and 605 in FIG. 23 (B) are made of metal plates 415, 417 in FIG. 26. The two (B) pi capacitors between 602, 603, 605, and 606 are made of metal plates 417, 416 of the sixth, and the inductors between Figure 23 (B) and 605 are based on The strip line 414 in FIG. 26 comes from. 604 Twenty-three (B) is the connection point 604, 605, 606. In Fig. 26, the 0-side electrode 4 ^ 4 ^ 02 is used. The edge electrode ^^ dou ^ in Figure 26 is also used as an output, input contact. In addition, in Figure 26, ’40 1, 40 2, 403 is a grounded metal plate, and 402 is also used as an electromagnetic layer. In Figure 2 = 6, 404 ~ 400 are dielectric layers or ceramic bodies. 、、 ——, the pi-type electricity between 601, 6 0 2, 6 0 4, 6 0 5 in Fig. 23 (B), the set is made by the metal plate 718, 720 in Fig. 27. The pi-type capacitor bank between 6 0 2, 6 0 3, 6 0 5, 6 0 6 in Figure 23 (B) is made by referring to the figure ^ 20 metal plate Γ0,719, and in Figure 20 The inductance between "4" in three (B) is made by the strip line 7 1 7 in Fig. 27. The inductance between "f" in Fig. 23 (B) between "605" and "0.66" It is made with the strip line 716 in Fig. 27 ^. The connection points in Fig. 23 (B) are 604, 606, and in Fig. 27 are the side electrodes 71 3, 715. Production. The t-side electrode 7 13, 715 in Fig. 27 is also used as an output and input contact. The connection point 605 in the system is shown in Fig. 23, and the side electrodes 714a and 714b are used in Fig. 27. 7 ^. 71 4a is used to connect the strip line 7 丨 6, and 7 14b is used to connect the strip line. In addition, in Fig. 27, 7〇 丨, 7 0 2, 70 3 are ground metal plates, and 〇82 is used as an electromagnetic insulation layer. In Figure 27, 705 ~ 71〇 is a solid layer or a ceramic body.
480813 曰 ―修-480813 Said ―Xiu-
案號 8810824Q 五、發明說明（18) 在圖二十三（Β)中介於6 〇1,602, 604, 605間之pi型電 容組是以圖二十八中之金屬板818, 820來製作。而圖二十 二（B)中介於602 ,603,605，606間之pi型電容組是以圖二十 八中之金屬板820, 819來製作，而在圖二十三（B)中介於6〇4 及605間之電感則是以圖二十八中之帶狀線Η?來製作。而 在圖二十三（B)中介於605及606間之電感則是以圖二十八 中之帶狀線816來製作。圖二十三（3)中之連接點6〇4 6〇5, 6 0 6,在圖二十八中則是以邊電極8丨3, 8 14, 815來製作。圖 二十^中之邊電極8 1 3，8 1 5亦被使用為輸出，輸入接點。圖 二十二（B)中之連接點6〇5，在圖二十八中則是以邊電極 814a，814b來製作。814a用以連接帶狀線816，而8Hb用以 連接帶狀線817。另外在圖二十八中8〇1，8〇2, 8〇3為接地金 屬板，而8 0 2則亦被使用為電磁隔絕層。而在圖二十八中 805〜809則為介質層或陶究體。 —，圖二=三（B)中介於6 01，602, 604, 605間之Pi型電 ^組是以圖二十九中之金屬板918,92〇來製作。而圖二十 二（B)中介於6 02, 603, 605, 606間之pi型電容組是以圖二十 九中之金屬板9 20, 919來製作，而在圖二十三（B)中介於6〇4 及6 0 5間之電感則是以圖二十九中之帶狀線917來製作、。而 在圖二十三（B)中介於6 0 5及6〇6間之電感則是以圖二 中之帶狀線916來製作。圖- + -（只、由♦、由上 .^ 丄丄山 ^ 圖一十二（B)中之連接點604, 606, 在圖一十九中則是以邊電極913, 914, 915來製作。 電查極Γ3, 915亦被使用為輸出，輸入接點。圖二十 一（B )中之連接點6 〇 5，在圖二十七中則是以邊電極 9 14&，9141)來製作。91“用以連接帶狀線916，而914匕用以Case No. 8810824Q V. Description of the invention (18) The pi-type capacitor group between 601,602, 604, 605 in Figure 23 (B) is made of metal plates 818, 820 in Figure 28. The pi-type capacitor bank between 602, 603, 605, and 606 in FIG. 22 (B) is made of metal plates 820, 819 in FIG. 28, and it is between 60 and 203 in FIG. 23 (B). The inductance between 4 and 605 is made by the strip line Η in Figure 28. The inductor between 605 and 606 in Figure 23 (B) is made by the strip line 816 in Figure 28. The connection points 604, 605, 606 in Fig. 23 (3) are made with edge electrodes 8 丨 3, 8 14, 815 in Fig. 28. The edge electrodes 8 1 3 and 8 1 5 in Figure 20 ^ are also used as output and input contacts. The connection point 605 in Fig. 22 (B) is made with side electrodes 814a, 814b in Fig. 28. 814a is used to connect the stripline 816, and 8Hb is used to connect the stripline 817. In addition, in Figure 28, 801, 802, and 803 are grounded metal plates, and 802 is also used as an electromagnetic insulation layer. In Figure 28, 805 ~ 809 are dielectric layers or ceramics. —, Figure 2 = Pi of the three (B) between 6 01, 602, 604, 605 ^ The set of Pi-type electricity ^ is made from the metal plate 918, 920 in Figure 29. The pi-type capacitor bank between 6 02, 603, 605, and 606 in Figure 22 (B) is made of metal plates 9 20, 919 in Figure 29, and in Figure 23 (B) The inductor between 604 and 605 is made with the strip line 917 in Figure 29. The inductor between 605 and 606 in Figure 23 (B) is made by the strip line 916 in Figure 2. Figure-+-(Only, from ♦, from above. ^ Laoshan ^ The connection points 604, 606 in Figure 12 (B), and in Figure 19 are the side electrodes 913, 914, 915 Production. The electric probe Γ3, 915 is also used as the output and input contact. The connection point 6 0 5 in Figure 21 (B), and the side electrode 9 14 & 9141 in Figure 27) To make. 91 "to connect the stripline 916, and 914 to
第22頁 480813 _MM 88108249__年月日 修正_ 五、發明說明（19) 連接帶狀線9 17。另外在圖二十九中9〇19〇2,9〇3為接地金 屬板，而902則亦被使用為電磁隔絕層。而在圖二十九中 905〜910則為介質層或陶瓷體。 圖二十七至圖二十九除了電容性金屬板間相互幾何位 置不同外，實屬同一種實施例，在圖二十七中，三片金屬板 718,719,720被放置於不同之三層7〇8,7〇9,71〇上，而中間 之電谷板720則放置於710介質層上。在圖二十八中，金屬 板818, 819被放置於同一個介質層8〇8之上而中間之電容板 820則置於另一介質層80 9之上，在圖二十九，三個金屬板 918,919,920亦分別被放罝於不同之介質板91〇 9〇9 9〇8之 上，而中間之電谷板920則被置於介質層909之上並位於918 及91 9之上。 上述之電容性金屬板之各種擺置，完全視所須電容值， 電路板之厚度安排，及電路模組之整合方式而定。一般而 言，在電路面積有限制之下，須要較大電容數值時，則金屬 板間之厚度必須要較薄。另外如圖二十九中之金屬板之擺 置，可以避免金屬板918及919間之直接耦合，因為金屬板 318(415, 718, 818)及31 9(41 6, 719, 819)間若有太強之耦合 則電路性能可能變差。 圖三十所示為一條帶狀線3 001被曲折及放置放介質層 3002上，在圖八中之傳輸線或圖二十四至二十九之帶狀線 皆可以此方式製作。 圖三十一所示為一條以螺旋狀安排之帶狀線3丨〇丨，在 圖八中之傳輸線或圖二十四至二十九之帶狀線皆可以此方 式製作。在圖三十一中，帶狀線3 101被置於介質層3102之Page 22 480813 _MM 88108249__ year, month, day, amendment _ V. Description of the invention (19) Connect strip line 9 17. In addition, in Fig. 29, 907,002 and 903 are grounded metal plates, and 902 is also used as an electromagnetic insulation layer. In Figure 29, 905 ~ 910 are dielectric layers or ceramic bodies. Figures 27 to 29 are the same embodiment except that the capacitive metal plates have different geometrical positions. In Figure 27, three metal plates 718,719,720 are placed on three different layers 708. 709,71, and the middle electric valley plate 720 is placed on the 710 dielectric layer. In Fig. 28, metal plates 818, 819 are placed on the same dielectric layer 808 and the middle capacitor plate 820 is placed on another dielectric layer 80 9. In Fig. 29, three The metal plates 918, 919, 920 are also placed on different dielectric plates 9109, 90.8, and the middle valley plate 920 is placed on the dielectric layer 909, and is located on 918 and 9119. The various placements of the above-mentioned capacitive metal plates depend entirely on the required capacitance value, the thickness arrangement of the circuit board, and the integration mode of the circuit module. Generally speaking, when the circuit area is limited, when a large capacitance value is required, the thickness between the metal plates must be thin. In addition, as shown in the metal plate in Figure 29, the direct coupling between metal plates 918 and 919 can be avoided because the metal plates 318 (415, 718, 818) and 31 9 (41 6, 719, 819) If there is too strong coupling, the circuit performance may deteriorate. Figure 30 shows that a strip line 3 001 is twisted and placed on the dielectric layer 3002. The transmission line in Figure 8 or the strip lines in Figures 24 to 29 can be made in this way. Figure 31 shows a strip line 3 丨 〇 丨 arranged in a spiral pattern. The transmission line in Figure 8 or the strip lines in Figures 24 to 29 can be made in this way. In FIG. 31, the strip line 3 101 is placed between the dielectric layers 3102
第23頁 480813 _案號88108249_年月日 條正_ 五、發明說明（20) 上，並有兩個端點，第一個端點為3105，第二個端點3107則 藉由穿孔3104連至不同層之另一條帶狀線3103。 本發明參照特定實施例來說明及圖示但並非以此限制 本發明，熟習此項技藝者可以實施若干修改及變動而沒有 脫離上述實施例及下文之申請專利範圍所述的發明原理。Page 23 480813 _Case No. 88108249_ Year, Month, and Day Article _ V. The description of the invention (20) has two endpoints, the first endpoint is 3105 and the second endpoint 3107 is perforated 3104 It is connected to another strip line 3103 of a different layer. The present invention is described and illustrated with reference to specific embodiments but is not limited thereto. Those skilled in the art can implement several modifications and changes without departing from the principles of the invention described in the above embodiments and the scope of patent applications below.
第24頁 480813 _案號 88108249_年月日__ 圖式簡單說明 圖一為傳統高頻低通濾波器之外觀圖。 圖二為圖一中之濾波器之等效電路圖。 圖三為另一個傳統之高頻低通濾波器之外觀圖。 圖四為圖三中之濾波器之等效電路圖。 圖五為先前技術之蛇形濾波器之外觀圖。 圖六為圖五中之濾波器之等效電路圖。 圖七為本發明之集總式等效電路圖。 圖八為本發明之半集總式之等效電路圖。 圖九為圖七，圖八電路中當k = 2及j = l之性能圖。 圖十為圖七，圖八電路中當k=3及j = 2之性能圖。 圖十一〜十八為圖七及圖八中之pi型電容組之各式具 體作法。 圖十一及十二為以微帶線方式來製作pi型電容組。_ 圖十三及十四為以帶狀線方式來製作pi型電容組。 圖十五（A ) 為利用兩電極片夾介電層以產生電容。 圖十五（B) 為利用多片電極片夾介電層以產生較大數 值電容。 圖十六〜十七為以MIM之方式來製作pi型電容組。 圖十八為電容組之輸出，輸入之另一種安排方式。 圖十九〜二十二為圖七及圖八中之傳輸線節之各式具 體作法。 圖十九為微帶線結構。 圖二十為帶狀線結構。 圖二十一為多層帶狀線結構。 圖二十二為混合微帶線及帶狀線結構。Page 24 480813 _Case No. 88108249_Year Month Day__ Brief Description of Drawings Figure 1 shows the appearance of a traditional high-frequency low-pass filter. Figure 2 is an equivalent circuit diagram of the filter in Figure 1. Figure 3 is an external view of another conventional high-frequency low-pass filter. Figure 4 is an equivalent circuit diagram of the filter in Figure 3. FIG. 5 is an external view of a snake filter of the prior art. Figure 6 is an equivalent circuit diagram of the filter in Figure 5. FIG. 7 is a lumped equivalent circuit diagram of the present invention. FIG. 8 is an equivalent circuit diagram of the semi-lumped type of the present invention. Figure 9 is the performance graph when k = 2 and j = l in the circuit of Figure 7 and Figure 8. Figure 10 is the performance graph when k = 3 and j = 2 in the circuit of Figure 7 and Figure 8. Figures 11 to 18 show various specific methods of the pi-type capacitor bank in Figures 7 and 8. Figures 11 and 12 show how to make a pi-type capacitor bank using microstrip lines. _ Figures 13 and 14 show the pi-type capacitor bank in stripline mode. Figure 15 (A) shows the use of two electrode pads to sandwich a dielectric layer to generate capacitance. Figure 15 (B) shows the use of multiple electrode pads to sandwich the dielectric layer to generate a larger value capacitance. Figures 16 to 17 show how to make a pi-type capacitor bank using MIM. Figure 18 shows another arrangement of the output and input of the capacitor bank. Figures 19 to 22 show various specific methods of the transmission line sections in Figures 7 and 8. Figure 19 shows the microstrip line structure. Figure 20 shows the stripline structure. Figure 21 is a multilayer stripline structure. Figure 22 is a hybrid microstrip line and stripline structure.
第25頁 480813 _案號88108249_年月日 修正_ 圖式簡單說明 圖二十三（A )為圖二十四之低通濾波器之集總式等效 電路。 圖二十三（B )為圖二十五~二十九之低通濾波器之集總 式等效電路。 圖二十四為圖八中等效電路k = 2及j = l之具體實施例。 圖二十五〜二十九為圖八中等效電路k = 3及j = 2之具 體實施例。 圖三十為圖八中等效電路之傳輸線安排為曲折式形 式。 圖三十一為圖八中等效電路之傳輸安排為螺旋式形 式。Page 25 480813 _Case No. 88108249_ Year, Month, Day, Amendment_ Brief Description of Drawings Figure 23 (A) is the lumped equivalent circuit of the low-pass filter shown in Figure 24. Figure 23 (B) is the lumped equivalent circuit of the low-pass filter shown in Figures 25 to 29. FIG. 24 is a specific embodiment of the equivalent circuits of k = 2 and j = 1 in FIG. Figures 25 to 29 are specific embodiments of the equivalent circuits k = 3 and j = 2 in Figure 8. Figure 30 shows the zigzag arrangement of the transmission line of the equivalent circuit in Figure 8. Figure 31 shows the transmission arrangement of the equivalent circuit in Figure 8 in a spiral form.
第26頁Page 26
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| TW88108249A TW480813B (en) | 1999-05-20 | 1999-05-20 | Miniaturized multi-layered ceramic low-pass filter |
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| TW88108249A TW480813B (en) | 1999-05-20 | 1999-05-20 | Miniaturized multi-layered ceramic low-pass filter |
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| US9252078B2 (en) | 2013-03-25 | 2016-02-02 | Fujitsu Limited | Semiconductor device |
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| US9252078B2 (en) | 2013-03-25 | 2016-02-02 | Fujitsu Limited | Semiconductor device |
| TWI550817B (en) * | 2013-03-25 | 2016-09-21 | 富士通股份有限公司 | Semiconductor device |
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