TW480734B - Method for producing thin film transistor (TFT) with transversal polysilicon - Google Patents

Abstract

The present invention discloses a method for producing a thin film transistor (TFT) with a transversal polysilicon, which comprises: providing an insulative substrate deposited with an amorphous silicon film thereon; forming a seed on the substrate; performing a local annealing on a portion of the amorphous film to form a laterally-grown die, in which the amorphous silicon film is defined as an active region; sequentially depositing a dielectric layer and a polysilicon layer on the active region, in which the dielectric layer and the polysilicon layer are a gate structure; using the gate structure as a mask and implanting a plurality of ions into the active region to form a source/drain region.

Description

480734 V. Description of the Invention (1) 5-1 Field of the Invention: The present invention relates to a method for manufacturing a thin film transistor, and more particularly to a method for manufacturing a thin film transistor having lateral polycrystalline silicon. 5-2 Background of the Invention: A conventional metal-initiated crystallization (MIC) process method is to use low temperature treatment to crystallize amorphous silicon, and then deposit some kinds of metal layers on multi-g crystalline silicon. Due to the low temperature process, it is beneficial to crystallize amorphous silicon in a metal-initiated crystallization process. However, in the application of metal-initiated crystallization process in electronic components, as the metal flows into the crystalline silicon film, a metal layer is formed at the bottom, which will cause the internal characteristics of polycrystalline silicon to deteriorate. Figures A through C are side cross-sectional views of a conventional thin-film transistor manufacturing channel region using a conventional metal-induced lateral crystallization process. Referring to FIG. 1A, an amorphous silicon layer is formed like an active region 110, which is partially repaired on an insulating substrate with a punched film (not shown in the figure), and patterned by lithography and etching techniques. Active area 1 1 0, gate insulation layer 1 2 0 and gate structure 130 ° are formed in active area 11 0 by a conventional process method

480734 V. Description of the invention (2) Referring to the first figure B, a nickel layer of 140 thickness is formed on the entire surface of the structure by base nickel plating. By heavily doping the entire surface with the impurity structure, a source region 110 S and a drain region 110 D are formed on a part of the active region 110. The source region 1 1 0 S and the drain region 1 1 0 D form a channel region 1 1 0 C on the substrate 100. Referring to the first figure C, the polycrystalline silicon in the active region 110 is crystallized by heating the substrate 100 at a temperature between 35 ° C and 500 ° C. A nickel layer 140 is then formed at the source On the 1 1 S and D 1 10 D areas, the M IC area becomes fragmented by the M IC process. The recording layer 140 is not formed directly in the channel area 1 10 C, so the channel area 110C becomes In the MILC region, silicon is crystallized by the MILC process. The source 1 10 S and the drain 1 10 D regions activate impurities, and polycrystalline fragments crystallize on the active region 1 10 during the heat treatment. The conventional thin film described above The manufacturing method of the transistor, with the channel region 1 1 0 C as the boundary, is defined as connecting the fragmented crystal structure on the surface of the MIC region to the M LC region. Because the connection boundary is located between the M IC region and the M LC region, the channel The region joins the source and drain regions, showing the difference in crystal structure and metal contamination from the MIC region adjacent to the MIC region. Therefore, this connection method allows the thin-film transistor to open immediately to form a snare_ (trap) 'Thus causing instability in the channel area And the deterioration of the interior of the film-bound transistor. Accordingly, there is a strong desire to seek a thin film transistor with lateral polycrystalline silicon.

480734 V. Description of the invention (3) Manufacturing method. This method can not only improve the flatness of the interface, increase the grains of large polycrystalline silicon channels and laterally grown grains, and increase carrier mobility, but also overcome traditional grain formation. Lack of methods. 5-3 Objects and Summary of the Invention: In view of the many shortcomings of the conventional thin film transistor process in the above background of the invention, the present invention provides a manufacturing method for forming a thin film transistor with lateral polycrystalline silicon, which can improve the traditional process. Carrier Migration || The main object of the present invention is to provide a method for manufacturing a thin film transistor having lateral polycrystalline silicon, which can improve the problem of carrier mobility. Another object of the present invention is to provide a manufacturing method for forming a thin film transistor having lateral polycrystalline silicon, which has a simple process, a low-temperature process, and a high carrier mobility. Yet another object of the present invention is to provide a method for forming a thin film transistor having lateral polycrystalline silicon, which has the advantages of improving the flatness of the interface, increasing the crystal grain size of the polycrystalline silicon channel, and increasing the lateral mobility of the crystal grains. According to the above object, the present invention discloses a method of forming

Page 6 480734 V. Description of the invention (4) A method for manufacturing a silicon thin film transistor. First, an insulating substrate is provided. An amorphous silicon film is deposited on an insulating substrate, and then a pregnant core is formed by partially annealing the amorphous silicon film to form a side-growth grain by annealing the amorphous silicon film. The amorphous silicon film is defined as an active silicon film. Area, and then, a dielectric layer and a polycrystalline silicon layer are successively deposited on the active area, in which the dielectric layer and the polycrystalline silicon layer are a gate structure. Ions enter the active region to form a source / dead region. The purpose and many advantages of the present invention will become apparent from the following detailed description of the preferred embodiments and with reference to the accompanying drawings. Detailed description of the preferred embodiments 5-4: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents. Figures 2A to 2G are the preferred embodiments of the present invention, and are side sectional views of a thin film transistor having a lateral polycrystalline stone. Referring to FIG. 2A, an insulating substrate 200 is first provided, such as a transparent plate. A thin film 210 is formed on a transparent plate. The thin film may be an amorphous silicon and may be formed by a chemical deposition method such as plasma CVD, APCVD, and LPCVD. most

480734 V. Description of Invention (5) " " '-It is better to use LPCVD. The second and one B pictures are enlarged views of the osmium film 2 1 0. By local annealing, an exCimer laser system 40 is used to illuminate the amorphous silicon film 2 1 0 regionally. A seed nucleus (seed) 20 is generated in a molten state at 2 10 °. Then the excimer laser system 40 is used to anneal at a low temperature of 400-500. ^ Cangzhao two C picture, and then, under the rapid annealing process, the above-mentioned pregnancy nucleus 20 was changed to k to grow lateral grains 60. In this annealing process, the growth of the pregnant nucleus 20 is performed by lateral growth to form laterally grown grains 60. Therefore, the amorphous silicon film 2 1 0 is now a polycrystalline thin film. Referring to the second D diagram, the amorphous silicon layer is regarded as the active region 2 1 0 a on the substrate 2 0. The active region 21 a was deposited by a low-pressure chemical method and patterned by lithography to form a thickness of about 100 angstroms. Then, a dielectric layer 2 200 is formed by a plasma enhanced chemical vapor deposition method to a thickness of about 400 angstroms. The dielectric layer 2 2 0 can be a dioxide layer. The gas is deposited by atmospheric pressure CVD at a pressure of 0.5 ~ ltorr and a temperature of 400 ~ 50 0 ° C. Or use SiH4 as φ as the reaction gas, and deposit it by plasma enhanced CVD at a pressure of 100 Torr and a temperature of 300 ~ 400 ° C. In addition, TEOS / 0 3 can be used as a reaction gas, and deposited by plasma enhanced CVD (plasma enhanced CVD). The metal layer is then used to deposit the gate junction by a base plating method.

II m

480734 V. Description of the invention (6) The structure 2 3 0 is formed on the dielectric layer 2 2 0 to a thickness of about 5 0 0 Angstroms. The metal layer is patterned by lithography to form a dielectric layer 2 2 0. The gate structure 2 3 0 is transferred to the dielectric layer 2 2 0 by lithography. The gate structure 2 3 0 is used to etch the dielectric layer 2 2 0 as a mask. Referring to the second E diagram, the source region 2 1 0 S and the drain region 2 1 0 D are formed on the active region 2 1 0 a by using a high concentration ion value distribution method on a part of the active region 2 1 0 a. The dielectric layer 220 and the gate structure 230 function as a doped photomask. Referring to FIG. 2F, the plasma-enhanced chemical vapor deposition method is used to form a low-temperature silicon oxide 2 40 with a thickness of about 2000 to 300 angstroms. The lithographic pattern defines the contact holes 2 3 0 in the gate electrode 2 3 0, the source electrode 2 1 0 S and the drain electrode 2 1 0 D. Referring to the second figure G, a metal layer 2 60 having a thickness of about 50 Angstroms is formed on the formed structure by means of vapor deposition of aluminum. This metal layer contains aluminum. The aluminum metal 260 is then isotropically etched on the contact area 250. The thin film transistor with lateral polycrystalline silicon provided by the method of the present invention has the following advantages: 1. Provide a method for manufacturing a thin film transistor with lateral polycrystalline silicon, which can improve the problem of carrier mobility.

480734 V. Description of the invention (7) 2 · Provide a method for manufacturing a thin film transistor with lateral polycrystalline silicon, which has a simple process, a low temperature process, and a high carrier mobility. 3. Provide a method for manufacturing a thin film transistor with lateral polycrystalline silicon, which can improve the flatness of the interface, and increase the crystal grains of the polycrystalline silicon channel and laterally grown grains can also increase the carrier mobility. The above are only examples of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following applications Within the scope of the patent.

Page 10 480734 Schematic illustrations Figures A through C are side cross-sectional views of the conventional thin film transistor manufacturing channel area using a conventional lateral crystallization process; Figures A through G are the present invention. The preferred embodiment is a side sectional view of a thin film transistor having lateral polycrystalline silicon. Representative symbols of the main part ... 100 ^ 200 Substrate 20 Laser regional irradiation 40 Pregnancy nucleus 60 Lateral growth grain 210 Thin film 11 (L · 210 a Active region 1 1 0 S, 21 OS Source region 1 1 0 D, 21 0D Drain region 110C Channel region 1 20 > 22 0 Dielectric layer 130 > 230 Gate structure 140 Nickel layer 240 Low temperature silicon oxide 250 Contact hole 260 Metal layer

Claims (1)

480734 VI. Application Patent Scope 1. A method for manufacturing a thin film transistor including at least providing an insulating substrate; depositing an amorphous broken film on the insulating substrate; forming a pregnant nuclei by partially annealing the partially amorphous Forming a silicon thin film; forming a side-growth crystal grain by annealing the amorphous silicon thin film, wherein the amorphous silicon thin film is defined as an active region; a dielectric layer and a polycrystalline silicon layer are sequentially deposited on the active region; removed Part of the dielectric layer and the polycrystalline silicon layer form a gate structure; and using the gate structure as a mask, implanting a plurality of ions into the active region to form a source / dead region. 2. The method according to item 1 of the patent application range, wherein the above-mentioned insulating substrate is a transparent plate. 3. The method according to item 1 of the scope of patent application, wherein the above-mentioned amorphous silicon thin film is formed at a temperature of 450-550 ° C. 4. The method as described in the first item of the patent application, wherein the above-mentioned nucleus formation is performed by an excimer laser system. 5. The method according to item 1 of the scope of patent application, wherein the formation of the above-mentioned lateral growth crystal grains is by lateral growth of the gestation nucleus. 6. The method as described in item 4 of the patent application, wherein the above-mentioned excimer laser Page 12 480734 6. Scope of patent application The system is to irradiate the amorphous silicon thin film with a regional irradiation method. 7. The method according to item 4 of the scope of patent application, wherein the formation temperature of the above-mentioned laterally grown crystal grains is between 400 °-500 ° C. 8. The method according to item 1 of the patent application range, wherein the above active area is formed by lithography and etching techniques. 9. The method according to item 1 of the patent application scope, wherein the above-mentioned dielectric layer includes at least SiO2. 10. The method according to item 1 of the scope of patent application, wherein the thickness of the above-mentioned dielectric layer is between 450 and 550 angstroms. 11. The method according to item 1 of the patent application range, wherein the above-mentioned dielectric layer is deposited by a plasma enhanced chemical vapor deposition method. 12. The method according to item 1 of the scope of patent application, wherein the thickness of the above-mentioned gate electrode is between 2000 and 300 angstroms. 13. The method according to item 1 of the scope of patent application, wherein the above-mentioned gate is formed by lithography technology. 14. The method according to item 1 of the scope of patent application, wherein the source and drain electrodes described above Page 13 480734 VI. Scope of patent application Zones are formed by high concentration ion value cloth. 1 5. A method for manufacturing a thin film transistor, which at least includes: providing an insulating substrate; depositing an amorphous silicon film on the insulating substrate; forming a pregnancy core by an excimer laser system to locally anneal the portion Amorphous silicon thin film; forming a side-growth crystal grain by annealing the lateral growth of the nucleus; an amorphous breaking film; wherein the amorphous hair layer is defined as an active region, and a dielectric layer is successively deposited and A polycrystalline silicon layer on the active region; removing a part of the dielectric layer and the polycrystalline silicon layer to form a gate structure; and using the gate structure as a mask, implanting a plurality of ions into the active region to form a source electrode / Drain region. 16. The method according to item 15 of the scope of patent application, wherein the above-mentioned insulating substrate is a transparent plate. 1 7. The method according to item 15 of the scope of patent application, wherein the above-mentioned amorphous silicon thin film is formed at a temperature of 4 5 0 _ 5 50 ° C. 1 8. The method according to item 15 of the scope of patent application, wherein the formation temperature of the above-mentioned laterally grown grains is between 400 °-500 ° C. 19. The method according to item 15 of the scope of patent application, wherein the above-mentioned excimer mine Page 14 480734 VI. Scope of patent application The irradiation system is used to illuminate the amorphous silicon film with a regional irradiation method. 2 ◦. The method according to item 15 of the scope of patent application, wherein the above active area is formed by lithography and etching techniques. 2 1. The method according to item 15 of the scope of patent application, wherein the above-mentioned dielectric layer contains at least silicon dioxide. 2 2. The method according to item 15 of the scope of patent application, wherein the thickness of the dielectric layer is between 400 and 100 angstroms. 23. The method according to item 15 of the scope of patent application, wherein the above-mentioned dielectric layer is deposited by a plasma enhanced chemical vapor deposition method. 2 4. The method according to item 15 of the scope of patent application, wherein the thickness of the gate electrode is between 2000 and 300 angstroms. 25. The method according to item 15 of the scope of patent application, wherein the above-mentioned gate is formed by a lithography technique. 26. The method according to item 15 of the scope of patent application, wherein the above-mentioned source and drain regions are formed by a high-concentration ion value distribution method. 2 7, a method for manufacturing a thin film transistor, which includes at least: Page 15 480734 6. The scope of the patent application provides an insulating substrate; depositing an amorphous silicon thin film on the insulating substrate; irradiating a part of the amorphous silicon thin film to form a pregnant core on the amorphous silicon thin film, and using the excimer lightning Radiation system; annealing the amorphous silicon film to form a multi-grain film with laterally grown grains, successively depositing a dielectric layer and a polycrystalline layer on the active region; removing a portion of the dielectric layer and The polycrystalline silicon layer is used to form a gate structure; and the gate structure is used as a mask to implant a plurality of ions into the active region to form a source / dead region. 28. The method according to item 27 of the scope of patent application, wherein the above-mentioned insulating substrate is a transparent plate. 29. The method according to item 27 of the scope of patent application, wherein the above-mentioned amorphous silicon thin film is formed at a temperature of 4 50-5 0 ° C. 30. The method according to item 27 of the scope of patent application, wherein the lateral growth of the above-mentioned grains is formed by lateral growth of the gestation nucleus. 3 1. The method according to item 27 of the scope of patent application, wherein the above-mentioned excimer laser system irradiates the amorphous silicon thin film with a regional irradiation method. 32. The method according to item 27 of the scope of patent application, wherein the above-mentioned lateral growth Page 16 480734 VI. Scope of patent application The temperature of the grain formation system is between 400 ° C and 500 ° C. 3 3. The method according to item 27 of the scope of patent application, wherein the above active area is formed by lithography and etching techniques. 34. The method according to item 27 of the scope of patent application, wherein the above-mentioned dielectric layer contains at least stone dioxide. 35. The method according to item 27 of the scope of patent application, wherein the thickness of the dielectric layer is between 400 and 100 angstroms. 36. The method according to item 27 of the scope of patent application, wherein the above-mentioned dielectric layer is deposited by a plasma enhanced chemical vapor deposition method. 37. The method according to item 27 of the scope of patent application, wherein the thickness of the above-mentioned gate electrode is between 2000 and 300 angstroms. 38. The method according to item 27 of the scope of patent application, wherein the above-mentioned gate is formed by lithography technology. 39. The method according to item 27 of the scope of patent application, wherein the above-mentioned source and drain regions are formed by a high-concentration ion value distribution method. Page 17