480720 五、發明說明（1) 發明背景 發明頜域 本發有關一種溝渠式功率M0SFET裝置及其製造方法， 且更特別地有關一種降低磊晶層電阻値之溝渠式功率 MOSFET裝置及其製造方法。 相關技術說明 大致地，如第1 - 1至1 - 4圖中所示，係顯示習知之溝 渠式功率MOSFET裝置的製程步驟及其完成結構圖。通常 ，溝渠式功率MOSFET裝置之導通電阻値主要來自（1)封 裝電阻値Rp ，（2)接觸電阻値Rc，（3)通道電阻値Rch ，（4)磊晶層電阻値Repi。目前在功率MOSFET之發展上 ，正朝向如何取得低的導通電阻値R ο η，減少功率消耗而 努力。 然而，如第1-4圖中所示，習知之溝渠式MOSFET裝置 之電子流（I ( e —))會因溝渠式閘極下方之反轉層所致而使 得通道之電子流快速地從通道經由溝渠式閘極下方之反 轉層經磊晶層1 b '流至基板1 a '，也就是汲極9，亦即， 電子流將大部分地聚集在溝渠式閘極下方，使得源極7 下方之磊晶層1 b '只有少數電流流過，造成該溝渠式 MOSFET之磊晶層電阻値Repi變大，而影響導通電阻値 Ron，使導通電阻値之降低面臨瓶頸，此現象可由先前之 文獻 ref[l，2]觀察到（其中[i]ViCT0R Α·Κ· TEMPLE, ROBERT P. LOVE, and PETER V. Gray "A 600-Volt 480720 五、發明說明（2) MOSFET Designed for low On-ResistanceM , 1 980 IEEE Trans, on Electron Devices，第 343-349 頁；以及[2] S. L. SUN and James D. PLUMMER， "Modeling of the On-Resistance of LDMOS , VDMOS and VMOS Power Transistor" 1980 IEEE Trans. On Election Devices, 第3 56 - 367頁）。由於溝渠式功率MOSFET之導通電阻値 有極大成分係Repi，一旦Repi可以再降低，則對於溝 渠式功率MOSFET而言，將在功能上更具效益。 因此，有必要發展出一種可減少電流聚集之現象而使 磊晶層電阻値降低之溝渠式功率MOSFET裝置及其製造方 法，使得導通電阻値可更進一步地減少而操作溫度可大 幅地降低。 發明槪述 所以，爲克服上述習知技術之溝渠式功率MOSFET裝置 的電流聚集現象之問題。本發明之目的在於提供一種降 低磊晶層電阻値之溝渠式功率MOSFET裝置及其製造方法 ，其中該裝置係採用一相同於源極區之導電型之摻雜物 的額外之磊晶層構造，而使電子流能在溝渠式閘極下方 平面地擴散且均勻地流至汲極端，使磊晶層電阻値Rep i 降低，藉此進一步地降低導通電阻値。 爲達成本發明之上述目的’根據本發明之觀點，提供 一種降低磊晶層電阻値之溝渠式功率MOSFET裝置之製造 方法，該方法包含下列步驟： 480720 五、發明說明（3) 1 )成長磊晶層晶圓，使依序地具有第一層第一導電型 重摻雜多晶矽層當作汲極，第一導電型微摻雜層，第二 層第一導電型重摻雜層，及第二導電型輕摻雜層，其中 此步驟亦可經由傳統功率MOSFET之磊晶結構經由離子布 植步驟來達成； 2 )以光罩離子佈植第一導電型重摻雜層阱當作源極區 ，然後去除光罩； 3 )以光罩蝕刻出溝渠閘極區至第二層第一導電型重摻 雜層之區，然後去除該光罩； 4 )成長氧化矽於溝渠側壁當作絕緣物，並充塡該溝渠 以多晶矽而構成多晶矽閘極，接著成長硼磷矽酸鹽玻璃 (BPSG)以保護該多晶矽閘極；以及 5 )金屬化源極區之接點。 進一步地，根據本發明，提供一種降低磊晶層電阻値 之溝渠式功率MOSFET裝置，其中該裝置係採用一相同於 源極區之導電型之摻雜層的額外之磊晶層構造’其中該 額外之磊晶層構造，亦即，該第二層第一導電型重摻雜 層之厚度爲〇 . 1至0 . 5微米，摻雜物之濃度爲磊晶層， 亦即，該第一導電型微摻雜層之摻雜物濃度的1至3倍 。，而使電子流能在溝渠式閘極下方平面地擴展且均勻 地流至汲極端，使磊晶層電阻値Repi降低，藉此進一步 地降低導通電阻値。 480720 五、發明說明（4 ) 本發明之上述與其他目的，特性及優點將從下文結合 附圖之詳細說明中呈更明顯，其中 第1 - 1至1 - 4圖係槪略圖，顯示習知技術溝渠式功率 M0SFET裝置之製造過程，其中第1-4圖係完成圖及顯示 其電子流流動及聚集之情形。 第2-1至2-4圖係槪略圖，顯示根據本發明之溝渠式 功率M0SFET裝置之製造過程，其中第2-4圖係完成圖及 顯示其使電子流能在溝渠式閘極下方平面地擴展且均勻 地流至汲極之功效。 發明詳細說明 理論上，若溝渠式功率M0SFET裝置不考慮封裝電阻値 Rp及接觸電阻値Rc時，則該裝置之導通電阻値Ron僅爲 通道電阻値Rch與磊晶層電阻値Repi之和，即，Ron = Rch + Repi。習知地，如本說明書之前文所述，因爲習知 技術溝渠式功率M0SFET裝置之磊晶層lb'之電流不均勻 之故，如第1-4圖中所示，聶晶層lbf電阻値Repi可化 簡爲R e p i X [ ( P t ) / A ] * f ’其中p係磊晶層1 b '電阻値 係數，t係磊晶層1 b'厚度，A係裝置面積，f係形貌 因數（topological factor) ’其中習知裝置之形貌因數 大於1，而根據本發明可將f降低至1之理想値。 首先，如第2 - 1圖中所示，顯示一磊晶晶圓1，其中基 板1 a係摻雜有N +摻雜物之第一層多晶5夕層當作汲極金屬 歐姆接觸區，依序地在其上成長有N —多晶矽層1 b ’第二 480720 五、發明說明（5) 層N+多晶矽層1 d及P —多晶矽層1 c而形成4層之磊晶 晶圓1 ;接著’如第2 - 2圖中所示，以光罩（未圖示）離子 布植N +摻雜物而形成源極區2，然後去除光罩（未圖示）； 接著，以光罩1 0蝕刻出溝渠閘極區3至第二層N+多晶 矽層1 d的深度，然後去除光罩1 0，如第2 - 3圖中所示； 然後，成長氧化矽8於溝渠3側壁並充塡該溝渠3有多 晶矽而構成P_多晶矽閘極5，接著成長硼磷矽酸鹽玻璃 (BPSG ) 6以保護該多晶矽閘極5 ;以及，最後使源極區 金屬化而形成源極區之接點7，如第2 - 4圖中所示。 因此，如第2 - 4圖中所示，根據本發明，可提供一種 降低磊晶層電阻値之溝渠式功率M0SFET裝置，其中該裝 置係採用一相同於源極區之導電型之摻雜物的額外之磊 晶層1 d構造，而使電流能在溝渠式閘極下方平面地擴展 且均勻分佈地流至汲極9端，使磊晶層lb電阻値Rep i 降低，藉此進一步地降低導通電阻値Ron。 此外，根據本發明之利用磊晶層成長技術以減少溝渠 式功率M0SFET裝置之磊晶層電阻値之影響可利用於高的 以及低的操作電壓之溝渠式功率M0SFET裝置，使電流能 在溝渠式閘極下方平面地擴展且均勻分佈地流至汲極。 雖然上述說明係以N通道功率M0SFET來加以描述，但 本發明亦可適用於P通道功率M0SFET，其中僅需將p改 爲N以及將N改爲P即可；熟習於本項技術者將理解 的是，本發明並未受限於上述說明，而是可允許種種修 480720 五、發明說明（6) 飾及變化，然而本發明將以所附錄之申請專利範圍之對 等意義及範疇予以闡釋。 符號說明 1,1' ....晶晶晶圓 1 b，1 b '.疊晶層 1 c，1 e .多晶砂層 2 .......源極區 3 .......溝渠閘極區 Id......N +多晶i夕層 5 .......多晶砂閘極 6 .......硼磷矽酸鹽玻璃（BPSG) 7 .......源極接點 8 .......閘極氧化物 9 .......汲極480720 V. Description of the invention (1) Background of the invention The invention relates to a trench-type power MOSFET device and a manufacturing method thereof, and more particularly to a trench-type power MOSFET device and a manufacturing method thereof for reducing the epitaxial layer resistance. Description of the Related Art Generally, as shown in Figures 1-1 to 1-4, the process steps and completed structure diagrams of a conventional trench power MOSFET device are shown. Generally, the on-resistance 沟 of a trench power MOSFET device mainly comes from (1) package resistance 値 Rp, (2) contact resistance 値 Rc, (3) channel resistance 値 Rch, and (4) epitaxial layer resistance 値 Repi. At present, in the development of power MOSFETs, efforts are being made on how to obtain a low on-resistance 値 R ο η and reduce power consumption. However, as shown in Figures 1-4, the electron flow (I (e —)) of the conventional trench MOSFET device is caused by the inversion layer under the trench gate, which makes the electron flow of the channel quickly The channel flows through the inversion layer below the trench gate through the epitaxial layer 1 b 'to the substrate 1 a', that is, the drain electrode 9, that is, the electron current will be mostly collected under the trench gate, so that the source The epitaxial layer 1 b 'under the pole 7 has only a small amount of current flowing, which causes the epitaxial layer resistance 値 Repi of the trench MOSFET to increase, which affects the on-resistance 値 Ron, so that the reduction of the on-resistance 面临 faces a bottleneck. The previous document ref [l, 2] observed (where [i] ViCT0R Α · Κ · TEMPLE, ROBERT P. LOVE, and PETER V. Gray " A 600-Volt 480720) 5. Description of the invention (2) MOSFET Designed for low On-ResistanceM, 1 980 IEEE Trans, on Electron Devices, pages 343-349; and [2] SL SUN and James D. PLUMMER, " Modeling of the On-Resistance of LDMOS, VDMOS and VMOS Power Transistor " 1980 IEEE Trans. On Election Devices, pages 3 56-367). Because the on-resistance of trench-type power MOSFETs has a very large component, Repi, once Repi can be reduced, it will be more functionally effective for trench-type power MOSFETs. Therefore, it is necessary to develop a trench-type power MOSFET device which can reduce the phenomenon of current accumulation and reduce the epitaxial layer resistance 及其 and its manufacturing method, so that the on-resistance 値 can be further reduced and the operating temperature can be greatly reduced. DISCLOSURE OF THE INVENTION Therefore, in order to overcome the problem of current accumulation in the trench-type power MOSFET device of the conventional technology described above. An object of the present invention is to provide a trench-type power MOSFET device with reduced epitaxial layer resistance and a manufacturing method thereof, wherein the device uses an additional epitaxial layer structure with the same conductivity type dopant as the source region. As a result, the electron current can be diffused flatly and uniformly to the drain terminal under the trench gate, so that the epitaxial layer resistance 値 Rep i is reduced, thereby further reducing the on-resistance 値. To achieve the above-mentioned object of the invention, according to the viewpoint of the present invention, a method for manufacturing a trench-type power MOSFET device with reduced epitaxial layer resistance is provided. The method includes the following steps: 480720 V. Description of the invention (3) 1) Growth A crystal layer wafer, which sequentially has a first layer of a first conductivity type heavily doped polycrystalline silicon layer as a drain, a first conductivity type lightly doped layer, a second layer of a first conductivity type heavily doped layer, and a first layer A lightly doped layer of two conductivity type, in which this step can also be achieved by an ion implantation step through the epitaxial structure of a conventional power MOSFET; 2) using a photomask to implant the first conductivity type heavily doped layer well as a source electrode Area, and then remove the photomask; 3) etch the trench gate region to the second layer of the first conductive type heavily doped layer with a photomask, and then remove the photomask; 4) grow silicon oxide on the side wall of the trench as insulation And fill the trench with polycrystalline silicon to form a polycrystalline silicon gate, followed by growing borophosphosilicate glass (BPSG) to protect the polycrystalline silicon gate; and 5) contacts in the metallized source region. Further, according to the present invention, a trench-type power MOSFET device with reduced epitaxial layer resistance is provided, wherein the device uses an additional epitaxial layer structure with the same doping layer as the conductivity type of the source region. An additional epitaxial layer structure, that is, the thickness of the second layer of the first conductive type heavily doped layer is 0.1 to 0.5 μm, and the concentration of the dopant is the epitaxial layer, that is, the first The dopant concentration of the conductive type micro-doped layer is 1 to 3 times. In this way, the electron current can be spread flatly under the trench gate and flow uniformly to the drain terminal, so that the epitaxial layer resistance 値 Repi is reduced, thereby further reducing the on-resistance 値. 480720 V. Description of the invention (4) The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description in conjunction with the drawings. Among them, Figures 1-1 to 1-4 are sketches showing conventional knowledge. The manufacturing process of the technology trench power MOSFET device, of which Figures 1-4 are completed diagrams and show the flow and accumulation of their electron flow. Figures 2-1 to 2-4 are schematic diagrams showing the manufacturing process of a trench-powered MOSFET device according to the present invention, of which Figures 2-4 are completed diagrams and show that they enable electron flow to be below the trench-type gate Ground spreads and flows evenly to the drain. Detailed description of the invention In theory, if the trench power M0SFET device does not consider the package resistance 値 Rp and contact resistance 値 Rc, the on resistance of the device 値 Ron is only the channel resistance 値 the sum of Rch and epitaxial layer resistance 値 Repi, namely , Ron = Rch + Repi. Conventionally, as described earlier in this specification, because the current of the epitaxial layer lb 'of the trench power MOS device of the conventional technology is not uniform, as shown in Figure 1-4, the resistance of the Nie crystal layer lbf is 値Repi can be simplified as R epi X [(P t) / A] * f 'where p is the epitaxial layer 1 b' resistance 値 coefficient, t is the epitaxial layer 1 b 'thickness, A is the device area, and f is the shape. Topological factor 'Where the topographic factor of the conventional device is greater than 1, the ideal can be reduced to 1 according to the present invention. First, as shown in Figure 2-1, an epitaxial wafer 1 is shown, in which the substrate 1 a is a first polycrystalline layer doped with N + dopants as the drain metal ohmic contact region. There are sequentially grown N-polycrystalline silicon layer 1b 'on the second 480720 V. Description of the invention (5) layer N + polycrystalline silicon layer 1d and P-polycrystalline silicon layer 1c to form a 4-layer epitaxial wafer 1; Next, as shown in Figs. 2-2, the source region 2 is formed by ion implanting N + dopants with a photomask (not shown), and then the photomask (not shown) is removed; 10 Etch the gate region 3 of the trench to a depth of 1 d of the second N + polycrystalline silicon layer, and then remove the photomask 10, as shown in Figures 2-3. Then, grow silicon oxide 8 on the sidewall of the trench 3 and fill it.沟 The trench 3 has polycrystalline silicon to form P_polycrystalline silicon gate 5, followed by growing borophosphosilicate glass (BPSG) 6 to protect the polycrystalline silicon gate 5; and finally, the source region is metallized to form the source region. Contact 7 is shown in Figures 2-4. Therefore, as shown in FIGS. 2 to 4, according to the present invention, a trench type power MOSFET device with reduced epitaxial layer resistance can be provided, wherein the device uses a dopant having the same conductivity type as the source region. The additional epitaxial layer 1 d structure, so that the current can spread flatly under the trench gate and flow uniformly to the drain 9 terminal, so that the resistance 値 Rep i of the epitaxial layer lb is reduced, thereby further reducing On resistance 値 Ron. In addition, the use of epitaxial layer growth technology in accordance with the present invention to reduce the effect of the epitaxial layer resistance of trench-type power M0SFET devices can be used in trench-type power M0SFET devices with high and low operating voltages, so that current can flow in trench-type The gate electrode extends flatly and evenly to the drain electrode. Although the above description is described by using N-channel power M0SFET, the present invention can also be applied to P-channel power M0SFET, where only p is changed to N and N is changed to P; those skilled in the art will understand The invention is not limited to the above description, but can allow various repairs 480720 V. Description of the invention (6) Decoration and changes, however, the invention will be explained in terms of equivalent meanings and scope of the appended patent application scope . DESCRIPTION OF SYMBOLS 1,1 '.... Crystalline wafer 1 b, 1 b'. Superimposed layer 1 c, 1 e. Polycrystalline sand layer 2 ....... Source region 3 ..... ..Gutter gate area Id ... N + polycrystalline layer 5 ....... Polycrystalline sand gate 6 .. Borophosphosilicate glass (BPSG) 7 ....... source contact 8 ....... gate oxide 9 ....... drain