TW479356B - Circuit for performing the erasing procedure onto reference cell array of the split-gate flash memory device - Google Patents

Abstract

A kind of circuit structure for flash memory device is disclosed in the present invention. The flash memory device includes a memory cell array and a reference cell array. When a control logic apparatus performs reading action onto the memory cell array based on the input address, a reading current can be generated by a specific memory cell, and a reference current is generated by a reference cell, in which the reading current is compared with the reference current to judge the logic status of the read memory cell. The reference cell array can respond to a power on reset apparatus to conduct the erasing procedure so as to maintain the stored data of the reference cell. When a voltage supplied by a power source is input, the power on reset apparatus can transmit high-voltage signals to the reference cell array through a high-voltage apparatus in order to conduct the erasing procedure onto the entire reference cells and maintain the stored data of the reference cell.

Description

479356

Field of the Invention: The invention relates to a gate-separated flash memory in a integrated circuit, and the volume element == lt-gate flash is deleted, in particular, the memory of the reference cell array (reference ceu) = Related circuits and methods of erasing. Background of the Invention: M yuan: Hi-related design towels are often accompanied by the production of a considerable number of memory components in order to enhance the ability of electronic components to store data. Industry-type memory components, such as dynamic access memory (1) "Volatile memory such as 趵 or static access memory (SRAM), because the data stored in the power supply will be completely erased, so for some needs to be switched on the power supply: storage, you can still retain all For data entry systems, such as memory (ROM), programmable ROM (pROM), removable ROM (EPROM), electronic erasable programmable ROM Memory King II (EEPR0M), and flash memory (FLASH), etc ... Memory components that can continue to save input data in the power supply. Taking the EEPR0M flash memory device as an example, the program can be programmed or erased by two voltages passed to the memory cell, and whether to store data in the flash memory can be determined. In memory. Among them, the borrower performs a knowledge-based process and adjusts the

Page 4 479356

The two electronic teeth pass through the gate emulsification layer 'and are trapped in the fioatlng gate, and the memory unit is generated to a logic state. Conversely, when this data is no longer stored. of. Second, the red order is removed from the 1 order, so that the electrons trapped in the floating gate can be 1ΪΓ;: each :: electron on the pole. In this way, seeding is repeated; it is worth noting that the data stored in the memory unit can be controlled. It is worth noting that in the actual reading of EEPR0M, the reading current of the memory unit is compared by comparing the reading current of the memory unit (Ice⑴ and 贝贝 考 枓The size of the electrical Y y fef) determines the logic level of the memory cell as "factory or 0". Therefore, in order to provide a reference current for judging the logic level, in the related process design of flash memory, often Will produce corresponding reference cells when making brother memory cells. 11) Typical flash memory element architecture, in addition to the normal memory cell array, there are also reference cell arrays that provide reference currents. cell array). In this way, 'when the control logic (contr.ll.gic) device reads the cells in the memory cell array via the word line decoder (WL Decoder)', it can be output by the boost device (HV Block). The high voltage signal will cause the memory cell to generate a corresponding read current. At the same time, the control logic device also sends a signal to the reference cell array to generate the corresponding reference voltage.

Page 5 479356

= i t. In this way, by comparing the read current obtained from the memory unit with the reference current obtained from the multi-test 70 array, the logic state of the memory unit can be determined. It is important to note that when making the reference cell array, the logical state of all reference cells is always maintained by: / j ,, 仃 / Undivided program ’. That is, 'the reference cell array is maintained in a state where data rows are subtracted = ^ — so-then, the reference cell array is floated to the required reference current. However, due to the flow of bits; the charge will often produce a "gradual difference." After the minions, the reference current value will be wrong. At present, the reference unit reads the data in the memory unit in the program, so that the unit erases the action relative to the record. The operation of the memory unit is often under the signal. For example, when the data in the array is used, the data is erased to maintain the memory unit during the operation, and the erasing is performed when necessary to make it not the same, the life span, and then caused. By the same time, the data state is small and short. Therefore, under the same circumstances, the high-voltage signal memory element is distorted, and the number of words stored during the misjudgment sequence is more than the excessive flash charge required during the procedure. It is missing the related reference of the log. But in fact, the reference unit often leaks the data for a long time, and the memory unit configuration is set early. Because the maintenance of the reference log is reduced in units, the reading of the reference array is reduced. Meter, make the line erasure reference unit into the millions of erasure movement in the high-pressure test unit reading occurs 479356

error. Purpose and summary of the invention: ^ The purpose of the present invention is to provide a circuit design of a flash memory device so that the reference cell array can be automatically erased when the power supply voltage is supplied, and the data stored therein is maintained. The invention discloses a programmable flash memory device. Among them, the memory cell array has an array of plural 复 1J and bit line rows. The word line corresponding to the memory order number via the word line array is turned on for the operation signal and the address signal. Memory unit sequence, program execution. In addition, a high-voltage device between the clean line translator and the transponder can respond to the control signal and decode it with the first word line. To generate a single cell array corresponding to memory, there are a plurality of permutations. . It is taught that a second word speech line reference unit is coupled, and in response to the high erasing process of the reference cell array, it can be transferred to the high voltage device and the second word memory cell and distributed in the word line. In addition, the first wordline decoder element is coupled to the 'and responds to the column address column. A control logic device, in response to the first word speech decoder, the high-voltage signal generator turns on the programmed program, the erased program, and the control logic device and the first word logic device. The reference current of the element is input to the selected memory cell row, and a reference reference unit can be provided, and the second word line decoder can be used to connect the high voltage signal generated by the device through the word line to sequence. In addition, a power-on reset device

Page 7

Shi, Ming revealed a kind of flash memory: the smart unit and the reference unit array, and among them, can be the input of the power supply voltage of Ik, ^ to find

Pulse signal, and drive high-voltage device to generate high-voltage electricity = production: the array performs the erasing process to achieve maintenance; see 1 order; Cui's purpose. The detailed description of the present invention is as follows: the early and middle storage information reference, the first figure, which shows the programmable flash memory element 10 provided by the present invention. Among them, it is mainly used to store input data: J memory element is a memory cell array (memory cell ar) ray15. —,

In other words, this memory cell array 15 has millions of memory cells, which are distributed across the row of word 1 ine and the column of bit 1 ine. Into an array. Each of the 5 elements has a transistor element, which can transmit related control signals and data signals according to the word line and bit line passing through the memory unit, and program and erase the transistor element. Divide and read operations. In addition, the first word line decoder (word line decoder) 20

Page 8 479356 V. Description of the invention (6) The first word line translation number can be translated, and the phase line decoder 20 can set the word line sequence. Of course, except for the first bit line number , And lead to the memory word line of the specified row, and are connected with the memory array 5 of the memory. The main function of the encoder 20 is to respond to the word line corresponding to the column address signal. In other words, the first word here is regarded as a switching element, and is responsible for conducting the selection of the input signal in order to perform related actions on the memory cells in a specific row. In addition to the one-word speech line decoder 20, this memory cell array 5 is also a decoder (not shown in the figure), in response to the corresponding bit line row in the row address memory cell array 15, in order to Meta data signal. In addition, a control Is 2 0 'can respond to the signal transmitted by the decoder 2 0 for switching, and can be used to erase the program, or read the time (mass erase) time code 2 0, and select all words as Page shift 25 controls the removal of the first word. The one-word speech line decoding system makes the first word speech line logic device 25. The program is programmed to translate the first word speech line for the block removal process. On the contrary, the control logic device is used to perform the required logic device 25 connected to the above-mentioned operation signal and address signal. In other words, the fetching process is performed by controlling the selected memory unit. For example, when the control logic device 25 is controlled to conduct the conduction of the 5 lines, and the page erase is performed, the conduction of the 5 lines of the decoder 2 is performed column by line when the control logic device 25 passes through. Missing 5 筮 —empty & & ^ and Dao, s%, strong ~ 3 1 When searching for the signal to the dizi speech line decoder 20, > ft jin & 疋 's word line, this The control logic device 25 also transmits the g control signal to a high-voltage device qn 4 kw L > r to transmit the thought device 3 0 'and control the pressure device 3 〇 According to 479356, the description of the invention (7) Remove the binarization or read operation to generate the corresponding high-voltage signal (HV). In addition, since the high-voltage device 30 is also coupled to the first word-line decoder 20, the high-voltage signal generated by the high-voltage device 30 will be along a specific word-line array that is conducted by the first word-line decoder 20, and Acts on the corresponding memory unit. As described above, in order to provide a corresponding reference current, it is compared with the read current generated by the memory unit to determine the logical state of the data stored in the memory unit. A reference cell array 35 may be provided for coupling with the above-mentioned components. The reference cell array 35 is similar to the above-mentioned memory cell array 15 and has a plurality of reference cells. These reference cells are distributed along the word line and correspond to the memory cell array 15. And, for each reference unit, it can be kept in a logical state of "1π" by performing the erase procedure. In this way, when the data in the memory cell needs to be read at any time, the corresponding reference current can be generated by the reference cell (normally on cell) that keeps the data, which is used as the basis for judging the logical state of the read data. Similarly, in order to control the special reference cell row through the word line row of the reference cell array 35, a second word line decoder 40 can be provided to lightly connect with the reference cell array 35. In this way, when the control logic device 25 sends an address signal to the first word line decoder 20 and the high-voltage device 30 sends a high-voltage signal in order to perform a reading operation on a specific memory cell in the memory cell array 5 At this time, the reference cell array 35 will also generate a corresponding reference current. And by connecting to the memory cell array 5 and the reference cell separately

479356 V. Description of the invention (8) The device (not shown in the figure) can judge the data read by comparing the reading current with the size of the parameter. Gao Tianshang sets 30 Γ ^ The first-word incense thread decoder 4G and will respond to the above. The reference list 35 can be provided by the M signal (HV), available!通; χ; ϊ = data stored in the reference unit. It is respectively coupled with the high-voltage device 2 and the 0n reset; P0) 45 'high-voltage device 30 pairs of parameters; single code: 40 coupling, as a control power reset reset 45 ,; Decoder 4. Turn on 'and pass through; second to No., the high voltage signal generated by the erase program device 30 for the reference cell array 35 Please refer to the second figure, which shows the formula. Generally, when the power is turned on, the fm operation mode is gradually stabilized. At this time, for energization: the curve A rises, the supply voltage rises, and the corresponding pulse = Lu is generated, and the pulse-shaped output signal is prepared, as shown in curve B in the figure. The second word speech line decoder 40 is turned on and transported to the high-voltage device 30 and the line string 'and simultaneously inputs all words of the erasing action array 35. The information in the reference unit is maintained. The working South voltage signal 压), in order to use the circuit design provided by the present invention, the old m program has considerable advantages. First ★; = Line erasure ^ Θ

V. Description of the Invention (9) The electric reset device 45 is used to start the high-voltage device, so that the reference cell array 35 can be automatically erased as long as the power supply is input, without the need for additional manufacturing of other control signals. To manipulate the reference unit division program. In addition, the _-pulse signal generated by power-on resetting the set 45 is set to 30 with its Kai word line translation, and the erasing time is relatively short. In addition to the device information, the reference cell array ^ > and the storage time to reach the extended component life pressure state can be reduced, and although the present invention is a preferred example, the spirit of the invention and the entity of the invention, without departing from the present invention The spirit and scope of the invention are within the scope of patent application. The explanation of the month is as above, but it is not intended to limit to this embodiment. Therefore, the modifications made in should be included below

On page 12, 479356 and the year / year correction I will be able to easily understand the diagrams. Brief description By combining the following detailed descriptions with the above contents and the many advantages of this invention, the first diagram is a circuit architecture diagram. The circuit structure of the flash memory element provided by the present invention is shown; and the second figure is a voltage signal diagram showing the relationship between the power supply voltage and the output signal of the power-on reset device. Drawing number comparison table: Memory cell array 15 Control logic device 2 5 Reference cell array 3 5 Power-on reset device 4 5 Flash memory element 1 〇 First word line decoder 2 0 High voltage device 3 0 Second word line Decoder 4 0

Page 13

Claims (1)

479356 I, silver η: 丨 and year / > month from: a j I supplement I 6. Patent application scope 1 · A flash memory element with a memory cell array and a reference cell array, wherein the reference cell array can be In response to a power on reset device, when a power supply voltage is input, the power on reset device can transmit a high voltage signal to the reference cell array through a high voltage device, and perform an erasing process on all the reference cells. To maintain the data stored in the reference unit. 2. For the element in the scope of the patent application, the above flash memory element further includes a control logic device, which can perform a programmed procedure on the selected memory unit through the first word line decoder, Erase and read programs. 3. For the element in the scope of patent application item 2, wherein the first word speech decoder can turn on the selected memory unit according to the signal of the control logic device, so that the high voltage transmitted by the high voltage device Signal to operate the memory unit. 4. For the element in the third item of the patent application, the high voltage device can adjust the output voltage in response to the control logic device, and send the high voltage to the selected memory unit through the first word line decoder. Signal. 5. The component of the first item of the patent application scope further includes a second word line decoder, which is coupled between the reference cell array and the high voltage device, and can conduct the reference cell. Page 14 479356 ii 广 广 卜 ί :,; ... I _______ j-: -./-· j VI. Scope of Patent Application 'Ⅰ …… 一 ....: 6. A flash memory element with a memory cell array and Reference cell array. When the control logic reads the memory cell array according to the input address, a read current can be generated from the memory cell corresponding to the input address, and the reference cell also generates a reference current. By using a comparator to compare the read current with the reference current, the logic state of the read memory cell can be determined, which is characterized in that the reference cell array can respond to a power on reset device The erasing procedure is performed to maintain the stored data in the reference unit. When the power supply voltage is input, the power-on reset device can transmit a high-voltage signal to the reference unit array through a high-voltage device, and perform the operation on all the reference units. Erase procedure to maintain stored data in the reference unit. 7. For example, the element in the sixth item of the patent application scope further includes a second word line decoder coupled between the reference cell array, the power-on reset device, and the high-voltage device. 8. A programmable flash memory element, at least comprising: a memory cell array having a plurality of memory cells for storing input data; a high-voltage device coupled to the memory cell array and capable of responding to data signals and Address signal, and high voltage signal is transmitted to the selected memory cell; the reference cell array has a plurality of reference cells for providing reference Page 15 479356 VI. Patent application current to compare and judge the logic state of the data in the memory unit; and power-on reset device, coupled between the high-voltage device and the reference unit array, can respond to the voltage supplied by the power supply Input, and the high-voltage signal generated by the high-voltage device is used to erase the reference unit array to maintain the state of the reference unit continuously on (η 〇rma 1 1 y ο η). 9. According to the element in the scope of the patent application, the above memory cells are distributed in an array composed of word lines and bit lines. 10. If the element of the scope of patent application item 9 further includes a first word line decoder, coupled to the memory cell array, it can be connected to the memory cell line through the word line line and respond to the line. Address signal and the corresponding word line. 11. If the element in the scope of patent application item 10 includes a control logic device, it can respond to the operation signal and the address signal, and the selected memory cell is listed by the first word line decoder. To program, erase, or read. «12. If the element in the scope of patent application No. 8 includes a second word line decoder, the reference cell array can be turned on in response to the high voltage signal generated by the high voltage device. Erase procedure0 Page 16 479356 6. The scope of patent application 13. If the element of the scope of patent application No. 8 includes a comparator, it can perform the reading current obtained by the selected memory cell and the reference current obtained by the reference unit. Compare to determine the logical state of the data in the read memory unit. 14. A programmable flash memory element, including at least: a memory cell array having a plurality of memory cells distributed in an array composed of word lines and bit lines; The first word line decoder is coupled to the memory unit through the word line line, and can respond to the column address signal, and turn on the corresponding word line line. Controlling the $ series device can respond to the operation Signal and address signal, and through the first word line decoder, the selected memory cell row is programmed, erased, and read the program and the pressure device is coupled to the control The logic device and the first word speech line decoder can output a high voltage signal in response to the control logic device, and send the high voltage signal to the selected memory cell row by the second sub-line decoder; , t, a w is called Shao Ke Wu Wu, and is arranged in a music line, and corresponds to the memory cell array ί: word line decoder 丄 and the 'response through the second word line In the south pressure device, the ancient bismuth, Gu Bichu, and the reference mouth, Dingkou, Yong Pingmao, and the second word ugly complex unit in Jingtian, can be returned to the high pressure station. ° The U signal of the U should be placed on the A gate & the high voltage signal generated by the μ is referred to the early element array for wiping. Procedures; and C code reset means coupled to the high voltage between the translation device and the second language word line, means responsive to the power supply voltage of the wheel, so that the second word Page 17 479356 VI. Scope of patent application The speech decoder is turned on and the reference cell array is erased by the high voltage signal generated by the high voltage device to maintain the stored data in the reference unit. 15. If the element in the scope of patent application No. 14 includes a comparator, it can compare the read current obtained by the selected memory cell and the reference current obtained by the reference unit to determine the Read the logical state of its data in the memory unit. ❿ Page 18