TW479341B - Wire bonding method - Google Patents

Wire bonding method Download PDF

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Publication number
TW479341B
TW479341B TW90100913A TW90100913A TW479341B TW 479341 B TW479341 B TW 479341B TW 90100913 A TW90100913 A TW 90100913A TW 90100913 A TW90100913 A TW 90100913A TW 479341 B TW479341 B TW 479341B
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Taiwan
Prior art keywords
wire
bonding
circuit board
printed circuit
patent application
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TW90100913A
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Chinese (zh)
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Kai-Guang He
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United Microelectronics Corp
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A wire bonding method is disclosed, which at least comprises: providing a chip, this chip has an active surface and the corresponding back side, and having plural bonding pads located at the center of the active surface; provide a printed circuit board having plural contact points, these contact points are corresponding to these bonding pads; provide a bonding material, connect the backside of the chip with the printed circuit board; form a conductive bump on each bonding pad; bond the metal conducting wire on these contact points using bonding machine to form the first bond, and stitch the metal wire to the conductive bump on the corresponding bonding pad from the first bond formed on these contact points.

Description

經濟部智慧財產局員工消費合作社印製 479341 6 2 6 6twf. doc/Ο Ο 6 A7 ^___ 五、發明說明（I) 本發明是有關於一種打線方法，且特別是有關於一 種適用於將動態隨機存取記憶體（DRAM，Dynamic Random Access Memory)晶片直接組裝在印刷電路板上（COB，Chip on Board)的打線方法。 在腳數要求不高的積體電路產品中，常利用打線 (wire bonding)的方式，將晶片（die)上的銲墊(bonding pad)與 導線架上的導腳（lead)作電性連接。此類的產品常見的有 小型包裝（S〇P，Small Outline Package)及四排腳扁平包裝 (QFP，Quad Flat Package)。而晶片上銲墊的分布則有周圍 分布型(peripheral pad)及中央分布型(central pad)等。 就動態隨機存取記憶體晶片而言，因其所需的接腳 數少，且內部線路簡單，故可將其銲墊設計成中央分布型， 以共用部份的接線。故習知的動態隨機存取記憶體，常採 用導線接腳位於晶片上(LOC，Lead on Chip)之封裝製程。 .但其仍是將動態隨機存取記憶體晶片封裝完成後，再利用 表面黏著技術（SMT，Surface Mount Technology)將封裝完成 後的動態隨機存取記憶體晶片連接到模組印刷電路板 (module print circuit board)上。爲了能簡化製程，更有在封 膠之前，利用打線(wire bonding)直接將晶片連接到模組印 刷電路板（C〇B，Chip on Board)的技術。 依習知的方法利用打線直接將動態隨機存取記憶體 晶片連接到模組印刷電路板時，會先利用打線機打在晶片 的銲墊上形成一第打線點（first bond)，並從此第一打線點 向上延伸一段距離，然後再轉向下拉線到模組印刷電路板 3 t紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------— — — — — — — ^ · I I (請先閱讀背面之注意事項寫本頁) · 479341 6266twf.doc/006 A7 B7 i、發明說明（1) 的金手指（gold finger)後扯線（stitch)抽離。此時，因動態隨 機存取記憶體晶片的銲墊是中央分布型，故其打線的距離 會較一般周圍分布型銲墊的打線距離長，且因其拉線係先 自銲墊處上拉後再向外並同時向下打到金手指，故當其拉 線到晶片邊緣時常會因爲高度過低，而容易在晶片邊緣發 生短路的問題（short to die edge)，造成良率降低。 綜上所述，習知利用打線將動態隨機存取記憶體晶 片直接連接到模組化印刷電路板的技術的主要缺點爲其在 打線時容易在晶片邊緣發生短路，造成良率降低。 -請同時參考第1圖及第2圖，其中第1圖繪示習知 動態隨機存取記憶體模組(DRAM Module)示意圖，第2圖 係第1圖之局部區域100之放大示意圖。如第1圖所示， 模組印刷電路板(module print circuit board)104上排列有數 個動態隨機存取記憶體元件102。爲了便於說明，第2圖 .並未繪示原動態隨機存取記憶體元件102的外部封膠 (molding compound)，圖示爲動態隨機存取記憶體的晶片 108，其中，銲墊(bonding pad)106係分布於晶片108的中 央，並藉由金線(gold wire)110與晶片108兩側模組印刷電 路板104上的金手指（gold Hnger)112相連接。 請參考第3圖，其係第1圖之局部剖視圖，晶片108 具有主動表面（active surf ace) 108a和與其對應的背面108b， 於主動表面108a上並具有分布於中央的銲墊106。晶片108 係利用黏貼帶（tape)122將背面108b黏著於模組印刷電路 板104上，銲墊106上具有一個由打線機（wire bonding 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項ϋ 裝—— I寫本頁) 經濟部智慧財產局員工消費合作社印製 479341 6266twf. doc/ 006 A7 B7 五、發明說明（i) machine，圖i繪示）形成的第一打線點（first bond)116。在晶 片108與模組印刷電路板104之間，藉由打線機的金線110 將晶片1〇8之主動表面108a上的銲墊106和模組印刷電路 板104的金手指112電性連接。絕緣材料（111〇1(11112 compound)114則用以包覆晶片108、金線110、金手指112 及部份的模組印刷電路板104。如此則可將晶片108直接 組裝在模組印刷電路板1〇4(COB，Chip on Board)上。 經濟部智慧財產局員工消費合作社印製 針對上述的打線製程詳如第4圖及第5圖所示’其 中，第4圖繪示習知動態隨機存取記憶體晶片之打線第一 點示意圖，第5圖繪示習知動態隨機存取記憶體晶片之打 線第二點示意圖。請先參考第4圖，依習知的打線方法將 動態隨機存取記憶體晶片108直接連接到模組印刷電路板 104時，會先透過打線機(局部繪示）的打線頭126，藉由打 線管124內塡充的金屬材質，在晶片108主動表面l〇8a的 .銲墊106上形成一個第一打線點116。請再同時參考第5 圖，其係接續第4圖的打線動作，從銲墊106上第一打線 點116向上延伸一段距離，然後轉向下拉線到模組印刷電 路板104的金手指112，之後再扯線(stitch)抽離。此時， 因動態隨機存取記憶體晶片108的銲墊106是中央分布 型，故其打線的距離會較一般周圍分布型銲墊的打線距離 長，且因其拉線係自銲墊106處上拉後再向下打到金手指 112，故當其拉線到晶片108邊緣時常會因爲高度過低， 而容易在晶片108邊緣發生短路的問題（short to die edge)， 造成良率降低。 5 ts尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） " 479341 62 6 6twf. doc/〇〇 6 A7 ______ B7 五、發明說明（q ) --------------- (請先閱讀背面之注音？事項寫本頁) 爲g決習知的問題點，本發明提出一種打線方法， 至少包括:提供一晶片，此晶片具有一主動表面及對應之一 背面，晶片並具有複數個銲墊位於主動表面中央；提供一 印刷電路板，具有複數個接點，此些接點分別與此些銲墊 相對應;提供一接合材料，將晶片的背面與印刷電路板相連 接;於每一個銲墊上形成一導體凸塊;以及使用打線機，分 別將金屬導線先打線於此些接點上形成第一打線點（first bond)，再分別自此些接點上形成的第一打線點上將金屬導 線拉線到對應銲墊上的導體凸塊上。 經濟部智慧財產局員工消費合作社印製 本發明並提出一種半導體元件的封裝方法，本封裝 方法至少包括:提供一晶片，此晶片具有一主動表面及對應 之一背面’此晶片並具有多數個銲墊位於主動表面中央； 提供一印刷電路板，具有多數個接點，此些接點分別與銲 墊相對應;提供一接合材料，將晶片的背面與印刷電路板相 連接;於每一個銲墊上形成一導體凸塊;使用打線機，分別 將金屬導線先打線到接點上形成第一打線點，再分別自接 點上的第一打線點將金屬導線拉線到對應的銲墊上的導體 凸塊;以及提供一絕緣材料，包覆晶片、金屬導線、接點與 印刷電路板的一部份。 依照本發明的特徵，因將金屬導線先打線到印刷電 路板的接點，形成一導體凸塊（conductive bump)再從接點 將金屬導線拉線到對應的中央分布的銲墊(central pad)上， 故可避免習知因先打線到中央分布的銲墊後再向外同時向 下拉線到印刷電路板的接點時，因高度不夠而在動態隨機 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479341 6266twf.doc/006 A7 B7 五、發明說明（S) 存取§Β憶體晶片邊緣造成短路。 --------------裝 i — (請先閱讀背面之注意事項 寫本頁) 依照本發明的特徵，其在中央分布的銲墊上形成導 體凸塊的方法更包括利用打線機形成。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知動態隨機存取記憶體模組示意圖； 第2圖係第1圖之局部區域100之放大示意圖； 第3圖係第1圖之局部剖視圖； 第4圖繪示習知動態隨機存取記憶體晶片之打線第 一點示意圖； 第5圖繪示習知動態隨機存取記憶體晶片之打線第 二點示意圖； 第6圖繪示依照本發明之較佳實施例的動態隨機存 取記憶體模組示意圖； 第7圖係第6圖之局部區域200之放大示意圖； 第8圖係第6圖之局部剖視圖； 經濟部智慧財產局員工消費合作社印製 第9圖繪示依照本發明之較佳實施例的動態隨機存 取記憶體晶片之打線第一點示意圖； 第10圖繪示依照本發明之較佳實施例的動態隨丰幾 存取記憶體晶片之打線第二點示意圖。 圖式標號說明 100、200:模組印刷電路板局部區域 7 1¾尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — 479341 ^266twf.doc/006 A7 —_B7_ 五、發明說明（6 ) 102、202 :動態隨機存取記憶體元件 104、204 :模組印刷電路板（module print circuit board) 106、206 :銲墊（bonding pad) 108、208 :晶片(die) 108a、208a :主動表面（active surface) 108b、208b :背面 110 :金線(gold wire) 112 :金手指（gold finger) 114、214 :絕緣材料 116 :第一打線點(first bond) 122 :黏貼帶（tape) 124、224 :打線管（wire bonding tube) 126、226 :打線頭（wire bonding head) 210 :金屬導線(metal wire) 212 :接點（contact point) 216 :導體凸塊（conductive bump) 經濟部智慧財產局員工消費合作社印製 217:第一打線點 222 :接合材料 第一實施例 請同時參考第6圖及第7圖，其中第6圖繪示依照 本發明之較佳實施例的動態隨機存取記憶體模組（DRAM Module)示意圖，第7圖係第6圖之局部區域200之放大示 意圖。如第6圖所不，模組印刷電路板（moc}uie print circuit 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） 479341 6266twf.doc/006 A7 __B7__ 五、發明說明（1 ) board)204 i排列有數個動態隨機存取記憶體元件202。爲 了便於說明，第7圖並未繪示原動態隨機存取記憶體元件 202的外部封膠（molding compound)’圖不爲動態隨機存取 記憶體的晶片208，其中，銲墊(bonding pad)206係分布於 晶片208的中央，並藉由金屬導線210,比如爲金線(gold wire) 與晶片208兩側模組印刷電路板204上的接點212，比如 爲金手指（gold finger)相連接。 請參考第8圖，其係第6圖之局部剖視圖，晶片208 具有主動表面（active surface)208a和與其對應的背面208b ’ 於主動表面208a上並具有分布於中央的銲墊206。晶片208 係利用接合材料222,比如爲黏貼帶(tape)將背面208b黏 著於模組印刷電路板204上，銲墊206上及模組印刷電路 板204的接點212上，分別具有導體凸塊（conductive bimip)216及217，其中該導體凸塊217在此作爲模組印刷 電路板204打線到銲墊206時的第一打線點（以下也稱217 爲第一打線點）。在晶片208與模組印刷電路板204之間， 經濟部智慧財產局員工消費合作社印製 藉由打線機的金屬導線210將晶片208之主動表面208a上 的銲墊206和模組印刷電路板204上的接點212電性連接。 絕緣材料214，比如爲封膠（molding compound)則用以包覆 晶片208、金線210、接點212及部份的模組印刷電路板 204。如此則可將晶片208直接組裝在模組印刷電路板 204(C〇B，Chip on Board)上。 第9圖與第10圖係說明根據本發明之一較佳實施 例’動態隨機存取記憶體晶片的打線程序。請先參考第9 9 &^尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) "— 479341 6266twf.doc/006 A7 B7 五、發明說明（X) 圖，依照本發明之較佳實施例的打線方法將動態隨機存取 記憶體晶片208直接連接到模組印刷電路板204時’會先 在晶片208主動表面208a的銲墊206上形成一個導體凸塊 216，舉例而言，可透過打線機（局部繪示）的打線頭226， 藉由打線管224內塡充的金屬材質形成導體凸塊216,比 如爲金凸塊(gold bump)。請再同時參考第10圖，完成第9 圖之導體凸塊216之後，利用打線機的打線頭226在模組 印刷電路板204的接點212上形成一個第一打線點（first bond)217，並從接點212上的第一打線點217向上延伸一 段距離，然後轉向下拉線到銲墊206上的導體凸塊216， 之後再扯線（stitch)抽離，使晶片與印刷電路板得以電性連 接。 依照本發明之較佳實施例的半導體元件封裝方法， 如第8圖所示，完成上述打線之後，再提供一絕緣材料214， 比如爲封膠（molding compound)包覆晶片208、金屬導線 210、接點212與印刷電路板204的一部份。 依照本發明較佳實施例的打線方法，雖因動態隨機 存取記憶體晶片208的銲墊206是中央分布型，其打線的 距離會較一般周圍分布型銲墊的打線距離長，但依本發明 特徵係將習知動態隨機存取記憶體晶片直接組裝到模組印 刷電路板上的打線順序改爲，先打線到印刷電路板204上 的接點212,形成一個第一打線點217後向上延伸一段距 離後，再向下向內拉線到銲墊206上的導體凸塊216，故 其拉線路徑會先經過晶片208的邊緣向上，再延伸到銲墊 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 479341 6 2 6 6twf. Doc / Ο Ο 6 A7 ^ ___ V. Description of the Invention (I) The present invention relates to a method of wire bonding, and in particular to a method suitable for applying dynamic A wire bonding method in which a random access memory (DRAM) chip is directly assembled on a printed circuit board (COB, Chip on Board). In integrated circuit products with low pin requirements, wire bonding is often used to electrically connect the bonding pad on the die to the lead on the lead frame. . Common products of this type are Small Outline Package (S0P) and Quad Flat Package (QFP). The pads on the wafer are distributed in peripheral pads and central pads. As far as the dynamic random access memory chip is concerned, because it requires a small number of pins and its internal circuit is simple, its pads can be designed as a centrally distributed type to share some wiring. Therefore, the conventional dynamic random access memory often uses a packaging process in which a lead pin is located on a chip (LOC). However, after the package of the dynamic random access memory chip is completed, the surface-mounted technology (SMT, Surface Mount Technology) is used to connect the packaged dynamic random access memory chip to the module printed circuit board (module). print circuit board). In order to simplify the manufacturing process, the technology of directly connecting the chip to the module printed circuit board (COB) by wire bonding is used before the sealing. When a dynamic random access memory chip is directly connected to a module printed circuit board using a wire according to a conventional method, a wire bonder is first used to form a first bond on the pad of the chip, and the first bond The wire point extends upward for a distance, and then turns to the pull-down wire to the module printed circuit board. The 3 t paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ------------ — — ^ · II (Please read the notes on the back to write this page first) · 479341 6266twf.doc / 006 A7 B7 i. The gold finger of the description of the invention (1) is pulled away from the stitch. At this time, because the pads of the dynamic random access memory chip are centrally distributed, the distance of the wire will be longer than that of the general surrounding distributed pads, and because the wire is pulled up from the pad first After that, the finger is punched outward and downward at the same time. Therefore, when the wire is pulled to the edge of the chip, the height is often too low, which is prone to short-to-die edges, which reduces the yield. In summary, the main disadvantage of the conventional technique of directly bonding dynamic random access memory chips to a modular printed circuit board using wire bonding is that it is prone to short-circuits at the edge of the chip during wire bonding, resulting in a decrease in yield. -Please refer to Figure 1 and Figure 2 at the same time, where Figure 1 shows a schematic diagram of a conventional dynamic random access memory module (DRAM Module), and Figure 2 is an enlarged schematic diagram of the local area 100 of Figure 1. As shown in FIG. 1, a plurality of dynamic random access memory elements 102 are arranged on a module print circuit board 104. For the convenience of explanation, FIG. 2 does not show the external molding compound of the original dynamic random access memory device 102, and it shows the chip 108 of the dynamic random access memory. Among them, a bonding pad 106) is distributed in the center of the chip 108, and is connected to a gold finger 112 on a module printed circuit board 104 on both sides of the chip 108 by a gold wire 110. Please refer to FIG. 3, which is a partial cross-sectional view of FIG. 1. The wafer 108 has an active surface 108a and a corresponding back surface 108b on the active surface 108a and has the pads 106 distributed in the center. The chip 108 uses a tape 122 to adhere the back surface 108b to the module printed circuit board 104, and the bonding pad 106 has a wire bonding (wire bonding 4) paper standard applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back page first-I write this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 479341 6266twf. Doc / 006 A7 B7 V. Description of the invention (i) machine, picture i is shown) a first bond 116 formed. Between the wafer 108 and the module printed circuit board 104, the bonding pads 106 on the active surface 108a of the chip 108 and the gold finger 112 of the module printed circuit board 104 are electrically connected by the wire 110 of the wire bonding machine. The insulating material (111〇1 (11112 compound) 114 is used to cover the chip 108, the gold wire 110, the gold finger 112, and part of the module printed circuit board 104. In this way, the chip 108 can be directly assembled on the module printed circuit The board 104 (COB, Chip on Board) is printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The first point of the random access memory chip is wired. Figure 5 shows the second point of the conventional dynamic random access memory chip. Please refer to Figure 4 first, the dynamic random When the access memory chip 108 is directly connected to the module printed circuit board 104, it will first pass through the wire bonding head 126 of a wire bonding machine (partially shown), and the metal material filled in the wire bonding tube 124 will be used on the active surface of the chip 108. 〇8a. A first wire bonding point 116 is formed on the bonding pad 106. Please refer to FIG. 5 at the same time, which is the wiring operation following the fourth figure, and extends a distance from the first wire bonding point 116 on the bonding pad 106, and then Turn down the cable to the module printed circuit board 1 The gold finger 112 of 04 is then pulled away by the stitch. At this time, because the pads 106 of the dynamic random access memory chip 108 are centrally distributed, the distance of the wire will be longer than that of the general distributed pads. The wiring distance is long, and because the wire is pulled up from the solder pad 106 and then hit the gold finger 112 downwards, when it is pulled to the edge of the wafer 108, it is often easy to be on the edge of the wafer 108 because the height is too low. Short-to-die edge occurred, resulting in lower yield. 5 ts scale applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) " 479341 62 6 6twf. Doc / 〇〇6 A7 ______ B7 V. Description of the invention (q) --------------- (Please read the phonetic on the back? Matters to write on this page) To solve the problems known by g, the present invention proposes a method of wire bonding At least, a wafer is provided, the wafer has an active surface and a corresponding back surface, the wafer has a plurality of pads located in the center of the active surface, a printed circuit board is provided with a plurality of contacts, and these contacts are respectively These pads correspond; provide a bonding material to the back of the wafer Connected to the printed circuit board; forming a conductor bump on each pad; and using a wire bonding machine, wire the metal wire first to these contacts to form a first bond, and then from there The metal wire is drawn on the first bump formed on the contact to the conductor bump on the corresponding solder pad. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the present invention and proposes a packaging method for semiconductor components. The packaging method at least Including: providing a chip, the chip has an active surface and a corresponding one of the back surface; the chip has a plurality of solder pads located in the center of the active surface; providing a printed circuit board with a plurality of contacts, and these contacts are respectively Pads; provide a bonding material to connect the back of the wafer to the printed circuit board; form a conductor bump on each pad; use a wire bonding machine to wire the metal wires to the contacts first to form the first wire bonding points , And then pull the metal wire to the corresponding conductor pad on the corresponding solder pad from the first wiring point on the contact; and provide an insulating material to cover the chip , Metal wires, contacts and parts of a printed circuit board. According to the features of the present invention, since the metal wires are first wired to the contacts of the printed circuit board, a conductive bump is formed, and then the metal wires are drawn from the contacts to the corresponding central pads. Therefore, it is possible to avoid the fact that when the wire is first wired to the centrally distributed pads and then pulled down to the contacts of the printed circuit board at the same time, it is dynamic and random due to insufficient height. 6 This paper size applies Chinese National Standards (CNS) A4 specification (210 X 297 mm) 479341 6266twf.doc / 006 A7 B7 V. Description of the invention (S) Access to the § B memory chip edge caused a short circuit. -------------- Install i — (Please read the note on the back to write this page) According to the features of the present invention, the method for forming conductor bumps on the centrally distributed pads further includes Formed using a wire drawing machine. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 Figure 2 shows a schematic diagram of a conventional dynamic random access memory module; Figure 2 is an enlarged schematic view of the local area 100 of Figure 1; Figure 3 is a partial cross-sectional view of Figure 1; Figure 4 shows a conventional dynamic random access memory Take the first point of the memory chip wiring diagram; Figure 5 shows the second point of the conventional dynamic random access memory chip wiring diagram; Figure 6 shows the dynamic random access according to the preferred embodiment of the present invention Schematic diagram of the memory module; Figure 7 is an enlarged schematic view of the local area 200 in Figure 6; Figure 8 is a partial cross-sectional view of Figure 6; Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs; FIG. 10 is a schematic diagram showing the second point of the dynamic random access memory chip wiring according to the preferred embodiment of the present invention. FIG. 10 is a schematic diagram showing the second point of the dynamic random access memory chip wiring according to the preferred embodiment of the present invention. 100, 200: Partial area of the module printed circuit board 7 1¾ scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) — 479341 ^ 266twf.doc / 006 A7 —_B7_ V. Description of the invention ( 6) 102, 202: dynamic random access memory elements 104, 204: module print circuit board 106, 206: bonding pads 108, 208: die 108a, 208a: Active surface 108b, 208b: back surface 110: gold wire 112: gold finger 114, 214: insulating material 116: first bond 122 (tape) 124, 224: wire bonding tube 126, 226: wire bonding head 210: metal wire 212: contact point 216: conductive bump Wisdom of the Ministry of Economic Affairs Printed by the Property Cooperative's Consumer Cooperative 217: First Wire Point 222: Bonding Material For the first embodiment, please refer to Figures 6 and 7 at the same time, where Figure 6 shows the dynamic random storage according to the preferred embodiment of the present invention Take the memory module (DRAM Module) schematic diagram, the seventh The drawing is an enlarged view of a partial area 200 in FIG. 6. As shown in Figure 6, the module printed circuit board (moc) uie print circuit is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) 479341 6266twf.doc / 006 A7 __B7__ V. Description of the invention (1) board) 204 i is arranged with a plurality of dynamic random access memory elements 202. For ease of explanation, FIG. 7 does not show the external molding compound of the original dynamic random access memory device 202. The figure is not a chip 208 of the dynamic random access memory. Among them, a bonding pad 206 is distributed in the center of the chip 208, and the metal wire 210, such as a gold wire, and the contacts 212 on the module printed circuit board 204 on both sides of the chip 208, such as a gold finger connection. Please refer to FIG. 8, which is a partial cross-sectional view of FIG. 6. The wafer 208 has an active surface 208 a and a corresponding back surface 208 b ′ on the active surface 208 a and the pads 206 distributed in the center. The chip 208 uses a bonding material 222, such as a tape to adhere the back surface 208b to the module printed circuit board 204, the bonding pad 206 and the contact 212 of the module printed circuit board 204, which each have a conductor bump. (Conductive bimip) 216 and 217, where the conductive bump 217 is used as the first wiring point when the module printed circuit board 204 is wired to the bonding pad 206 (hereinafter also referred to as 217 as the first wiring point). Between the chip 208 and the module printed circuit board 204, the employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the bonding pads 206 on the active surface 208a of the chip 208 and the module printed circuit board 204 through the wire 210 of the wire bonder. The contact 212 is electrically connected. The insulating material 214, such as a molding compound, is used to cover the chip 208, the gold wire 210, the contact point 212, and a part of the module printed circuit board 204. In this way, the chip 208 can be directly assembled on the module printed circuit board 204 (COB, Chip on Board). Figures 9 and 10 illustrate the wire bonding procedure of a dynamic random access memory chip according to a preferred embodiment of the present invention. Please refer to the 9th & ^ standard for China National Standard (CNS) A4 (210 X 297 public love) " — 479341 6266twf.doc / 006 A7 B7 V. Description of the invention (X) The wire bonding method of the preferred embodiment, when directly connecting the dynamic random access memory chip 208 to the module printed circuit board 204, will first form a conductor bump 216 on the bonding pad 206 of the active surface 208a of the chip 208, for example The conductor bump 216, such as a gold bump, can be formed through a wire bonding head 226 of a wire bonding machine (partially shown) by using a metal material filled in the wire bonding tube 224. Please refer to FIG. 10 at the same time. After the conductor bump 216 of FIG. 9 is completed, the wire bonding head 226 of the wire bonding machine is used to form a first bond 217 on the contact 212 of the module printed circuit board 204. And extend a distance upward from the first bonding point 217 on the contact 212, and then turn to the pull-down line to the conductor bump 216 on the bonding pad 206, and then pull the stitch away to enable the chip and the printed circuit board to be electrically Sexual connection. According to the semiconductor device packaging method according to a preferred embodiment of the present invention, as shown in FIG. 8, after the above-mentioned bonding is completed, an insulating material 214 is provided, such as a molding compound covering the chip 208, the metal wire 210, The contacts 212 are part of the printed circuit board 204. According to the wire bonding method of the preferred embodiment of the present invention, although the bonding pads 206 of the dynamic random access memory chip 208 are centrally distributed, the bonding distance will be longer than that of the general distributed bonding pads. The invention is characterized in that the wiring sequence of the conventional dynamic random access memory chip directly assembled on the module printed circuit board is changed to wire 212 on the printed circuit board 204 first to form a first wire bonding point 217 and then upward. After extending a certain distance, the cable is pulled down inward to the conductor bump 216 on the bonding pad 206, so the path of the cable will pass through the edge of the chip 208 first and then extend to the bonding pad 10. (CNS) A4 size (210 X 297 mm)

(請先閱讀背面之注意事S •丨裝—— F寫本頁) -I線· 經濟部智慧財產局員工消費合作社印製 外/9341 Α7Β7 五、發明說明（^ ) 206上事先已形成的導體凸塊216，故可避免習知將動態 隨機存取記憶體晶片直組裝到模組印刷電路板的打線方 式’造成拉線高度過低，而容易在晶片邊緣發生短路的問 題（short to die edge) 〇 依照本發明的特徵，因將金屬導線210先打線到模 組印刷電路板204的接點212,再從接點212將金屬導線210 拉線到對應的銲墊206上，可避免習知因先打線到銲墊後 再向外向下拉線到印刷電路板的接點時，因高度不夠而在 動態隨機存取記憶體晶片邊緣造成短路。 依照本發明的特徵，其在銲墊206上形成一導體凸 塊216的方法更包括利用打線機形成。 依照本發明的特徵，本發明可應用於將中央分布型 銲墊(central pad)的晶片直接組裝到印刷電路板，尤其可應 用於將動態隨機存取記憶體的晶片208直接組裝到模組印 刷電路板204(C〇B，Chip on Board)上，避免中央分布型銲 墊的晶片利用習知打線方法於打線時在晶片邊緣發生短路 的問題。 依照上述本發明之實施例可知，本發明至少具有下 列優點： (1)依照本發明的特徵，因將金屬導線先打線到模組印刷電 路板的接點，再從接點將金屬導線拉線到對應的銲墊 上，故可避免習知因先打線到中央分布的銲墊後再向外 向下拉線到印刷電路板的接點時，因高度不夠而在動態 隨機存取記憶體晶片邊緣造成短路，以提高打線良率。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -ϋ H ϋ ϋ H ϋ n ϋ ϋ ϋ ϋ 1· I · ϋ ϋ (請先閱讀背面之注意事項寫本頁) . 經濟部智慧財產局員工消費合作社印製 479341 62 6 6twf. doc/0 〇 6 A7 B7 五、發明說明（fO) (2)依照本發明的特徵，本發明可應用於將中央分布型銲墊 (central pad)的晶片直接組裝到印刷電路板，尤其可應用 於將動態隨機存取記憶體的晶片208直接組裝到模組印 刷電路板204(COB，Chip on Board)上，避免動態隨機存 取記憶體的晶片於利用習知打線方法打線時在晶片邊緣 發生短路的問題。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項 I I - I I f) H^T. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公髮）(Please read the note on the back S • 丨 Installation-F to write this page) -I line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / 9341 Α7Β7 V. Description of the invention (^) 206 The conductor bump 216 can avoid the conventional wiring method of directly mounting the dynamic random access memory chip to the module printed circuit board, which causes the problem that the wire height is too low and it is easy to short circuit at the edge of the chip. (edge) 〇 According to the features of the present invention, because the metal wire 210 is first wired to the contact 212 of the module printed circuit board 204, and then the metal wire 210 is pulled to the corresponding solder pad 206 from the contact 212, the practice can be avoided. It is known that when the wires are first wired to the solder pads and then pulled down to the contacts of the printed circuit board, a short circuit is caused at the edge of the dynamic random access memory chip due to insufficient height. According to a feature of the present invention, the method for forming a conductor bump 216 on the bonding pad 206 further includes forming it with a wire punch. According to the features of the present invention, the present invention can be applied to directly assemble a central distributed wafer to a printed circuit board, and is particularly applicable to directly assemble a dynamic random access memory chip 208 to a module printing On the circuit board 204 (COB, Chip on Board), the problem of short-circuiting at the edge of the wafer when the wafers with the centrally distributed pads are bonded by the conventional wiring method is avoided. According to the above embodiments of the present invention, it can be known that the present invention has at least the following advantages: (1) According to the features of the present invention, the metal wires are first wired to the contacts of the module printed circuit board, and then the metal wires are drawn from the contacts to The corresponding solder pads can avoid the short circuit caused at the edge of the dynamic random access memory chip due to insufficient height when the wires are first wired to the centrally distributed pads and then pulled down to the contacts of the printed circuit board. To improve the line yield. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)-ϋ H ϋ ϋ H ϋ n ϋ ϋ ϋ 1 · I · ϋ ϋ (Please read the precautions on the back to write this page). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 479341 62 6 6twf. Doc / 0 〇6 A7 B7 V. Description of the Invention (fO) (2) According to the features of the present invention, the present invention can be applied to the use of a centrally distributed pad ( The central pad) chip is directly assembled on the printed circuit board, and is particularly applicable to the assembly of the dynamic random access memory chip 208 directly on the module printed circuit board 204 (COB, Chip on Board) to avoid dynamic random access memory. When a conventional wafer is wired using a conventional wiring method, a short circuit occurs at the edge of the wafer. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back I I-I I f) H ^ T. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (21〇 X 297)

Claims (1)

479341 A8 B8 C8 D8 ^266twf.doc/006 申請專利範圍 1 · 一種打線方法，至少包括： 提供一晶片，該晶片具有一主動表面及對應之一背 面’該晶片並具有複數個銲墊位於該主動表面中央； 提供一印刷電路板，具有複數個接點，該些接點分 別與該些銲墊相對應； 提供一接合材料，將該晶片的該背面與該印刷電路 板相連接； 於每一個該些銲墊上形成一導體凸塊;以及 使用打線機，分別將金屬導線先打線於該些接點上 形成第一打線點(first bond)，再分別自該些接點上形成的 該些第一打線點上將該些金屬導線拉線到對應的該些銲墊 上的該些導體凸塊上。 2·如申請專利範圍第1項所述之打線方法，其中該 接合材料更包括黏貼帶。 ’、 3·如申請專利範圍第1項所述之打線方法，其中於 該銲墊上形成該導體凸塊的方法更包括使用該打線機。、 ' 4·如申請專利範圍第1項所述之打線方法，其 該導體凸塊材質更包括金。 〃 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 一 5.如申請專利範圍第1項所述之打線方法，苴 該金屬導線材質更包括金線。 /、 ’ 6. —種半導體兀件的封裝方法，至少包括· 提供-晶片，該晶片具有1動表面及對應 面’該晶片並具有複數個靜墊位於該主動表面中央；同 提供-印刷電’，具賴數個㈣，該些接點分479341 A8 B8 C8 D8 ^ 266twf.doc / 006 Patent application scope 1 · A wire bonding method at least includes: providing a wafer with an active surface and a corresponding back surface 'the wafer and a plurality of pads located on the active The center of the surface; a printed circuit board is provided with a plurality of contacts corresponding to the solder pads; a bonding material is provided to connect the back surface of the wafer with the printed circuit board; A conductor bump is formed on the solder pads; and a wire bonding machine is used to wire the metal wires to the contacts to form a first bond, and then respectively form the first bonds formed on the contacts. The metal wires are drawn to the conductor bumps on the corresponding solder pads at a wiring point. 2. The wire bonding method according to item 1 of the scope of patent application, wherein the bonding material further comprises an adhesive tape. ', 3. The wire bonding method described in item 1 of the scope of patent application, wherein the method of forming the conductor bump on the pad further includes using the wire bonding machine. 4. The wire bonding method described in item 1 of the scope of patent application, wherein the material of the conductor bumps further includes gold. Printed by the Consumer Affairs Agency of the Intellectual Property Office of the Ministry of Economic Affairs. 5. According to the wiring method described in item 1 of the scope of patent application, the material of the metal wire includes gold wire. /, '6. —A method for packaging a semiconductor component, at least including: providing a wafer having a moving surface and a corresponding surface. The wafer has a plurality of static pads located in the center of the active surface; 'Relying on several puppets, these points 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） 479341 A8 B8 62 6 6twf.doc/ 0 0 6_g 六、申請專利範圍 別與該些銲墊相對應； 提供一接合材料，將該晶片的該背面與該印刷電路 板相連接； 於每一個該些銲墊上形成一導體凸塊； 使用打線機，分別將金屬導線先打線於該些接點上 形成第一打線點，再分別自該些接點上形成的該些第一打 線點上將該些金屬導線拉線到對應的該些銲墊上的該些導 體凸塊上；以及 提供一絕緣材料，包覆該晶片、該些金屬導線、該 些接點與該印刷電路板的一部份。 7. 如申請專利範圍第6項所述之封裝方法，其中該 接合材料更包括黏貼帶。 8. 如申請專利範圍第6項所述之封裝方法，其中於 該銲墊上形成該導體凸塊的方法更包括使用該打線機。 9. 如申請專利範圍第6項所述之封裝方法，其中於 該導體凸塊材質更包括金。 10. 如申請專利範圍第6項所述之封裝方法，其中 於該金屬導線材質更包括金線。 -------------II (請先閱讀背面之注意事項hSU本頁) --線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 479341 A8 B8 62 6 6twf.doc / 0 0 6_g 6. The scope of patent application corresponds to these pads; provide a bonding material Connect the back surface of the wafer with the printed circuit board; form a conductor bump on each of the pads; use a wire bonding machine to wire the metal wires to the contacts to form the first wire bonding points, The metal wires are respectively drawn from the first bonding points formed on the contacts to the conductor bumps on the corresponding pads; and an insulating material is provided to cover the chip, The metal wires, the contacts and a part of the printed circuit board. 7. The packaging method according to item 6 of the patent application scope, wherein the bonding material further comprises an adhesive tape. 8. The packaging method according to item 6 of the scope of patent application, wherein the method of forming the conductor bump on the bonding pad further comprises using the wire bonding machine. 9. The packaging method according to item 6 of the scope of patent application, wherein the conductor bump material further includes gold. 10. The packaging method as described in item 6 of the scope of patent application, wherein the material of the metal wire further includes gold wire. ------------- II (Please read the note on the back of hSU page first) --Line · Printed on the paper by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs The Chinese paper standard applies to CNS A4 size (210 X 297 mm)
TW90100913A 2001-01-16 2001-01-16 Wire bonding method TW479341B (en)

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