TW479000B - Polish pad for polishing semiconductor wafer - Google Patents

Polish pad for polishing semiconductor wafer Download PDF

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Publication number
TW479000B
TW479000B TW89103217A TW89103217A TW479000B TW 479000 B TW479000 B TW 479000B TW 89103217 A TW89103217 A TW 89103217A TW 89103217 A TW89103217 A TW 89103217A TW 479000 B TW479000 B TW 479000B
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Taiwan
Prior art keywords
polishing pad
polishing
groove
pad
grooves
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TW89103217A
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Chinese (zh)
Inventor
Shu-Jen Chen
Hung-Yu Kou
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United Microelectronics Corp
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Priority to TW89103217A priority Critical patent/TW479000B/en
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Publication of TW479000B publication Critical patent/TW479000B/en

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Abstract

This invention provides a polish pad used in a chemical mechanical polish platform for polishing semiconductor wafer. The polish pad has at least a curvy groove and a plural number of linear grooves intersecting with the curvy groove to form interlaced grooves structure on the surface of the polishing pad. The coated polish slurry on the pad is homogeneously distributed on the surface of the pad through the guidance of the interlaced grooves. The curvy groove can be a spiral groove, closed wavy circular groove or concentric circular grooves with various radii. The linear grooves can be radiated from the center of the pad, linear or curvy grooves not completely parallel with the radial direction.

Description

479000 五、發明說明(1) 發明之領域 , 本發明k供一種用於化學機械研磨(chemicai mechanical polishing)製程的研磨墊(polishing pad)。 背景說明 目刖’多重金屬化製程(multiievei metallization process)’這種利用複數層的金屬内連線層以及介電常數 較低之介電材料(dielectrics)來將半導體晶片上之各個 半導體元件彼此争接起來而完成整個堆疊化之迴路架構, 已被廣泛地應用在超大型積體電路(very large scale integration,VLSI)的製程上。然而這些金屬線及半導體 元件會使付積體電路的表面呈現高低起伏的陡峨地勢 (severe topography),增加後續在進行沉積或圖案轉移 (pattern transfer)製程時’產生突懸(〇verhang)造成孔 洞(v 〇 i d ),或者聚焦不易以及餘刻困難等缺點。所以在進 入深次微米的半導體製程之後’半導體業者大多會使用平 坦化效果較佳的化學機械研磨法來達到&導體晶^表面的 全面平坦化。 請參考圖一,圖一為一半導體晶片丨〇的結構示意圖。 半導體晶片1 0包含有一基底1 2,一金屬層i 4設於基底i 2之 上以及一介電層1 6設於基底1 2之表面並覆蓋金屬層14。請 479000 五、發明說明(2) 考圖二,圖二為一習知化學機械研磨裝置20的結構示意 圖。化學機械研磨裝置2 0包含有一研磨台22,一研磨^24 . 平鋪於研磨台2 2之上’一半導體晶片握柄28’用以將半導 體晶片1 0按壓於研磨墊2 4之上,一研磨液供應袭置3〇,用 · 以供給研磨半導體晶片1 0之研磨液,以及一調節器 , 32(condi t ioner),用來調節研磨墊24表面之研磨液的分 ·_ 佈狀況,同時清除殘留於研磨墊2 4表面之研磨碎屑。請參 考圖三與圖四,圖三為習知之研磨墊24的俯視圖,而圖四 則為圖三沿4 - 4切線方向之研磨墊2 4的剖視圖。研磨墊2 4 的表面設有三條同心圓式的溝槽2 6,研磨液則由研磨液供 應裝置30自研磨台22上方往下滴到研磨墊24的表面,並藉 _ 由溝槽2 6以及調節器3 2的導引而使研磨液能均勻分佈於研 囑 磨墊24表面。 習知在對半導體晶片1 〇進行化學機械研磨時,係先將 半導體晶片1 0安置於半導體晶片握柄2 8之放置位置,握柄 2 8抓住半導體晶片1 〇的背面,而半導體晶片i 〇的正面則壓 在鋪有研磨塾24之研磨台22之上。在進行化學機械研磨製 程時,研磨台2 2以順著逆時針方向進行旋轉,而半導體晶 片握柄2 8也以逆時針方向自轉且沿一水平方向移動,使半 導體晶片1 0之正面得到較佳的研磨效果。如圖五所示,在 ▲ π成化學機械研磨製程之後,半導體晶片1〇具有一全面平勢 坦化的表面。479000 V. Description of the invention (1) Field of the invention The present invention provides a polishing pad used in a chemical mechanical polishing process. Description of the background: "Multiievei metallization process" This method uses a plurality of metal interconnect layers and dielectrics with lower dielectric constants to compete individual semiconductor elements on a semiconductor wafer with each other. They are connected together to complete the entire stacked loop architecture, which has been widely used in the process of very large scale integration (VLSI). However, these metal lines and semiconductor elements will cause the surface of the integrated circuit to show a severe topography, which will increase the occurrence of overhangs during subsequent deposition or pattern transfer processes. Holes (v 〇id), or difficult to focus, and other shortcomings. Therefore, after entering the deep sub-micron semiconductor process, most semiconductor manufacturers will use a chemical mechanical polishing method with better planarization effect to achieve the overall planarization of the surface of the conductor crystal. Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a semiconductor wafer. The semiconductor wafer 10 includes a substrate 12, a metal layer i 4 is disposed on the substrate i 2, and a dielectric layer 16 is disposed on the surface of the substrate 12 and covers the metal layer 14. Please 479000 V. Description of the invention (2) Consider Figure 2. Figure 2 is a schematic diagram of the structure of a conventional chemical mechanical polishing device 20. The chemical mechanical polishing device 20 includes a polishing table 22 and a polishing ^ 24. A semiconductor wafer handle 28 is laid on the polishing table 22 to press the semiconductor wafer 10 on the polishing pad 24. A polishing liquid supply is set at 30, and is used to supply a polishing liquid for polishing the semiconductor wafer 10, and a regulator, 32 (conditoner), for adjusting the distribution of the polishing liquid on the surface of the polishing pad 24. At the same time, the grinding debris remaining on the surface of the polishing pad 24 is removed. Please refer to FIG. 3 and FIG. 4. FIG. 3 is a top view of the conventional polishing pad 24, and FIG. 4 is a cross-sectional view of the polishing pad 24 in FIG. The surface of the polishing pad 2 4 is provided with three concentric circular grooves 2 6. The polishing liquid is dripped from the polishing liquid supply device 30 from above the polishing table 22 to the surface of the polishing pad 24, and the groove 2 6 And the guide of the adjuster 32 allows the polishing liquid to be evenly distributed on the surface of the polishing pad 24. Conventionally, when performing chemical mechanical polishing on the semiconductor wafer 10, the semiconductor wafer 10 is first placed at the position of the semiconductor wafer handle 28, and the handle 28 holds the back of the semiconductor wafer 10, and the semiconductor wafer i The front side of 〇 is pressed on the polishing table 22 on which the polishing pad 24 is laid. During the chemical mechanical polishing process, the polishing table 22 is rotated in a counterclockwise direction, and the semiconductor wafer handle 28 is also rotated in a counterclockwise direction and moved in a horizontal direction, so that the front surface of the semiconductor wafer 10 is relatively compared. Good grinding effect. As shown in FIG. 5, after the chemical mechanical polishing process of ππ, the semiconductor wafer 10 has a fully flattened surface.

479000 五、發明說明(3) 由於研磨塾 注於半徑較小區 而被導引至半徑 調節器3 2來將研 停地移動的調節 面,以保持化學 同時清除殘留於 少研磨墊2 4的使 不但增加化學機 更換研磨墊2 4的 (throughput) ° 發明概述 2 4表面僅設有同心圓式的溝槽2 6,所以加 域的研磨液是無法光藉由同心圓式溝槽2 6 較大的區域,所以必須藉由不斷地移動的 磨液均勻地分佈於研磨墊2 4表面。然而不 器3 2以將研磨液均勻地分佈於研磨墊2 4表 機械研磨製程的研磨率(remove_rate), 研磨墊2 4表面之研磨碎屑,卻又會大幅減 用壽命。所以習知研磨墊2 4的設計結構, 械研磨程的成本,更必須付出不斷停機以 時間成本,嚴重降低半導體製程的產能 因此本發明之主要目的在提供一種用於化學機械研磨 製程的研磨墊,以解決上述的問題。 本發明係提供一種用於一化學機械研磨機台中的研磨 墊。該研磨墊包含有至少一曲線溝槽設於研磨墊表面之 上,以及複數條線形溝槽設於斫磨墊表面之上並與該曲線 溝槽相交,形成一交錯排列的網狀溝槽結構,進而使塗佈 於該研磨墊表面的研磨液得以綹由該網狀溝槽的導引而均 勻分佈於該研磨墊的表面。其中該曲線溝槽可為一螺旋狀 溝槽、封閉之波浪狀的環形迪線或為不同半徑之同心圓,479000 V. Description of the invention (3) Because the grinding is injected into the smaller radius area, it is guided to the radius adjuster 3 2 to move the adjustment surface of the ground to maintain the chemistry while removing the remaining residue on the small polishing pad 2 4 It not only increases the chemical machine to replace the polishing pad 2 4 (throughput) ° Summary of the invention 2 4 The surface is only provided with concentric grooves 2 6, so the polishing liquid of the domain cannot be used only by the concentric grooves 2 6 Large area, it must be evenly distributed on the surface of the polishing pad 24 by the continuously moving polishing liquid. However, in order to evenly distribute the polishing liquid on the polishing pad 24, the surface of the polishing pad (remove_rate) in the mechanical polishing process, the grinding debris on the surface of the polishing pad 24, will greatly reduce the life. Therefore, the design structure of the conventional polishing pad 24, the cost of the mechanical polishing process, and the continuous cost of time must be paid to seriously reduce the production capacity of the semiconductor process. Therefore, the main object of the present invention is to provide a polishing pad for a chemical mechanical polishing process. To solve the above problems. The present invention provides a polishing pad for use in a chemical mechanical polishing machine. The polishing pad includes at least one curved groove provided on the surface of the polishing pad, and a plurality of linear grooves provided on the surface of the honing pad and intersects the curved groove to form a staggered mesh groove structure. , So that the polishing liquid coated on the surface of the polishing pad can be uniformly distributed on the surface of the polishing pad by being guided by the mesh grooves. The curved groove may be a spiral groove, a closed wavy annular di wire, or concentric circles with different radii.

第6頁 479000 五、發明說明(4) 而且該線形溝槽可為一由該研磨墊之圓心向外呈放射狀,或 不完全平行於該研磨墊的徑向方向之線形或為弧形溝槽。 由於本發明之研磨墊具有一呈交錯排列的網狀溝槽, 因此加注於研磨墊表面的研磨液能經由交錯排列之網狀溝 槽的導引而均勻地分佈於研磨墊的表面,進而使半導體晶 片表面在進行化學機械研磨製程時,維持一較佳的研磨 率,ϋ使半導體晶片表面在完成化學機械研磨製程之後具 有一較佳的平坦性。此外,調節器對研磨墊的修整頻率亦 玎以大幅降低甚至不用,因此研磨墊的使用壽命也可得以 延長。 發明之詳細說明 請參考圖六,圖六為使用本發明之化學機械研磨裝置 40的結構示意圖。化學機械研磨裝置40包含有一研磨台 42,一研磨墊4 4平鋪於研磨台4 2之上,一半導體晶片握柄 48,用以將一半導體晶片46按壓於研磨墊44之上,一研磨 液供,裝置50,用以供給研磨半導體晶片46之研磨液以及 一調節器52’用來調節研磨墊44表面之研磨液的分佈狀 況’同時清除殘留於研磨墊44表面之研磨碎屑。 請參考圖七及圖八,圖七為本發明之研磨墊44的俯視 圖八為圖七沿8 - 8切線方向之研磨塾4 4的剖視圖。研 479000 五、發明說明(5) 磨墊44的表面 圓心向外呈放 研磨塾44表面 表面。 利用彳b學 械研磨時,係 之放置位置。 晶片46的正面 研磨台4 2以被 逆時針方向進 導體晶片4 6之 平坦化的表面 由於本發 並利用四條由 溝槽5 4,而在 槽。所以當研 下被加注於研 以及直線形溝 磨墊4 4的各個 用研磨液襄的 4 4之機械式的 輪廓加以磨平 設有一螺旋狀溝槽5 3以及四條 射狀分佈的直線形溝槽5 4,用 之研磨液,使研磨液均勻地分 機械研磨裝置4 0對半導體晶片 先將半導體晶片4 6安置於半導 握柄4 8抓住半導體晶片4 6的背 則被壓在鋪有研磨墊44之研磨 逆時針方向旋轉,而半導體晶 行自轉並沿一水平方向做往復 正面得以經由化學機械研磨而 由研磨墊4 4之 來導引加注於 佈於研磨墊44 4 6進行化學機 體晶片握柄48 面,而半導體 台4 2上,然後 片握柄4 8亦以 式移動,使半 形成一全面性 明之研磨墊4 4的表面設有一螺 研磨墊4 4之圓心向外呈放射狀 研磨墊44表面形成一呈交錯排 磨液由研磨液供應裝置50自研 磨墊44表面時,研磨液會經由 槽5 4導引流動,而得以均勻地 區域。所以化學機械研磨裝置 研磨微粒所產生的化學反應, 研磨來將半導體晶片46表面高 ’使研磨後的半導體晶片4 6呈 旋狀溝槽5 3, 分佈的直線形 列的網狀溝 磨台4 2上方往 螺旋狀溝槽5 3 分佈於整個研 4 〇可充分地利 配合以研磨墊 低起伏不一之 現一全面性平 479000 五、發明說明(6) 坦化的表面。 請參考圖九,圖九為本發明之第二實施例之研磨墊5 6 的俯視圖。研磨墊5 6的表面設有一螺旋狀溝槽58,以及複 數條不完全平行於研磨墊5 6徑向的直線形溝槽60,用來連 接相鄰之同心圓狀溝槽6 4,以加強導引加注於研磨墊5 6表 面之研磨液,使其均勻地分佈於研磨塾5 6表面。所以當研 磨液被加注於研磨墊5 6表面時,研磨液將經由螺旋狀溝槽 5 8以及直線形溝槽6 0導引,而得以均勻地分佈於研磨墊5 6 各個區域,以提供一均勻地化學反應以及機械式研磨來磨 平半導體晶片46表面,使得研磨後的半導體晶片46呈現全 面性平坦化的表面。 請參考圖十,圖十為本發明之第三實施例之研磨墊62 的俯視圖。研磨墊6 2的表面設有四條不同半徑之同心圓狀 溝槽6 4,以及複數條依據研磨台4 2的旋轉方向所設立之不 完全平行於研磨塾5 6徑向的弧形溝槽66。當研磨液4 6被加 注於研磨墊6 2表面之較靠近於圓心的某一圓狀溝槽6 4時, 研磨液將被孤形溝槽6 6導引至其它較外側的圓狀溝槽6 4, 使得研磨液得以均勻地分佈於研磨墊6 2的各個區域,以提 供一均勻地化學反應以及機械式研磨來磨平半導體晶片46 表面,使得研磨後的半導體晶片4 6呈現全面性平坦化的表 面0Page 6 479000 V. Description of the invention (4) Furthermore, the linear groove may be a radial or outward arc that is radially outward from the center of the polishing pad, or is not completely parallel to the radial direction of the polishing pad groove. Since the polishing pad of the present invention has a staggered network of grooves, the polishing liquid filled on the surface of the polishing pad can be evenly distributed on the surface of the polishing pad through the guidance of the staggered network of grooves, and further When the surface of the semiconductor wafer is subjected to the chemical mechanical polishing process, a better polishing rate is maintained, so that the surface of the semiconductor wafer has a better flatness after the chemical mechanical polishing process is completed. In addition, the adjustment frequency of the polishing pad by the regulator is greatly reduced or even not used, so the service life of the polishing pad can be extended. Detailed description of the invention Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of a chemical mechanical polishing device 40 using the present invention. The chemical mechanical polishing device 40 includes a polishing table 42, a polishing pad 44 is tiled on the polishing table 42, and a semiconductor wafer handle 48 for pressing a semiconductor wafer 46 on the polishing pad 44 and polishing. The liquid supply device 50 is used to supply the polishing liquid for polishing the semiconductor wafer 46 and a regulator 52 ′ to adjust the distribution of the polishing liquid on the surface of the polishing pad 44. At the same time, the polishing debris remaining on the surface of the polishing pad 44 is removed. Please refer to FIG. 7 and FIG. 8. FIG. 7 is a plan view of the polishing pad 44 of the present invention. FIG. 8 is a cross-sectional view of the polishing pad 44 taken along the line 8-8 of FIG. Research 479000 V. Description of the invention (5) Surface of grinding pad 44 The center of the circle is outward. When using 彳 b to grind, place it. The front side of the wafer 46, the polishing table 4 2 is fed in a counterclockwise direction, and the flattened surface of the conductor wafer 46 is formed in the groove by using four grooves 5 4. Therefore, when the research is performed, the mechanical contour of each of the 4 and 4 linear groove grinding pads 4 4 is polished with a polishing liquid, and a spiral groove 5 3 and four linearly distributed linear shapes are provided. The groove 5 4 is used for the polishing liquid, so that the polishing liquid is evenly divided into the mechanical polishing device 40. For the semiconductor wafer, the semiconductor wafer 4 6 is first placed on the semiconducting grip 4 8 and the back of the semiconductor wafer 4 6 is pressed on The polishing provided with the polishing pad 44 rotates counterclockwise, and the semiconductor crystal line rotates and reciprocates in a horizontal direction. The front surface can be guided by the polishing pad 4 4 through the chemical mechanical polishing and filled on the polishing pad 44 4 6 The chemical body wafer handles 48 faces, and the semiconductor stage 4 2 is then moved in a manner, so that a comprehensive polishing pad 4 4 is formed on the surface, and a spiral polishing pad 4 4 is provided at the center of the circle. A staggered row of polishing liquid is formed on the surface of the outer radial polishing pad 44 from the surface of the polishing pad 44 by the polishing liquid supply device 50, and the polishing liquid is guided to flow through the grooves 54 to form a uniform area. Therefore, the chemical reaction produced by the chemical mechanical polishing device grinds the particles, and the surface of the semiconductor wafer 46 is polished so that the polished semiconductor wafer 46 has a spiral groove 5 3, and a linear groove grinding table 4 is arranged in a straight line. 2 Spiral grooves 5 3 are distributed throughout the research. It can fully cooperate with the low fluctuations of the polishing pad. Comprehensiveness 479000 V. Description of the invention (6) The surface is frank. Please refer to FIG. 9, which is a top view of a polishing pad 5 6 according to a second embodiment of the present invention. The surface of the polishing pad 5 6 is provided with a spiral groove 58 and a plurality of linear grooves 60 that are not completely parallel to the radial direction of the polishing pad 5 6 to connect adjacent concentric circular grooves 6 4 to strengthen The polishing liquid filled on the surface of the polishing pad 56 is guided to be evenly distributed on the surface of the polishing pad 56. Therefore, when the polishing liquid is filled on the surface of the polishing pad 5 6, the polishing liquid will be guided through the spiral grooves 58 and the linear grooves 60 to be evenly distributed in each area of the polishing pad 5 6 to provide A uniform chemical reaction and mechanical polishing are used to smooth the surface of the semiconductor wafer 46, so that the polished semiconductor wafer 46 presents a comprehensive flattened surface. Please refer to FIG. 10, which is a top view of a polishing pad 62 according to a third embodiment of the present invention. The surface of the polishing pad 6 2 is provided with four concentric circular grooves 6 4 with different radii, and a plurality of arc-shaped grooves 66 which are not completely parallel to the radial direction of the polishing pad 5 6 according to the rotation direction of the polishing table 4 2. . When the polishing liquid 4 6 is filled in a circular groove 64 near the center of the surface of the polishing pad 62, the polishing liquid will be guided by the solitary groove 6 6 to other outer circular grooves. 64, so that the polishing liquid can be evenly distributed in each area of the polishing pad 62, so as to provide a uniform chemical reaction and mechanical polishing to smooth the surface of the semiconductor wafer 46, so that the polished semiconductor wafer 46 is fully flat. Surface 0

第9頁 479000 五、發明說明(7) j 相較於習 引研磨液的研 的網狀溝槽, 交錯排列之網 面,進而使得 之後能擁有較 體晶片亦有較 頻率也可以降 機械研磨程的 大幅提昇半導 以上所述 專利範圍所做 蓋範圍。 知僅於研磨墊表面形成同心圆式的溝槽 磨墊,本發明之研磨墊具有呈一呈交錯 因此加注於研磨墊表面的研磨液得以經 狀溝槽的導引,來均勻地分佈於研磨墊 半導體晶片表面的在完成化學機械研磨 好的平坦性,而且化學機械研磨製程對 佳的研磨率。此外,調節器對研磨墊的 低,因而延長研磨墊的使用壽命,減少 成本’以及停機以更換研磨墊的時間成 體製程的產能。 僅為本發明之較佳實施例,凡依本發明 之均等變化與修飾,皆應屬本發明專利 來導 排列 由該 的表 製程 半導 修整 化學 本, 申請 之涵 479000 圖式簡單說明 圖示之簡單說明 圖一為習知的半導體晶片的剖面圖。 圖二為習知化學機械研磨裝置的結構示意圖。 圖三為習知研磨塾的俯視圖。 圖四則為圖三沿4-4切線方向之研磨塾的剖視圖。 圖五為圖一之半導體晶經平坦化製程之後的剖視圖。 圖六為使用本發明之化學機械研磨裝置的結構示意 圖。 圖七為本發明之研磨墊的俯視圖。 圖八為圖七沿8 - 8切線方向之研磨墊的剖視圖。 圖九為本發明第二實施例之研磨墊的俯視圖。 圖十為本發明第三實施例之研磨墊的俯視圖。 圖示之符號說明 10 半 導 體 晶 片 12 基 底 14 金 屬 層 16 介 電 層 20 化 學 機 械 研 磨 裝 置 22 研 磨 台 24 研 磨 墊 26 溝 槽 28 握 柄 30 研 磨 液 供 應裝置 32 調 節 器 40 化 學 機 械 研 磨 裝 置 42 研 磨 台 44 研 磨 墊 46 半 導 體 晶 片Page 9 479000 V. Description of the invention (7) j Compared with the reticular grooves of Xiyin's grinding fluid, the staggered arrangement of the mesh surface enables the use of more compact wafers and more frequent mechanical reduction. The process has greatly improved the coverage of the semiconducting patent range. It is known that a concentric circular groove polishing pad is formed only on the surface of the polishing pad. The polishing pad of the present invention has a staggered pattern so that the polishing liquid added to the surface of the polishing pad can be guided by the grooves to be evenly distributed on The flatness of the surface of the polishing pad semiconductor wafer after the chemical mechanical polishing is completed, and the chemical mechanical polishing process has a good polishing rate. In addition, the regulator has a low polishing pad, thereby extending the life of the polishing pad, reducing costs, and the time it takes to shut down to change the polishing pad. It is only a preferred embodiment of the present invention. Any equivalent changes and modifications according to the present invention should belong to the patent of the present invention to guide and arrange the semi-conducted trimmed chemical book by the watchmaking process. The application is 479000. Brief Description FIG. 1 is a cross-sectional view of a conventional semiconductor wafer. FIG. 2 is a schematic structural diagram of a conventional chemical mechanical polishing device. FIG. 3 is a top view of a conventional grinding mill. Figure 4 is a sectional view of the grinding mill in Figure 3 taken along the 4-4 tangential direction. FIG. 5 is a cross-sectional view of the semiconductor crystal of FIG. 1 after the planarization process. Fig. 6 is a schematic structural view of a chemical mechanical polishing apparatus using the present invention. FIG. 7 is a top view of the polishing pad of the present invention. Fig. 8 is a sectional view of the polishing pad in Fig. 7 taken along a tangential direction of 8-8. FIG. 9 is a top view of a polishing pad according to a second embodiment of the present invention. FIG. 10 is a top view of a polishing pad according to a third embodiment of the present invention. Description of reference symbols 10 semiconductor wafer 12 base 14 metal layer 16 dielectric layer 20 chemical mechanical polishing device 22 polishing table 24 polishing pad 26 groove 28 handle 30 polishing liquid supply device 32 regulator 40 chemical mechanical polishing device 42 polishing table 44 polishing pad 46 semiconductor wafer

第11頁 479000 圖式簡單說明 48 握 柄 50 研 磨 液 供 應裝置 52 調 節 器 53 螺 旋 狀 溝 槽 54 直 線 形 溝 槽 56 研 磨 墊 58 螺 旋 狀 溝 槽 60 直 線 形 溝 槽 62 研 磨 墊 64 同 心 圓 溝 槽 66 弧 形 溝 槽Page 11 479000 Brief description of drawings 48 Handle 50 Polishing fluid supply device 52 Regulator 53 Spiral groove 54 Straight groove 56 Grinding pad 58 Spiral groove 60 Straight groove 62 Grinding pad 64 Concentric circular groove 66 curved groove

第12頁Page 12

Claims (1)

479000 六、申請專利範圍 〜S 1 · 一種研磨半導體晶片之研磨墊,該研磨墊包含有· 至少一曲線溝槽,設於研磨塾表面之上;以及 槽相 複數 交。 條 線 形 溝 槽 ? 設於研磨墊表 面之上並與該曲線溝 2. 如申 請 專 利 範 圍 第 1項之研磨墊, 其 中該曲線溝槽 為一 螺旋 狀 溝 槽 〇 3. 如申 請 專 利 範 圍 第 1項之研磨塾, 其 中該曲線溝槽 為不 同半 徑 之 同 心 圓 0 4. 如申 請 專 利 範 圍 第 1項之研磨墊, 其 中該線形溝梯 為一 由該 研 磨 墊 之 圓 心 向外呈放射狀 分布的直線形溝槽' 5. 如申 請 專 利 範 圍 第 1項之研磨墊, 其 中各該線形滏 係為 不平 行 於 該 研 磨 墊 之徑向方向的 線形溝槽。 6. 如申 請 專 利 範 圍 第 5項之研磨墊, 丨其 中該線形溝槽 係 為一 弧形 溝 槽 〇 7. 如申 請 專 利 範 圍 第 1項之研磨墊 ,其 中該研磨墊係 安 置於 一化 學 機 械 研 磨 機 台之中,該研 磨機台另包含一言 同節 器(conditioner),用來調節於研磨墊表面之研磨液的分 佈狀況,同時清除殘留於該研磨墊表面之研磨碎屑。479000 VI. Scope of patent application ~ S 1 · A polishing pad for polishing semiconductor wafers, the polishing pad including · at least one curved groove provided on the surface of the polishing pad; and the grooves intersect in plural. A linear groove is provided on the surface of the polishing pad and is connected to the curved groove. 2. The polishing pad of item 1 of the patent application scope, wherein the curved groove is a spiral groove. Item of the polishing pad, wherein the curved grooves are concentric circles with different radii. 4. For the polishing pad of item 1 in the scope of patent application, wherein the linear groove ladder is a radial distribution outward from the center of the polishing pad. Linear grooves' 5. For the polishing pad of item 1 of the patent application scope, each of the linear grooves is a linear groove not parallel to the radial direction of the polishing pad. 6. For example, the polishing pad of item 5 of the patent application, wherein the linear groove is an arc groove. 7. For the polishing pad of item 1 of the patent application, the polishing pad is disposed in a chemical machine. Among the polishing machines, the polishing machine also includes a conditioner, which is used to adjust the distribution of the polishing liquid on the surface of the polishing pad and remove the grinding debris remaining on the surface of the polishing pad. 第13頁 479000 k°yll J _i 六、申請專利範圍 8 . —種使研磨液均勻分佈於研磨墊表面的方务’該方法 包含: 於該研磨墊上形成至少一曲線溝槽;以及 於該研磨墊上複數條線形溝槽,與該曲線溴槽相交·, 其中當該研磨液被加注於該研磨墊時,經由該曲線溝 槽及該直線溝槽的導引,該研磨液將能均勻地分佈於該研 磨塾表面。 9. 如申請專利範圍第8項之方法,其中該曲線溝槽係為 一螺旋狀溝槽。 1 0.如申請專利範圍第8項之方法,其中該曲線溝禕係為 不同半徑之同心圓。 1 1.如申請專利範圍第8項之方法,其中該線形溝槽係為 一由該研磨墊之圓心向外呈放射狀分布的直線形溝糟。 1 2 ·如申請專利範圍第8項之方法,其中各該線形溝禕係 為不平行於該研磨墊之徑向方向的線形溝槽。 1 3.如申請專利範圍第1 2項之方法,其中該線形溝槽.肩 一弧形溝槽。Page 13 479000 k ° yll J _i 6. Application scope of patent 8. A method for uniformly distributing polishing liquid on the surface of the polishing pad 'The method includes: forming at least one curved groove on the polishing pad; and polishing the polishing pad A plurality of linear grooves on the pad intersect the curved bromine groove. When the polishing liquid is filled in the polishing pad, the polishing liquid will be uniformly guided by the curved grooves and the linear grooves. Distributed on the surface of the mill. 9. The method according to item 8 of the patent application, wherein the curved groove is a spiral groove. 10. The method according to item 8 of the scope of patent application, wherein the curved grooves are concentric circles with different radii. 1 1. The method according to item 8 of the scope of patent application, wherein the linear groove is a linear groove distributed radially outward from the center of the circle of the polishing pad. 1 2 · The method according to item 8 of the patent application, wherein each of the linear grooves is a linear groove not parallel to the radial direction of the polishing pad. 1 3. The method according to item 12 of the scope of patent application, wherein the linear groove. The shoulder is an arc groove. 479000 六、申請專利範圍 1 4.如申請專利範圍第8項之方法,其中該研磨墊係安置 於一化學機械研磨機台之中,該研磨機台另包含一調節器 (conditioner),用來調節於研磨墊表面之研磨液的分佈 狀況,同時清除殘留於該研磨墊表面之研磨碎屑。479000 VI. Application for patent scope 1 4. The method according to item 8 of the patent application scope, wherein the polishing pad is arranged in a chemical mechanical polishing machine, and the polishing machine further includes a conditioner for The distribution of the polishing liquid on the surface of the polishing pad is adjusted, and at the same time, the polishing debris remaining on the surface of the polishing pad is removed. 第15頁Page 15
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7357698B2 (en) 2005-05-24 2008-04-15 Hynix Semiconductor Inc. Polishing pad and chemical mechanical polishing apparatus using the same
TWI449598B (en) * 2008-12-23 2014-08-21 羅門哈斯電子材料Cmp控股公司 High-rate polishing method
US10586708B2 (en) 2017-06-14 2020-03-10 Rohm And Haas Electronic Materials Cmp Holdings, Inc. Uniform CMP polishing method
US10777418B2 (en) 2017-06-14 2020-09-15 Rohm And Haas Electronic Materials Cmp Holdings, I Biased pulse CMP groove pattern
US10861702B2 (en) 2017-06-14 2020-12-08 Rohm And Haas Electronic Materials Cmp Holdings Controlled residence CMP polishing method
US10857648B2 (en) 2017-06-14 2020-12-08 Rohm And Haas Electronic Materials Cmp Holdings Trapezoidal CMP groove pattern
US10857647B2 (en) 2017-06-14 2020-12-08 Rohm And Haas Electronic Materials Cmp Holdings High-rate CMP polishing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7357698B2 (en) 2005-05-24 2008-04-15 Hynix Semiconductor Inc. Polishing pad and chemical mechanical polishing apparatus using the same
TWI449598B (en) * 2008-12-23 2014-08-21 羅門哈斯電子材料Cmp控股公司 High-rate polishing method
US10586708B2 (en) 2017-06-14 2020-03-10 Rohm And Haas Electronic Materials Cmp Holdings, Inc. Uniform CMP polishing method
US10777418B2 (en) 2017-06-14 2020-09-15 Rohm And Haas Electronic Materials Cmp Holdings, I Biased pulse CMP groove pattern
US10861702B2 (en) 2017-06-14 2020-12-08 Rohm And Haas Electronic Materials Cmp Holdings Controlled residence CMP polishing method
US10857648B2 (en) 2017-06-14 2020-12-08 Rohm And Haas Electronic Materials Cmp Holdings Trapezoidal CMP groove pattern
US10857647B2 (en) 2017-06-14 2020-12-08 Rohm And Haas Electronic Materials Cmp Holdings High-rate CMP polishing method

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