TW478131B - Fabrication method of the contact plug of embedded memory - Google Patents

Abstract

The present invention provides a fabrication method of the contact plug of embedded memory, which comprises forming plural MOS transistors on the semiconductor chip for defining a memory array region and a periphery circuit region, forming a first dielectric layer on the memory array region, forming plural landing pads in the first dielectric layer, then forming a stop layer and a second dielectric layer on the surface of the semiconductor chip sequentially, proceeding a photo-etching process (PEP) to form plural contact plug holes in the second dielectric layer of the memory array region and the periphery circuit region, and finally filling a conductive layer in each contact plug hole to form the contact plug on each memory array region and periphery circuit region.

Description

478131

V. Description of the Invention (1) Field of the Invention The present invention provides a method for making a contact plug of an embedded memory. 0 Background description In order to avoid short circuit of various components in the embedded memory, each component and The circuits are covered with an insulating layer, and then the photo-etching-process (PEP) is used. A plurality of contact holes (c ο ntacth ο 1 e) are formed in the insulating layer. The hole is filled with a conductive layer to achieve the purpose of electrical 'interconnect ion' of each metal oxide semiconductor transistor and circuit. Refer to FIG. 1 to FIG. 8. FIG. 1 to FIG. 8 are the methods for contacting the interposer and the tape of an embedded memory on a semiconductor wafer 10, which is a conventional method. As shown in FIG. 1, a memory array region 12 and a peripheral circuit region 14 have been defined on the surface of the silicon substrate 10 of the semiconductor wafer 10, and the memory array region i 2 includes at least one cell-well. ) 18, and the peripheral circuit area 14 includes at least one N-well 20 and at least one P-well 1 (P-we 1 1) 2 2. A conventional method is to first form a plurality of gates 2 4, 2 6, 2 8 on the memory array region 12 and the peripheral circuit region 14 at the same time, and each gate 2 4, 2 6, 2 8 is provided with a gate. Side wall 30 and a lightly doped drain

Page 4 478131 V. Description of the invention (2) (lightly doped drain (LDD) 32), and a source electrode 34 and a drain electrode 36 are formed around the gate electrodes 26 and 28 respectively. 'Next, as shown in the figure, a dielectric layer 38 is formed on the surface of the semiconductor wafer 10, such as a silicon dioxide layer. Then, a yellow light process is used to define a pattern of several light metal connection regions 40 on the surface of the dielectric layer 38, as shown in FIG. Subsequently, another yellow light process is used to define the first 44, the second 42, and the third contact window 46 in the dielectric layer 38, as shown in FIG. 4. The first contact window 44 is used to connect a capacitor, and the second contact window 42 is used to connect a bit line ', that is, an via via. The third connection is a portion of the strip contact of the peripheral circuit region 14 connected to the source or the drain. The depths of the first 4 4, the second 4 2, and the third 4 6 are the same. Therefore, they are located on the same horizontal plane.

^ As shown in FIG. 5, a fourth contact window 48 is then formed in the dielectric layer 38 using a yellow light process. The fourth contact window 48 is a part for connecting the gate electrode in the contact with the peripheral circuit area 14. Because of its shallow depth, it is located at a different water from the first 4 4, the first 4 2 and the third contact window 46. And the third and fourth contact windows are respectively connected to the gate and the source or the drain of different transistors, so they are located on different vertical sections. Then, as shown in FIG. 6, a barrier layer 50 and a dielectric layer 52 are sequentially formed on the silicon substrate 16. The barrier layer 50 and the dielectric layer 52 may be respectively composed of a nitrogen nitride layer and a second oxide layer. .

Page 5 478131 V. Description of the invention (3) Subsequently, as shown in FIG. 7, a photoresist layer (not shown) is used as a mask to etch the dielectric layer 5 2 so that the dielectric layer 52 remains only at the second contact. The window 42 is in its metal connection region 40. As shown in FIG. 8, a metal layer 54 is deposited on the surface of the silicon substrate 16, and the metal layer 54 is filled in each of the contact windows 42, 44, 46, 48 and the metal connection area 40, and finally the dielectric is used again. The layer 38 is used as an etch stop layer to perform a planarization process on the metal layer 54. However, in the method disclosed in the above-mentioned conventional method for making embedded memory area interconnects, since the height difference between the memory array area and the peripheral circuit area is large, the transfer interposer and the area interconnect must be separated. Production, and the conventional manufacturing process requires at least four photomasks, which not only makes the process more complicated, complicated, but also more costly. In addition, the parts connected with the gate and the parts connected with the source or the drain in the contact with the peripheral circuit area are formed separately, and therefore occupy a large space in the unit memory. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for making a contact plug of an embedded memory to simplify the complexity of the manufacturing process and reduce the cost. The method of the present invention is to first form a plurality of MOS transistors on a semiconductor wafer defining a memory array area and a peripheral circuits area, and then form a first dielectric on the memory array area. Electrical layer and forming a plurality of transitions in the first dielectric layer

Page 6 478131 V. Description of the invention (4) H (landing pad). Subsequently, a stop layer and a second dielectric layer are sequentially carried on the surface of the semiconductor wafer, and a yellow light and 14-etching process (PEP) is performed to the second array on the memory array region and the peripheral circuit region. A plurality of contact plug holes (c ο ntact ρ 1 ugh 〇1 e > are formed in the human electrical layer. ^ Then, a conductive layer is filled in each of the contact plug holes, so as to simultaneously fill the * most column area and Each of the contact plugs is formed above the peripheral circuit area. The Λ ° memory array uses the contact plug manufacturing method of the embedded memory of the present invention. Only two photomask procedures are needed in the process. At the same time, each contact plug and the ^ $ The metal interconnect layer of the in-memory memory is completed at the same time as a yellow light and a ^ = process, which can greatly reduce the complexity and production cost of the process. Χ 'For a detailed description of the invention, please refer to Figures 9 to 2 14. Figures 9 to 24 show the method of making an embedded memory (embedded contact plug) on a semiconductor wafer 60 according to the present invention. As shown in FIG. A memory array region 6 2 has been defined on the surface of the substrate 7 2 and The peripheral circuit area 64 and the memory array area 62 include a single cell well 6 6, while the peripheral circuit area 64 includes an n-type well 68 and a P-type well 70, each of which is separated by several shallow trenches 61 In the method of the present invention, a dielectric layer 74, an undoped polycrystalline silicon layer 76, and a dielectric layer 78 are sequentially formed before the surface of the semiconductor wafer 60. Then, as shown in FIG.

478131 5. As shown in the description of the invention (5), a mask layer 80 is formed over the peripheral circuit area 64, and an N-type ion implantation process is performed on the undoped polycrystalline silicon layer 76 over the memory array area 62. In order to form the undoped polycrystalline silicon layer 76 above the memory array region 62, an N-doped polycrystalline silicon layer 82 is formed. Then, as shown in Figure Η--, a more than one etching process is performed to completely remove the dielectric layer 78 above the memory array region 62, and the doped polycrystalline silicon layer 82 is etched down to the original name until the impurity is not changed. The half of the total heterogeneity of the polycrystalline crushed layer 76 is about 1000-190 angstroms (angstrom). As shown in FIG. 12, after the mask layer 80 above the peripheral circuit area 64 is removed, it is then at the half-day sundial ...

A metal silicide layer 84 is formed to reduce the sequential formation resistance of the doped surface. The silicon nitride oxide layer 86 is used as the contact interface electrical layer of the antireflective spar layer 82 and a photoresist layer. 9 0. 9, a silicon nitride layer 8 8 as a read-only

Then, a yellow light process is performed to define a plurality of " unit cells 6 6 of the memory cell area 6 2 of the photoresist layer 90 above the pattern of the photoresist layer 90 as a hard mask. In the pattern of the intermediate electrode 91, the silicon layer 82 above the memory array region 62 is etched with the silicon nitride layer 88, the silicon oxynitride layer 86, and the metal, to the surface of the dielectric layer 74, and the silicon oxide layer 84. And the gate 9b of the doped polycrystalline MOS transistor (in, a silicon nitride layer 88, a silicon oxynitride layer 8bxSltU are formed on the memory array region 62), and a dielectric layer 7 is formed on the peripheral circuit region 64 8 surface, as shown in Figure 13. And the metal oxide layer 84 until the subsequent ion implantation process is performed as shown in FIG.

478 + 3i

Note (6) The lightly doped drain electrodes (Η 92 'of each MOS transistor in the memory array region 62 and remove the photoresist layer 90. 卩; 7 ^ 7 ^ χ, after removing the photoresist layer 90 After that, as shown in Figure 15 of the Fang Fang ... 8, 1 on the semiconductor crystal "two division = road area" and a silicon oxynitride layer (not shown) as the anti-reflective photoresist layer 94 as shown, proceed-yellow light Controlled by =: As shown in the photoresist layer 94 above the well 70 of the sixteenth type, the definitions are: Type 2 * 68 and P also ^ ⑴ 疋 I have a number of gate patterns. Then use the photoresist layer 94 The pattern is used as a hard mask to engrav the undoped polysilicon | 76 above the peripheral circuit area 64 until the dielectric layer face to form the gates 93, 95 of a plurality of MOS transistors on the peripheral circuit area 64. Next, as shown in FIG. 17, an ion implantation process is performed to form a lightly doped drain (LDD) 92 of each MOS transistor in the peripheral circuit region 64. Then, as shown in FIG. 18, the photoresist is removed. After the layer 94, a silicon nitride layer 97 is formed on the surface of the semiconductor wafer 60 and covers the surfaces of the gate electrodes 93 and 95. Then, as shown in FIG. 19, a photoresist layer (not shown) is used. (Shown) and a yellow light process to define a mask pattern to etch the nitrogen silicon layer 97 around the gate electrodes 9b 93, 95 above the peripheral circuit area 64 to form a side wall 96. Subsequently, a Ion implantation process to form the source 98 and the drain 100 of each M 0 S transistor on the peripheral circuit area 64. After forming the source of each M 0 S transistor on the peripheral circuit area 64, After the electrode 98 and the drain electrode 100, a metal layer (not shown) made of Co (Co) is formed on the surface of the semiconductor wafer 60 as shown in FIG. 20, and the metal layer is overlaid.

Page 9 478131 V. Description of the invention (7) The source electrodes 98, the drain electrodes 100 and the gate electrodes 9, 3 and 95 are covered on the peripheral circuit area 64. Subsequently, a first rapid thermal processing (RTP) process is performed at a temperature range of 40 ° to 60 ° (rc and a heating time of 10 to 50 seconds), so that each of the source electrodes 98, A self-aligned silicide layer 10 is formed on the surface of the electrode 100 and the gate electrodes 93 and 95. Then, a wet etching is used to remove the unreacted metal layer on the surface of the semiconductor wafer 60. Finally, a temperature range of 60 is performed. 0 ° C ~ 8 0 (TC and heating time of 10 ~ 50 seconds is the second fastest == processing (RTP) process to align self-alignment with co2Si in the silicide layer 102 and ... and CoS Cosi reacts to a lower resistance, wherein the cobalt (c) metal layer can also be replaced with a metal layer such as titanium (Ti), nickel (Ni), or Is (Mo). As shown in FIG. After completing the metal oxide semiconductor transistors in the embedded memory, a dielectric layer 104 is then formed over the memory array region 62, and a yellow light and etching process (pEP) is used in the dielectric layer ι04. A plurality of transfer pads 106 are formed, as shown in FIG. 22. Then, a stop layer 1 08 is formed on the surface of the semiconductor wafer 60, and a stop layer 1 is formed on the surface of the semiconductor wafer 60. Another dielectric layer 110 is formed on the surface of 〇8, as shown in FIG. 23. The etching rate of dielectric layer 110 is lower than that of stop layer 108, and after forming dielectric layer 110, another Processes such as chemical mechanical polishing (CMP) or etching back to planarize the surface of the dielectric layer 110. Subsequently, as shown in FIG. 24, a photoresist layer is formed on the surface of the semiconductor wafer 60. (Not shown), and then a yellow light and etching process (PEP) is performed to define the photoresist layer above the memory array region 62 and the peripheral circuit region 64.

Page 10 478131 I. Description of Invention (8)-A pattern of a plurality of contact plugs. Then, the mask of the photoresist layer is used to etch the dielectric layer 11 to the surface of the stop layer 108 to form a plurality of contact plug holes in the substrate 110. Subsequently, the metal conductive layer composed of each U 2 object is removed, and then the contact plug array regions are formed simultaneously on the m fish two x and the peripheral circuit region 64 by using —Yellow Light H Low King Photo — etching-process (PEP). 62. A metal interconnect layer of embedded memory is formed above layer 110. ^ The dielectric method is to make a contact plug for embedded memory. Refer to A. After the formation of the transfer pad in the hidden array area, the following: before the formation of the contact plugs in the road area and the embedded A layer, so that the process can be greatly simplified. The method of the contact plug of the memory, this contact plug, and: 2 and the peripheral circuit area can form an interconnect layer at the same time-m-based and the use of the photomask in the metal process of the embedded memory: =]: The ingenious manufacturing process can therefore reduce I and reduce production costs. Furthermore, the reliability and controllability of the manufacturing process can be reduced by the patent scope: JJJ: 2 J: Example 'where the scope of application is covered according to the present invention. # 欠 化The modification and the modification should all belong to the patent of the present invention. Page 478131 Simple illustration of the diagrams Simple illustration of the diagrams Figures 1 to 8 are schematic diagrams of the conventional method for making contact plugs of embedded memory. Figures 9 to 20 The fourth is a schematic diagram of a method for making a contact plug of an embedded memory according to the present invention. Symbols illustrated in the figure 10> 60 semiconductor wafer 12 '62 memory array area 14, 64 peripheral circuit area 16' 72 $ 夕 substrate 18 ~ 66 cells Well 20 > 68 N-type well 11 70 P-type well 30 ^ 96 side wall 24 > 26 ^ 28 '9 95 93' 95 gate 32 ^ 92 lightly doped electrode 40 metal connection region 3 [98 source 36 ^ 100 drain 38 ^ 52> 74, 78, 104, 110 dielectric layer 42 first contact window 44 second contact window 46 third contact window 48 third contact window 50 barrier layer 76 undoped polycrystalline silicon layer 8 0 mask layer 82 doped polycrystalline silicon layer 84 metal silicide layer 86 silicon oxynitride layer 88 '97 silicon nitride layer 9 (L · 94' 106 photoresist layer

Page 12 478131

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Claims (1)

478131 VI. Scope of patent application-1 · A method for making a contact plug of an embedded 6-type memory (embedded memory). The method includes the following steps: / Provide a semiconductor wafer, And a silicon array (si 1 icon substrate) surface of the semiconductor chip has a memory array area and a peripheral circuits area defined on the memory array area and the peripheral circuit area, respectively. Forming a plurality of metal oxide semiconductor (MOS) transistors, forming a first dielectric layer above the memory array region; forming a plurality of transitions in the first dielectric layer above the memory array region; (Landing pad); forming a stop layer on the surface of the semiconductor wafer; forming a second dielectric layer on the surface of the stop layer; forming a first photoresist layer on the surface of the semiconductor wafer; performing a first yellow light process to A plurality of contact plugs are defined in the memory array area and the first photoresist layer above the peripheral circuit area. Pattern; using the pattern of the first photoresist layer as a hard mask to etch the second dielectric layer up to the surface of the stop layer to form a plurality of numbers in the second dielectric layer A contact plug hole; removing a stop layer at the bottom of each contact plug hole; and filling a conductive layer in each of the contact plug holes to simultaneously store in the memory 478131 VI. Patent application scope Each contact plug is formed above the array area and the peripheral circuit area. 2. The method according to item 1 of the scope of patent application, wherein the method of forming each MOS transistor on the memory array region and the peripheral circuit region includes the following steps: sequentially forming a third dielectric on the surface of the semiconductor wafer An electrical layer, an undoped polysilicon layer, and a fourth dielectric layer; performing a first ion implantation process on the undoped polycrystalline silicon layer above the memory array region to make the memory The undoped polycrystalline silicon layer above the array region is formed as a doped polycrystalline silicon layer; a second etching process is performed to completely remove the fourth dielectric layer above the memory array region, and the doped polycrystalline silicon is etched Layer to a predetermined depth; sequentially forming a metal silicide layer, a protective layer, and a second photoresist layer on the surface of the semiconductor wafer; and performing a second yellow light process on the memory array area A plurality of gate patterns are defined in the second photoresist layer; the pattern of the second photoresist layer is used as a hard mask to etch the protective layer and the metal silicide layer above the memory array region. And the doped polycrystalline silicon layer up to the surface of the third dielectric layer, and simultaneously etching the protective layer and the metal silicide layer above the peripheral circuit area up to the surface of the fourth dielectric layer; performing a second ion cloth A planting process to form a lightly doped drain (LDD) around each of the gates in the memory array region; removing the second photoresist layer and the fourth dielectric above the peripheral circuit region 478131 6. Apply for a patent coverage layer; form a third photoresist layer on the surface of the semiconductor wafer; perform a third yellow light process to define a plurality of gates in the third photoresist layer above the peripheral circuit area Using the pattern of the third photoresist layer as a hard mask, etching the undoped polycrystalline silicon layer above the peripheral circuit area up to the surface of the third dielectric layer to form each of the peripheral circuit areas. A gate; performing a third ion implantation process to form a lightly doped drain (LDD) around each of the gates in the peripheral circuit area; removing the third photoresist layer; forming on the surface of the semiconductor wafer A silicon nitride layer; etching the silicon nitride layer on the peripheral circuit region to form a sidewall around each of the gate electrodes on the peripheral circuit region; and performing a fourth ion implantation process on the periphery A source and a drain are formed around each of the gates in the circuit area. 3. The method according to item 2 of the patent application, wherein the third dielectric layer is composed of silicon dioxide (SiO 2) and is used as a gate oxide layer of each gate. 4. The method according to item 2 of the patent application, wherein the predetermined depth is approximately half the total thickness of the undoped polycrystalline silicon layer. 5. The method of claim 2 in which the protection layer is formed by a 478131 6. The scope of the patent application is composed of a silicon nitride compound, and a silicon-oxy-nitride (SiOxN y) layer is further included between the protective layer and the metal silicide layer, which is used as an anti-reflection Anti-reflection coating (ARC). 6. If the method of claim 2 is applied, before the third photoresist layer is formed on the surface of the semiconductor wafer, a silicon oxynitride (Si 0xNy) layer may be formed on the surface of the semiconductor wafer as an anti-reflection layer. (ARC). 7. If the method of claim 6 is applied, after the third photoresist layer is removed, the oxynitride layer formed under the third photoresist layer must also be removed. 8. The method according to item 2 of the patent application, wherein after forming the source and drain of each of the MOS transistors in the peripheral circuit region, the method further includes the following steps: forming a semiconductor wafer surface A metal layer covering the source, drain, and gate surfaces on the peripheral circuit area; performing a first rapid thermal process (RTP) process; removing on the surface of the semiconductor wafer The unreacted metal layer is subjected to a second rapid thermal processing (RTP) process. 9. The method of claim 8 in which the metal layer is made of cobalt (Co), titanium (Ti), nickel (Ni), or key 47g / Amendment 6. Constituted by the scope of patent application (molybdenum, Mo). 10. The method according to item 1 of the scope of patent application, wherein each of the contact plugs of the embedded memory and the first metal interconnect layer of the embedded memory are simultaneously completed in the same yellow light and etching process ( photo-etching-process (PEP), and 1 the conductive layer is a metal layer 0 kinds 11. The method for making a contact plug of an embedded memory, the method includes the following steps: ^ contains to contains at least The metal is oxidized on the pad; a memory array area and a peripheral circuit area have been defined on the surface of the pheno substrate of the semiconductor wafer where a semiconductor wafer is provided on the process circuit area, and in the memory array area One cell-well, and the peripheral circuit area includes an N-well (N-we 1 1) and at least one P-well (P-we 1 1); a memory array area and the peripheral circuit Multiple semiconductor (M0S) transistors are respectively formed on the region; a first dielectric layer is formed above the memory array region; a plurality of transfer semiconductor wafer surfaces are formed in the first dielectric layer above the memory array region to form a stop layer A second dielectric layer is formed on the surface of the stop layer; a first photoresist layer is formed on the surface of the semiconductor wafer; a first yellow light process is used to define a plurality of numbers in the memory array region and the first photoresist layer on the periphery. Figure of a contact plug Page 18 478131 6. Application for patent scope; using the pattern of the first photoresist layer as a hard cover to etch the second dielectric layer up to the surface of the stop layer for forming in the second dielectric layer A plurality of contact plug holes; removing a stop layer at the bottom of each of the contact plug holes; forming a conductive layer on the surface of the semiconductor wafer and filling the contact plug holes; and A yellow light and etching process (PEP) is performed to form each of the contact plugs above the memory array region and the peripheral circuit region, and at the same time, a metal interconnect layer is formed on the second dielectric layer. 1 2. The method according to item 11 of the scope of patent application, wherein the method of forming each MOS transistor on the memory array region and the peripheral circuit region includes the following steps: sequentially forming on the surface of the semiconductor wafer A third dielectric layer, an undoped polycrystalline silicon layer, and a fourth dielectric layer; performing a first ion implantation process on the undoped polycrystalline silicon layer above the memory array region to make the memory array region above Forming the undoped polycrystalline silicon layer into a doped polycrystalline silicon layer; performing a second etching process to completely remove the fourth dielectric layer above the memory array region, and etching the doped polycrystalline silicon layer to a predetermined depth; A metal silicide layer, a protective layer, and a second photoresist layer are sequentially formed on the surface of the semiconductor wafer; a second yellow light process is performed on the semiconductor cell well above the cell well in the memory array region. Page 19 478131 VI. Application scope Patent pattern of the plurality of gates is defined in the second photoresist layer; the pattern of the second photoresist layer is used as a hard cover to etch the protection above the memory array area Layer, the metal silicide layer, and the doped polycrystalline silicon layer up to the surface of the third dielectric layer, and simultaneously etch the protective layer and the metal oxide layer above the peripheral circuit area until the fourth dielectric layer Surface; removing the second photoresist layer; performing a second ion implantation process to form a lightly doped drain (LDD) around each of the gates in the memory array region; removing the upper part of the peripheral circuit region The fourth dielectric layer; forming a third photoresist layer on the surface of the semiconductor wafer; performing a third yellow light process to the third photoresist layer above the N-type well in the peripheral circuit region and the P-type well A pattern of a plurality of gates is defined; using the pattern of the third photoresist layer as a hard mask, the undoped polycrystalline silicon layer above the peripheral circuit area is etched up to the surface of the third dielectric layer, so that Formed on the peripheral circuit area Each of the gates; removing the third photoresist layer; performing a third ion implantation process to form a lightly doped drain (LDD) around each of the gates in the peripheral circuit region; on the semiconductor wafer Forming a silicon nitride layer on the surface; etching the silicon nitride layer on the peripheral circuit area to form a side wall around each of the gate electrodes on the peripheral circuit area; and performing a fourth and fifth ion implantation process To form a source around each of the gates above the P-type well and the N-type well in the peripheral circuit area, respectively 6. Scope of patent application Extreme and drain. 13. The method according to item 12 of the scope of patent application, wherein the second dielectric layer is composed of silicon dioxide (Si02) and is used as a gate oxide layer of each gate. 14. The method according to item 12 of the scope of patent application, wherein the predetermined depth is approximately half of the total thickness of the undoped polycrystalline silicon layer. 15. The method according to item 12 of the scope of patent application: wherein the protective layer is composed of a silicon nitride compound, and a silicon oxynitride (SiOxN y) is further included between the protective layer and the metal silicide layer. ) Layer is used as an anti-reflection layer (ARC). 16. The method according to item 12 of the scope of patent application, wherein before the third photoresist layer is formed on the surface of the semiconductor wafer, a silicon oxynitride (Si OxNy) layer may be formed on the surface of the semiconductor wafer as a resist Reflective layer (ARC). 17. The method according to item 16 of the scope of patent application, wherein after the third photoresist layer is removed, the oxynitride layer formed under the third photoresist layer must also be removed. 1 8. The method according to item 12 of the scope of the patent application, wherein the fourth and fifth ion implantation processes will respectively place the gates above the P-type well and the N-type well. 478131 6. Scope of patent application The undoped polycrystalline silicon layer in the electrode is doped. 19. The method according to item 12 of the scope of patent application, wherein after forming the source and drain of each of the MOS transistors in the peripheral circuit area, the method further includes the following steps: on the surface of the semiconductor wafer Forming a metal layer, and the metal layer covers each of the source, drain, and gate surfaces on the peripheral circuit area; performing a first rapid thermal processing (RTP) process; Removing the unreacted metal layer on the surface of the semiconductor wafer; and performing a second rapid thermal processing (RTP) process. 20. The method according to item 19 of the application, wherein the metal layer is composed of cobalt (Co), titanium (Ti), nickel (Ni), or molybdenum (Mo). Page 22