TW478125B - Semiconductor device having bump electrode - Google Patents

Abstract

A semiconductor device having bump electrode is disclosed, which comprises a copper contact pad disposed on a substrate, the copper contact pad having at least a portion exposed from the dielectric layer on the substrate. The copper contact pad has an under bump metal (UBM) which comprises a titanium layer disposed on the portion of copper contact pad exposed from the dielectric layer. A nichel/vandanium layer disposed on the titanium layer, and a copper layer is disposed on the nichel/vandanium layer. A metal bump is disposed on the under bump metal to form the bump electrode. The characteristic of the present invention is that the Nichel/Vandanium layer is used as the barrier layer of the under bump metal to greatly reduce the required thickness of the titanium layer, whereby the cost is reduced and the reliability is enhanced.

Description

478125

[Field of the Invention] The present invention relates to electronic packaging technology, and more particularly to a metal bump structure for mounting a chip with copper contact pads to an interconnection substrate. [Previous technology] a «With chip miniaturization, copper circuits have unparalleled advantages of traditional aluminum circuits. Copper wire conducts forty percent less resistance than aluminum. For copper-based microprocessors, this means a 15% speed increase. In addition, copper lines are far less susceptible to electromigration damage than aluminum lines; electromigration refers to the high current density that causes $ atoms to move in the line and cause voids, which ultimately leads to the interruption of the line. 疋'The visibility of copper lines can be compressed from the current micron to 0.2 micron. This is difficult to achieve with the Ming circuit, because when the circuit is designed to be very small, the conventional aluminum alloy cannot conduct current well, and surely it can tolerate a higher current density (which is required to accelerate circuit conversion). Copper pad wafers will gradually replace wafers using traditional aluminum circuits. In addition, as the demand for lighter and more complex electronic devices becomes more and more intense, the speed and complexity of the chip are relatively more and more south, so higher packaging efficiency is required. Miniaturization is the main driving force behind the use of advanced packaging technologies such as chip scale packages and f 1 ip ch ip. Compared to ball grid array packages or thin smaii outline packages (TS 0 P), both chip size packaging and flip chip technologies significantly increase packaging efficiency, thereby reducing the required substrate space. general

P00-106.ptd Page 4 478125 V. Description of the invention (2) A wafer-size package is approximately 20% larger than the wafer itself, and flip chip is described as the ultimate packaging technology because it is about the same as the wafer It's as big as itself. The wafer itself is directly bonded to a substrate by using a bump electrode fixed on the wafer. The conventional flip chip implantation technology can be divided into two parts, namely the under bump metallurgy (UBM) and the metal bump body. Sub-bump metallurgy usually includes three layers of metal. They are: (a) Adhesion layers such as A1 and Cr. The main purpose is to provide aluminum pads (A 1 pads) and passivation layers. Adhesiveness; (b) barrier layer, such as

NiV and TiW, which are used to prevent the metal pads and metal bumps on the wafer from reacting with each other to produce an intermetallic compound (which may cause the wafer to lose its reliability); and (C) a wetting layer ( wetting layer), such as Ni, Cu, Μο, Pt, etc. Basically, wetting of these metals with solder is relatively high, and solder can be completely attached to form a ball during high-temperature reflow. Metal bumps have high temperature tin, low temperature tin alloy, gold, nickel, copper, etc. according to different needs. The first figure shows a conventional semiconductor device with bump electrodes. It is disclosed that an aluminum contact pad 110 is disposed on a semiconductor substrate 120. A protective layer 130 (which acts as an insulating layer) covers the entire surface of the substrate 120. The cover layer 130 is provided with a cover opening at a specific position to expose the aluminum pad 110. The semiconductor element under bump metallurgy 140 includes three layers of metal, respectively: (a) an aluminum layer u0a as an adhesion layer, (b) a nickel / vanadium layer 140b as a barrier layer; and (c) ) Copper layer 14Od as a wetting layer. Page 5 478125

However, the under bump metallurgy 140 cannot be applied to a copper pad wafer because the adhesion of the aluminum layer to the copper pad is extremely poor. Therefore, the industry has developed a semiconductor device 200 as shown in the second figure, and the metallurgical under the bump 240 includes two layers of metal, namely, (a) a titanium layer 24 0 a, and at the same time serves as an adhesion layer and a barrier layer; and (b) The copper layer 24 0 b 'serves as a wetting layer. Although the adhesion of the titanium layer to the copper pad 2 10 and the protective layer 130 is excellent, the thickness of the titanium layer generally needs to be as high as 400 angstroms to exert a good barrier effect. However, due to the high cost of titanium, it will make the Its thickness is limited, causing reliability issues. In addition, because titanium is very difficult to etch away, when the semiconductor device 2000 process includes an etching step, the required process time will increase rapidly with the thickness of the titanium layer. 'Therefore, it is necessary to find a sub-bump metallurgy that can effectively solve the aforementioned problems of the prior art, and apply it to copper pad wafers. [Summary of the Invention] The main object of the present invention is to provide a metallurgical (UBM) applied to a copper pad wafer, which includes a titanium layer, a nickel / starved layer, and a copper layer. Barrier layer and greatly reduce the required thickness of the titanium layer, thereby reducing costs and increasing reliability.

To achieve the above object, the present invention provides a semiconductor device having a bump electrode, which includes a copper pad disposed on a substrate, and the copper pad is at least partially exposed on a dielectric provided on the substrate. Floor. The steel pad is provided with a metallurgical layer under the bump including a titanium layer, which is provided on the copper pad and is exposed on the dielectric layer; a nickel / starved layer is provided on the thin layer; and a steel layer is provided on the nickel. / Vanadium layer. A metal bump is disposed under the bump of the copper pad

478125 V. Description of the invention (4) The a-hai bump electrode is formed on gold. Therefore, the semiconductor element of the present invention can be directly bonded to the connection substrate using the bump electrode. According to Ben Sheming ’s Bump Metallurgy ', it is characterized in that the thickness of the titanium layer (preferably about 1000 to 2000 Angstroms) is greatly reduced by using the R / K layer as a barrier layer, thereby reducing costs and Increase reliability. The present invention further provides a method for manufacturing a metal bump pad, which includes: (a) providing a substrate on which a copper contact pad is provided; the copper pad has at least Partially exposed on the dielectric layer provided on the substrate; (b) forming a titanium layer on the copper pad and exposed on the dielectric layer; (c) forming a nickel-vanadium layer on the substrate On a titanium layer; and (d) forming a copper layer on the nickel / starved layer to make the metal bump pad. In order to make the above and other objects, features, and advantages of the present invention more apparent, the preferred embodiments of the present invention are given below, and in conjunction with the accompanying drawings, a detailed description is as follows. Then: ’[Explanation of the invention] ~~ Please refer to the third figure, which reveals that a semiconductor device includes a substrate 3, a copper connection 320, and a dielectric layer (such as a protective layer 33). The substrate 31 () may include a layer of semiconductor material (such as silicon, gallium arsenide, silicon carbide, diamond, or other substrate materials well known in the industry). The protective layer 3 3 may be a polyimide layer, a polyimide layer, a silicon dioxide layer, a silicon nitride layer, or a protective layer material known in the industry. As shown in the figure, the cover layer 乂 is covered to the top edge of the copper pad 32, leaving only the middle surface portion exposed on the cover layer 3 3.

478125 V. Description of the invention (5) The third picture of the May tea photo 'The metallurgical under bump (υβ M) 3 4 〇 according to the present invention includes a thin layer 3 4 0 a' is provided on the copper pad 3 2 〇 A portion exposed on the protective layer 3 3 0; a recording / starving layer 340b provided on the titanium layer 34a; and a copper layer 340c provided on the nickel / starving layer 3 4 0b. The under bump metallurgy (υβ M) 3 4 0 according to the present invention selects the convergence layer 340 as the adhesion layer, because it has excellent adhesion to the copper pad 32 0 and the protective layer 3 3 0. In addition, the under-bump metallurgy 340 selects the nickel / vanadium layer 340b as a barrier layer to greatly reduce the required thickness of the titanium layer 340, thereby reducing costs and increasing reliability. Preferably, the thickness of the titanium layer 340a is between about 1000 and about 2000 angstroms, and the thickness of the nickel / vanadium layer is between about 275 and about 3750 angstroms. The thickness of the copper layer is between about 72,000 and about 88000 angstroms. The fourth figure shows a bump electrode half-body element 300 ′ including a solder bump 350 provided on the copper pad 3 20 according to a preferred embodiment of the present invention. 40 to form a bump electrode. Therefore, the semiconductor element of the present invention can be directly bonded to the connection substrate using the bump electrode. The metal bump 350 according to the present invention can be soldered into, for example, (a) a high-temperature tin-lead alloy such as 5Sn / 95Pb or 3Sn / 97Pb ^ \, (b) a low-temperature tin-lead ball such as 63Sn / 37Pb or 40Sn / 60Pb . The method of planting the ball includes methods such as steaming money, electroplating, and printing. The fifth figure discloses a bump electrode _ semiconductor device 400 according to another preferred embodiment of the present invention, which includes a gold A bump 360 is provided on the copper metallurgy 340 under the bump of the copper pad 320 to form a bump electrode. Generally speaking, the gold bump 3 6 0-generally contains at least ninety percent by weight of gold, is deposited under the bump by electroplating or evaporative lift-off.

P00-106.ptd Page 8 478125 V. Description of the invention (6) 340. The under-bump metallurgy (UBM) 3 4 0 according to the present invention may be formed using an additive process, which selectively deposits the layers of metal under the bump metallurgy 3 4 0 on the copper pad 32 0. . The additive process is conventional and generally includes a lift-off technique and uses a shadow mask.

In addition, the semiconductor element having a bump electrode according to the present invention can also be formed using a subtractive process, which generally includes (a) metallizing under bump 340 (including a titanium layer 340a, a nickel / hungry layer 340b, and Copper layer 340c) sputter deposition on the protective layer 330 and the copper pad exposed on the protective layer 330; (b) coating photoresist and forming patterning; (c) eiectrodeposition solder (Or gold) in the opening area of the photoresist layer; (d) using solder (or gold) as a mask to etch the metallurgy under the bump. Finally, if solder is used as the metal bump component ', a reflow step must be performed. Since the under bump metallurgy of the present invention uses a nickel / starved layer as a barrier layer to greatly reduce the required thickness of the titanium layer, the time required for the etching step (d) can be reduced by k steps. It can be understood that the semiconductor element with a bump electrode according to the present invention can also be formed by a process described later, which includes (a) sputter deposition of each layer of metal under the bump metal layer 340 on the protective layer 33 and the copper pad. Exposed on the part of the protective layer 3 3 0; (b) selectively etching the metal layer under the bump 34 o so that only the copper pad π and the nearby protective layer 33 o have a metal layer under the bump (see the third (Figure); (c) printed solder on the copper pad 32o and the metal layer 34o under the bump 330 on the nearby protective layer 330; and reflow soldering. 478125 V. Description of the invention (7) Although the present invention has been disclosed with the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. Changes and modifications. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. _

P00-106.ptd Page 10 478125 Brief description of the drawings [Illustration] Figure 1: Sectional view of a conventional semiconductor device with a bump electrode; Semi-conductor Figure 2: Another conventional semiconductor with a bump electrode Sectional view of the device FIG. 3: reveals the metallurgical shape of a semiconductor element under a bump according to a preferred embodiment of the present invention; FIG. 4: a half electrode body having a bump according to a preferred embodiment of the present invention A cross-sectional view of the element; and FIG. 5 is a cross-sectional view of a conductor element having a bump electrode according to another preferred embodiment of the present invention. [Illustration of the drawing number] 100 semiconductor element 110 inscribed 120 substrate 130 protective layer 140 under bump metallurgy 140a aluminum layer 140b nickel / starved 140d copper layer 200 semiconductor element 210 copper pad 24 0a titanium layer 240b copper layer 300 semiconductor element 310 substrate 320 copper pad 330 protective layer 340 under bump metallurgy 340a titanium layer 34 0b nickel / vanadium layer 340c copper layer 350 metal bump 3 6 0 gold bump 400 semiconductor element

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Claims (1)

478125 VI. Application Patent Scope 1. A method for manufacturing metal bump pads, which includes: providing a substrate on which a copper contact pad is provided; the copper pad At least partially exposed on the dielectric layer provided on the substrate; forming a titanium layer on the copper pad and exposing the dielectric layer; forming a nickel-vanadium layer on the titanium layer; and A copper layer is formed on the recording / hunting layer to obtain the metal bump pad. 2. The method for manufacturing a metal bump pad according to item 1 of the scope of patent application, wherein the thickness of the titanium layer is between about 100 and about 2000 angstroms. 3. The method for manufacturing a metal bump pad according to item 2 of the scope of the patent application, wherein the thickness of the nickel / vanadium layer is between about 2750 and about 3750, and the thickness of the copper layer is between About 7 2 0 0 to about 8 8 0 0 Angstroms. 4. The method for manufacturing a metal bump pad according to item 1 of the scope of the patent application, wherein the dielectric layer is a passivation layer. 5. A semiconductor element having a bump electrode, comprising: a substrate having a dielectric layer disposed thereon; a copper pad disposed on the substrate, wherein the copper pad is at least partially exposed to the dielectric A titanium layer provided on the copper pad and exposed on the dielectric layer; P00-106.ptd Page 12 478125 6. Application scope: A recording / starving layer is provided on the titanium layer; a copper layer is positioned on the nickel / starving layer; and a metal bump is positioned on the copper layer . 6. The semiconductor device having a bump electrode according to item 5 of the scope of the patent application, wherein the thickness of the titanium layer is between about 100 and about 2000 angstroms. 7. According to the semiconductor device with a bump electrode according to item 6 of the scope of the patent application, wherein the thickness of the nickel / vanadium layer is between about 2750 and about 3750, and the thickness of the copper layer is between Between about 7 2 0 0 and about 8 8 0 0 Angstroms. 8. The semiconductor device having a bump electrode according to item 5 of the patent application, wherein the dielectric layer is a passivation layer. 9. The semiconductor element having a bump electrode according to item 5 of the scope of patent application, wherein the metal bump is a gold bump. @ 1 0. The semiconductor device having a bump electrode according to item 5 of the scope of patent application, wherein the metal bump is a solder bump. P00-106.ptd Page 13