TW477049B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- TW477049B TW477049B TW089113278A TW89113278A TW477049B TW 477049 B TW477049 B TW 477049B TW 089113278 A TW089113278 A TW 089113278A TW 89113278 A TW89113278 A TW 89113278A TW 477049 B TW477049 B TW 477049B
- Authority
- TW
- Taiwan
- Prior art keywords
- wiring substrate
- aforementioned
- ground
- terminal
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
477049 五 發明說明（1) 【發明所屬之技術領域 本發明係關於一種在配線其 件，而在其相反面上形成有 =面上搭载有半導體元 導體裝置，且關於-種適化^以作為外部端子的半 裝置。 P化及小型化構造的半導體 【習知之技術】 圖7係顯示習知之半導雕壯里 導體裝置巾，係利用覆’晶月且接衣人術截面圖。在此習知之半 過銲錫凸塊（bumP)3而搭載有口半導雕己線^板1之一面上透 線美柘1G而μ r丄戰有牛¥肢凡件2，且電連接在配 、炎巷板1之相反面上形成撼姑Υ从 丄，, 风樹狀以作為外部端子的錫球4。在 如此的半導體裝置中，因半導f 十々 口干命版兀件越來越高集成化而帶 來夕腳化，就有必要隨著多腳化而增加錫球4之數目。 【發明所欲解決之問題】 在如上述之習知半導體裝置中，為了增加錫球4之數 目，就有必要加大配線基板1或縮小錫球4之間距 (Pi tch)，因此有不適於高密度安裝或安裝困難的問題。 本發明係為了解決如此的問題點而成者，本發明之目的 在於提供一種無須加大配線基板或縮小錫球之間距而適於 高密度安裝的半導體裝置。 【解決問題之手段】 第一發明之半導體裝置，其係在配線基板之一面上利用 覆晶術接合半導體元件，同時在前述配線基板之相反面上 形成柵狀的錫球’其特徵為··在前述配線基板之端部上’ 形成用以進行電連接的平坦端子。477049 Description of the five inventions (1) [Technical field to which the invention belongs] The present invention relates to a wiring element, and a semiconductor element conductor device is mounted on the opposite surface of the wiring element, and the invention is adapted as- Half device for external terminals. Semiconductor with P-shaped and miniaturized structure [Known Technology] Fig. 7 is a cross-sectional view showing a conventional semiconductor device, a conductive device towel, which is covered with a crystal moon and is connected to a garment. The conventional one is a solder bump (bumP) 3 and is equipped with a mouth semi-conductive engraved wire ^ one surface of the board 1 is transparent through 1G, and the μr is equipped with a cow ¥ limb 2 and is electrically connected to On the opposite side of the board, Yan Lane Board 1 is formed a tinker ball 4 which is shaped like a wind tree as an external terminal. In such a semiconductor device, due to the increasingly high integration of the semi-conducting f-defective interface device, it is necessary to increase the number of solder balls 4 as the number of pins increases. [Problems to be Solved by the Invention] In the conventional semiconductor device as described above, in order to increase the number of solder balls 4, it is necessary to increase the wiring substrate 1 or to reduce the distance between the solder balls 4 (Pi tch). High density installation or difficult installation problems. The present invention has been made in order to solve such problems, and an object of the present invention is to provide a semiconductor device suitable for high-density mounting without increasing the wiring substrate or reducing the distance between solder balls. [Means for solving the problem] The semiconductor device of the first invention is characterized in that semiconductor elements are bonded by flip chip on one surface of a wiring substrate, and grid-shaped solder balls are formed on the opposite surface of the wiring substrate. A flat terminal for electrical connection is formed on an end portion of the aforementioned wiring substrate.
89113278.ptd 第4頁 五、發明說明（2) 又，第二發 利用覆晶術接 面上形成栅狀 平面及接地平 更且，第三 上利用覆晶術 反面上形成柵 面上形成電源 又，第四發 係形成環狀。 更且，第五 上利用覆晶術 反面上形成柵 板表面之接地 地端子上連接 地電位。 又，第六發 利用覆晶術接 面上形成柵狀 基板表面之電 表面之電源端 述配線基板表 線基板表面之 【發明之實施 明之半導體骏 合半導體元件 的錫球，其特 面露出。 發明之半導體 接合半導體元 狀的锡球，甘 端子及接地端 明之半導體裝 發明之半導體 接合半導體元 狀的錫球，其 平面、或形成 有散熱器，俾 明之半導體裝 合半導體元件 的錫球，其特 源平面及接地 子及接地端子 面之電源平面 電源端子及接 形態】 置’其係在配線基板之一面上 &同時在前述配線基板之相反 心支為··使前述配線基板之電源 裝复 件， 特德: 子。 置， 裝薏 件， 特徵 於前 在前 ’其係在配線基板之一面 同時在前述配線基板之相 為：在前述配線基板之表 其中電源端子及接地端子 其係在配線基板之《 面 同時在前述配線基板之相 為：在露出於前述配線基 述配線基板表面之環狀接 述半導體元件背面施加接 置:，係在配線基板之一面上 同時在前述配線基板之相反 ^為·為俾於露出於前述配線 ”面、或形成於前述配線基板 之電連接作業，而在露出於前 及接地平面、或形成於前述配 地端子上安裝有引線端子。89113278.ptd Page 4 V. Description of the invention (2) In the second round, a grid-like plane and a ground plane are formed on the flip chip junction surface, and on the third side, a power supply is formed on the grid surface on the reverse side of the flip chip technique In addition, the fourth hair line formed a ring shape. Furthermore, the fifth ground is connected to the ground potential by using flip chip technology to form a ground ground terminal on the surface of the grid. In the sixth issue, the power supply terminal of the electrical surface on the surface of the grid-like substrate formed by the flip-chip interface is described in [Exemplary Invention of the Invention] The solder ball of the semiconductor substrate of the semiconductor substrate is exposed. Invented semiconductor-bonded semiconductor element-shaped solder balls, semiconductor terminals with ground terminals and bright grounded semiconductor devices Invented semiconductor-bonded semiconductor element-shaped solder balls, on a flat surface or formed with a heat sink, and Ming-ming semiconductor-mounted solder balls for semiconductor components, Its special source plane, grounding sub, and ground terminal plane. Power plane power terminal and connection mode] It is placed on one side of the wiring substrate & at the same time the opposite center of the aforementioned wiring substrate is to make the power supply of the aforementioned wiring substrate Pack it up, Ted: Son. The installation and installation feature is characterized by the front and the front. It is on one side of the wiring substrate and is on the wiring substrate. In the table of the wiring board, the power terminal and the ground terminal are on the side of the wiring substrate. The phase of the wiring substrate is: applying contact on the back surface of the ring-shaped semiconductor element exposed on the wiring substrate and the wiring substrate: on one side of the wiring substrate and at the same time on the opposite side of the wiring substrate. For the electrical connection work exposed on the "wiring" surface, or formed on the wiring board, lead terminals are mounted on the front and ground planes, or formed on the ground terminal.
89113278.ptd 第5頁 五、發明說明（3) 實施形^使用圖1至圖6就本發明之實施形態加以說明。 圖1係顯示本發明每价^〜 參照圖1，1為配吃V广1之半導體裝置的立體圖。 基板1之—面上透過鮮基錫板^2為利用覆晶接合術在此配線 載面la上的半導r亓杜錫凸塊3而搭載丽述配線基板1之搭 形成柵狀以作為夕:部不4為在前述配線基板1之相反面上 導體元件2之搭載面。而子的錫球。而5為形成於搭載有半 在上述構成中Λ 端部上的平坦端子(鲜塾）。 上透過銲錫凸塊3二在配古線基板1之半導體元件搭载面i a 形成於半導體元 ^妾^ +導體元件2，並分開電連接在 載面1r相反面m之平坦端子5及半導體元件搭 接作業，係利用2球4上。至此平坦端子5之外部的電連 如以上說明妒連f裔或繞線等直接進行者。 如上述般藉由:L ϊ依據本實施形態1之半導體裝置，則 形成平坦端子5 , ° ^有半導體元件2之搭載面1 a的端部上 之間距。而且，〜則'又有必要加大配線基板1或縮小錫球4 端子5進行電連错由利用打線接合（wire bonding)對平坦 以可實現一種可’由於可更加縮小平坦端子5之間距，所 1，且可對應多腳/、錫球4之數目並更加縮小配線基板 實施形熊^ _化的半導體裝置。 圖2係顯示太 在圖2中，&明實施形態2之半導體裝置的截面圖。 成於配線基板丨内配線基板’ 2為半導體元件，6a〜W為形 内的配線層，6a為用以連接銲錫凸塊3、錫89113278.ptd Page 5 V. Description of the Invention (3) Embodiment ^ An embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 is a perspective view of a semiconductor device according to the present invention. Referring to FIG. On the surface of the substrate 1, a fresh-based tin plate ^ 2 is used to form a grid shape of the semiconductor substrate 1 on the wiring carrier surface la using the flip-chip bonding technique to form a grid shape as follows: The part 4 is a mounting surface of the conductor element 2 on the opposite surface of the aforementioned wiring substrate 1. And the child's tin ball. In addition, 5 is a flat terminal (fresh) formed on the end of Λ mounted in the above structure. The semiconductor element mounting surface ia with the old wire substrate 1 is formed on the semiconductor element ^ 妾 ^ + conductor element 2 through solder bumps 3, and the flat terminal 5 and the semiconductor element are electrically connected to the opposite side m of the carrier surface 1r. To pick up the work, use 2 balls and 4 on. Thus far, the electrical connection outside the flat terminal 5 is directly performed as described above. As described above, by using: L 本 the semiconductor device according to the first embodiment, a flat terminal 5 is formed, and the distance between the ends of the mounting surface 1 a of the semiconductor element 2 is formed. In addition, ~ 'it is necessary to increase the wiring board 1 or reduce the solder balls 4 and the terminals 5 to be electrically connected by using wire bonding to achieve flatness. Since the distance between the flat terminals 5 can be further reduced, This is a semiconductor device that can correspond to the number of multi-pins and solder balls 4 and further reduce the size of the wiring substrate. Fig. 2 is a sectional view of the semiconductor device of Fig. 2 & Formed on the wiring substrate 丨 Internal wiring substrate ’2 is a semiconductor element, 6a to W are in-line wiring layers, and 6a is used to connect the solder bumps 3 and tin
89113278.ptd 第6頁 477049 五、發明說明（4) 球4的鲜塾層，6b為接地平面 面。 c為彳§唬層，β d為電源平 在如上述構成中，只有本導释一 球4上，而半導體元件2之接地：：之信號腳連接在錫 源腳係與電源平面⑽連• 董接地平面6b連接，電 基板1之端部以使接地平面6b、^錫球4連接並切除配線 二上說明般，若依據本實施二之之\: 如上述般藉由不將接地平面6b、電源平面置，則 上即可抑制錫球4之數目，1沒有千面6d連接在錫球4 小錫球4之間距。 有必要加大配線基板1或縮 又’在上述實施形態2中，雖妙 側之接地平面6b、6d露出，但是使^吏+ 兀件搭載面 面亦可不受限定，而仍可達成與2 C、6d露出之 果。 貝方也形恶相同的效 圖3係顯示本發明實施形態3 在圖3中，係將電源、接地拉出+至=豆衣置的立f圖。 件搭载面U(或是其相反面)上，以开配//板1之半導體元 端子7b。 $成電源端子7a、接地 =以上說明般，若依據本實施形態3之 壯 述般藉由不使電源端子〜、接;、版衣 、’ 即可抑制錫球4之數目，且沒有 社蜴球4 縮小錫球4之間距。 頁义要加大配線基板1或 ^9113278.ptd 477049 五、發明說明（5) 又，在上述實施形態3中，雖然係將電源端子7a、接地 端子7b形成於相對方向上，但是其方向並不受到限定。 又，逐次2邊地形成亦可不受到限定，而仍可達成與上述 實施形態相同的效果。 f施形態4. 圖4係顯示本發明實施形態4之半導體裝置的立體圖。 在圖4中，係將電源、接地拉出至配線基板丨之半導體元 件搭載面1 a (或是其相反面）上，以形成環狀的電源端子 8 a、接地端子8 b。 如以上說明般，若依據本實施形態4之半導體裝置，則 如上述般藉由不使電源端子8a、接地端子8b連接在錫球4 上，即可抑制錫球4之數目，且沒有必要加大配線基板丨或 縮小錫球4之間距。 又，在上述實施形態4中，雖然係在外侧形成電源端子 8a，在内侧形成接地端子8b，但是其位置並不受到限定， 而仍可達成與上述實施形態相同的效果。 f施形態5. 圖5係顯示本發明實施形態5之半導體裝置的截面圖。 對方、有必要在半導體元件2之背面施加接地電位的元件 而言^圖5(A)係在形成於前述配線基板1之晶片搭載面的 接地鈿子8b上利用導電性糊（paste )或導電性薄膜（f丨1冚）9 而安裝有環構件1〇、散熱器（heat spreader)u。而圖 5(B)係在將前述配線基板}之端部予以切除以使之露出的 接地平面6b與半導體元件2之背面上利用導電性糊或導電 477049 五、發明說明（6) 性薄膜9而安裝有環1 0、散熱器11。 如以上說明般，若依據本實施形態5之半導體裝置，則 除了前述實施形態2或前述實施形態4之效果以外，還具有 _ 可在半導體元件2之背面施加接地電位的效果。 實施形態6 . . 圖6係顯示本發明實施形態6之半導體裝置的立體圖。 圖6 (A)係在切除前述配線基板1之半導體元件搭載面 1 a (或是，其相反面）之端部使之露出的接地平面6 b、電源 平面6d上安裝有電連接用的引線端子1 2。而圖6 (B )係在形 成於前述配線基板1之半導體元件搭載面1 a (或是，其相反❶ 面）之電源端子7a、接地端子7b上安裝有電連接用的引線 端子1 2。 如以上說明般，若依據本實施形態6之半導體裝置，則 可在前述實施形態2或前述實施形態3之半導體裝置上，透 過引線端子進行電連接。 【發明之效果】 本發明由於係如以上說明般地構成，所以可達成如下所 示的效果。 若依據第一發明’則因藉由在搭載半導體元件之配線基 板的端部上形成平坦端子，即可無須增加錫球之數目而進 行接腳數之增加，所以可實現沒有必要加大配線基板或縮 小錫球之間距，同時可減少錫球之數目而更縮小配線基 板，且可對應更多腳化的半導體裝置。 . 又，若依據第二發明，則由於使接地平面、電源平面露89113278.ptd Page 6 477049 V. Description of the invention (4) Fresh layer of ball 4, 6b is the ground plane. c is the 唬 § blaze layer, β d is the power source. In the above structure, only the ball 4 of this guide is explained, and the ground of the semiconductor element 2: the signal pin is connected to the tin source pin and is connected to the power plane. The ground plane 6b is connected. The end of the electrical substrate 1 is connected to the ground plane 6b and the solder ball 4 and the wiring is cut. As described in the second embodiment, if the ground plane 6b is not used as described above, When the power supply is placed on the plane, the number of solder balls 4 can be suppressed on the top. 1 has no surface 6d connected to the solder balls 4 and the distance between the solder balls 4 is small. It is necessary to enlarge the wiring board 1 or shrink it. In the second embodiment described above, although the ground planes 6b and 6d on the smart side are exposed, the mounting surface of the element + element can be not limited, and can reach 2 C, 6d reveals the fruit. Beifang also has the same effect. Fig. 3 shows the third embodiment of the present invention. In Fig. 3, it is a vertical diagram of pulling out the power source and the ground + to = Douyi. The component mounting surface U (or the opposite surface thereof) is used to open the semiconductor element terminals 7b of the board 1. $ 成 Power terminal 7a, grounding = As explained above, if according to the description of this embodiment 3, the number of solder balls 4 can be suppressed by not making the power terminal ~, connected, version, ', and there is no social lizard Ball 4 Reduce the distance between solder balls 4. The meaning of the page is to increase the wiring board 1 or ^ 9113278.ptd 477049. 5. Description of the invention (5) In the third embodiment described above, although the power terminal 7a and the ground terminal 7b are formed in opposite directions, the directions are not the same. Not limited. In addition, the formation of two sides in succession may not be limited, and the same effect as that of the above embodiment can be achieved. fSection 4. Fig. 4 is a perspective view showing a semiconductor device according to a fourth embodiment of the present invention. In FIG. 4, the power supply and the ground are pulled out to the semiconductor element mounting surface 1a (or the opposite surface) of the wiring substrate 丨 to form a ring-shaped power terminal 8a and a ground terminal 8b. As described above, if the semiconductor device according to the fourth embodiment is used as described above, the number of solder balls 4 can be suppressed by not connecting the power terminals 8a and the ground terminals 8b to the solder balls 4, and it is not necessary to add The large wiring substrate 丨 or the distance between the solder balls 4 is reduced. In the fourth embodiment, although the power terminal 8a is formed on the outside and the ground terminal 8b is formed on the inside, the position is not limited, and the same effect as that of the above embodiment can be achieved. fSection 5. FIG. 5 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention. For the counterpart, an element that requires a ground potential to be applied to the rear surface of the semiconductor element 2 ^ FIG. 5 (A) uses a conductive paste or a conductive paste on the ground chip 8b formed on the wafer mounting surface of the wiring substrate 1 described above. The flexible film 9 is attached with a ring member 10 and a heat spreader u. 5 (B) uses a conductive paste or a conductive layer on the ground plane 6b and the back surface of the semiconductor element 2 which have been cut off at the ends of the aforementioned wiring substrate}. 477049 5. Description of the invention (6) Thin film 9 The ring 10 and the radiator 11 are installed. As described above, according to the semiconductor device according to the fifth embodiment, in addition to the effects of the foregoing second embodiment or the fourth embodiment, it has the effect that a ground potential can be applied to the back surface of the semiconductor element 2. Embodiment 6 Fig. 6 is a perspective view showing a semiconductor device according to Embodiment 6 of the present invention. FIG. 6 (A) shows a ground plane 6 b and a power supply plane 6 d where the ends of the semiconductor element mounting surface 1 a (or the opposite surface) of the wiring substrate 1 are cut out and exposed. Terminal 1 2 6 (B) shows the lead terminals 12 for electrical connection on the power supply terminal 7a and the ground terminal 7b formed on the semiconductor element mounting surface 1a (or the opposite surface) of the wiring substrate 1. As described above, according to the semiconductor device according to the sixth embodiment, the semiconductor device according to the second embodiment or the third embodiment can be electrically connected through lead terminals. [Effects of the Invention] Since the present invention is configured as described above, the following effects can be achieved. According to the first invention, the number of pins can be increased without increasing the number of solder balls by forming a flat terminal on the end portion of the wiring substrate on which the semiconductor element is mounted, so that it is not necessary to increase the wiring substrate. Or, the distance between the solder balls can be reduced, meanwhile, the number of solder balls can be reduced to further reduce the wiring substrate, and it can correspond to more pinned semiconductor devices. According to the second invention, since the ground plane and the power plane are exposed,
89113278.ptd 第9頁 抑制錫 間距。 依據第 地端子 加大配 據第五 或形成 器，所 依據第 及接地 地端子 的電源 子及接 之說明 線基板 導體元 導體元 錫凸塊 球 坦端子 塾層 地平面 號層 球之數目，且沒有必要加大配線基板或 五、發明說明（7) 出，所以可 縮小錫球之 更且，若 面上形成接 且沒有必要 又，若依 接地平面、 連接有散熱 位。 更且，若 的電源平面 源端子及接 線基板表面 面的電源端 【元件編號 1 配 la 半 2 半 3 銲 4 錫 5 平 6 a 銲 6b 接 6 c 信 三及第四發 、電源端子 線基板或縮 發明，則由 於前述配線 以可在半導 六發明，則 平面、或形 上安裝有引 平面及接地 地端子進行 ) 件搭載面 件 明，則由於在配線基板之表 ’所以可抑制錫球之數目， 小錫球之間距。 於在露出於配線基板表面的 基板表面的環狀接地端子上 體元件之背面施加接地電 由於在露出於配線基板表面 成於前述配線基板表面的電 線端子，所以可對露出於配 平面、或形成於配線基板表 電連接。 4189113278.ptd page 9 Suppress tin pitch. Increase the number of the fifth or former according to the first ground terminal, the power supply of the first and ground ground terminals, and the description of the line substrate, conductor, element, tin bump, ball terminal, and ground plane number. And there is no need to increase the wiring board or the invention description (7), so you can reduce the size of the solder ball. If the connection is formed on the surface and it is not necessary, if it is connected to the ground plane, there is a heat sink. Moreover, if the power plane source terminal and the power terminal on the surface of the wiring board [component number 1 with la half 2 half 3 solder 4 tin 5 flat 6 a solder 6b connected 6 c letter three and fourth hair, power terminal wire substrate The shrinking invention, because the aforementioned wiring is based on the semi-conductor six inventions, the plane or shape of the lead plane and the ground are connected to the ground terminal.) The mounting surface is clear, and the tin can be suppressed because it is on the surface of the wiring board. The number of balls, the distance between the small tin balls. Grounding is applied to the back surface of the ring-shaped ground terminal upper body element exposed on the substrate surface of the wiring substrate. Since the electric wire terminal formed on the wiring substrate surface is exposed on the wiring substrate surface, it can be exposed on the plane or formed. Electrically connect to the wiring board. 41
η 89113278.ptd 第10頁 477049η 89113278.ptd p. 10 477049
89113278.ptd 第11頁 477049 圖式簡單說明 圖1顯示本發明實施形態1之半導體裝置的立體圖。 圖2顯示本發明實施形態2之半導體裝置的截面圖。 圖3顯示本發明實施形態3之半導體裝置的立體圖。 圖4顯示本發明實施形態4之半導體裝置的立體圖。 圖5 (A )、（ B)顯示本發明實施形態5之半導體裝置的截面 -圖。 圖6 (A )、（ B)顯示本發明實施形態6之半導體裝置的立體 圖。 圖7係顯示習知之半導體裝置的截面圖。 镥89113278.ptd Page 11 477049 Brief Description of Drawings Fig. 1 shows a perspective view of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 3 is a perspective view of a semiconductor device according to a third embodiment of the present invention. Fig. 4 is a perspective view of a semiconductor device according to a fourth embodiment of the present invention. 5 (A) and 5 (B) are cross-sectional views of a semiconductor device according to a fifth embodiment of the present invention. 6 (A) and 6 (B) are perspective views showing a semiconductor device according to a sixth embodiment of the present invention. FIG. 7 is a cross-sectional view showing a conventional semiconductor device. Lutetium
89113278.ptd 第12頁89113278.ptd Page 12
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29116399A JP2001110938A (en) | 1999-10-13 | 1999-10-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW477049B true TW477049B (en) | 2002-02-21 |
Family
ID=17765270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089113278A TW477049B (en) | 1999-10-13 | 2000-07-05 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2001110938A (en) |
| KR (1) | KR100374242B1 (en) |
| TW (1) | TW477049B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4644717B2 (en) * | 2008-01-11 | 2011-03-02 | 富士通株式会社 | Board unit |
| JP5586328B2 (en) * | 2010-05-31 | 2014-09-10 | 京セラＳｌｃテクノロジー株式会社 | Wiring board |
-
1999
- 1999-10-13 JP JP29116399A patent/JP2001110938A/en active Pending
-
2000
- 2000-07-05 TW TW089113278A patent/TW477049B/en not_active IP Right Cessation
- 2000-07-13 KR KR10-2000-0040123A patent/KR100374242B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010069991A (en) | 2001-07-25 |
| KR100374242B1 (en) | 2003-03-03 |
| JP2001110938A (en) | 2001-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2755252B2 (en) | Semiconductor device package and semiconductor device | |
| TW550782B (en) | Semiconductor module | |
| TWI236721B (en) | Leadframe for leadless flip-chip package and method for manufacturing the same | |
| US6818981B2 (en) | Heat spreader interconnect for thermally enhanced PBGA packages | |
| TW200950048A (en) | Semiconductor package having an antenna | |
| US10297552B2 (en) | Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects | |
| TW200834846A (en) | Semiconductor device and method for manufacturing the same | |
| TWI582919B (en) | Substrateless fan-out multi-chip package and its fabricating method | |
| US7772696B2 (en) | IC package having IC-to-PCB interconnects on the top and bottom of the package substrate | |
| TW201218334A (en) | Package substrate and fabrication method thereof | |
| CN104867909A (en) | Embedded die redistribution layers for active device | |
| TW200849536A (en) | Semiconductor package and fabrication method thereof | |
| TWI227051B (en) | Exposed pad module integrated a passive device therein | |
| TW201011875A (en) | Package with power and ground through via | |
| CN110854093A (en) | Three-dimensional laminated packaging structure and manufacturing method thereof | |
| US9048223B2 (en) | Package structure having silicon through vias connected to ground potential | |
| TW477049B (en) | Semiconductor device | |
| TW201603223A (en) | Bumps bonds formed as metal line interconnects in a semiconductor device | |
| TW200416989A (en) | Semiconductor device and method therefor | |
| TW200926316A (en) | Semiconductor package and method thereof | |
| TWI581392B (en) | Electronic package assembly | |
| TWI311354B (en) | Multi-chip package structure | |
| TWI567843B (en) | Package substrate and the manufacture thereof | |
| US20070281393A1 (en) | Method of forming a trace embedded package | |
| US9721928B1 (en) | Integrated circuit package having two substrates |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |