TW476225B - Carrier return circuit - Google Patents

Abstract

The present invention proposes a design that uses a pilot signal, which is only added in the residual band edge mode, to complete the entire carrier return circuit. The carrier return circuit is featured with the followings. (1) Only a simple stage of filter is required to filter most of the noise since the maximum frequency error is only 100 KHz after the carrier in the carrier return circuit is demodulated. (2) The completely digital concepts of lead/lag detection and Delta/Sigma FLL are applied in the whole system. (3) The entire system is operated in one stage of phase lock loop such that the system is stable forever. The feasibility is verified through the simulations of C and Verilog, and additionally, the realization is obtained by using TSMC 0.35 μ process and the read only memory (ROM) provided by CIC. The entire circuit uses only more than 3000 logic gates (ROM is not included) such that hardware complexity can be greatly decreased and, additionally, layout area is very small. Furthermore, the phase noise is about 6 degrees.

Description

470 ^ V. Description of the invention (l) Revertive transfer, especially for residual sideband video transmission. With the development of digital communication systems, it was made by NTSC in the early days: TV systems can no longer meet the needs of modern people. Therefore, ATSC has proposed = a new standard for digital TV systems, with a digital modulation of 8vsb: a new standard for digital wireless transmission. The structure diagram of the transmission end provided by the custom service is shown in Fig. 2 and Fig. 2. The data area frame (F: and = is shown in Fig. 3. The data area frame is composed of 313 data areas. ^ a Segment), each data segment is composed of 832 = pay numbers. There are 4 sync codes in each section as the section. This step code can provide the demodulation of the timing recovery circuit. On the evening, the 8VSB material is added with a DC signal during transmission, and this signal can be used by the demodulation recovery circuit. Horse carrier The purpose of this case is the design of the carrier recovery circuit. In the signal system, the synchronization of the carrier is a very important issue. With a ^ ^: change: the system is very sensitive to phase noise, but also requires a very narrow loop bandwidth to get the smallest Phase noise. Due to the uncertainty of the RF oscillator and the influence of the channel, the maximum frequency error at the receiving end is still 100KHZ. ^ However, the carrier recovery circuit still needs to be in a frequency drift situation; it can still lock the phase and achieve the minimum phase noise. In the ATSC specification, due to the addition of a 125 to the signal) Λ data, the entire modulation method becomes a carrier transmission (Transmuted Carrier). The benefit of carrier transmission is

D: \ A \ case \ c60 苏朝琴 \ p60-002. Ptd Page 4 476225 V. Description of the invention (2) It can use smaller hardware than Suppressed Carrier to reduce the design difficulty , But the disadvantage is that you need to transfer more energy. So we can use Citta * s Loop taxi / good fee to achieve. Wanfalai This case uses the concepts of all-digital such as leading one- / backward detection and difference / accumulation to apply it to the entire system to synchronize the response of the streetmen. Not only does the entire system operate in a first-order phase-locked loop, but j is unstable, and only a very simple first-order '丨 = device can be used to remove most of the noise and make the phase The chance of detection of narrowing errors can be reduced to the remaining 25%, so the hardware cost is greatly reduced. In order to achieve the above purpose, this case proposes a plug-in, taxi-data transmission system, including: "Carrier reply circuit" is used for the first Two if Γ are used to multiply a first signal of the data transmission system by a first k 5 tiger to generate a third signal. A low-pass filter is electrically connected to the vertical-垂 xi ^ ^ ^ ^ Constrained into a multiplication state to filter out a roar of the first bluff to generate a fourth signal · A phase detection compensator, which is electrically connected ^ Two-bore system ΠΠ 户 Google ^, electric fan Connected to the side low-pass filter, so as to detect the phase of one of the four signals of the younger brother, with the product number; The sixth signal is produced by the detection compensator, which controls the oscillator digitally. Electrical connection: J seventh signal; and according to the fifth signal and the seventh signal # 5 Hai frequency compensator, the second signal is generated by the eighth signal

476225, Invention Description (3). " The carrier recovery circuit as described, wherein the data transmission system is a digital transmission system. As described in the carrier recovery circuit, the digital video transmission system is a residual sideband video transmission (VSB Video Transmission) system. As described in the carrier recovery circuit, the first signal includes a carrier signal and a data signal. The carrier recovery circuit as described above, wherein the data signal is a digital video signal. The carrier response circuit as described above, wherein the second signal is a local carrier signal = ㈣ The carrier response circuit operates to synchronize with the _th signal of / carrier #. The carrier response circuit, wherein the third signal includes the first signal, an error amount of the first signal, and the noise. The carrier recovery circuit as described above, wherein the noise includes one of the first data signals. ° The carrier recovery circuit as described above, wherein the error amount includes a difference amount and a frequency error amount. In as described, the carrier reply circuit, wherein the fourth signal includes an error amount between the one signal and the second signal. Λ bit The carrier recovery circuit as described above, wherein the fifth signal is an error amount. The carrier recovery circuit as described above, wherein the seven signals are-frequency error

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The carrier returns the electrical preset value as described. Circuit, where the eighth signal is-the carrier response frequency is as described, a phase detection cry, and its phase detection compensator includes two compensators. The phase detector is based on: The fourth signal-the phase error amount is advanced or 'ί: so that the phase of Shi Hai is repaired, and the upper and lower positions of each phase are fixed', if the number is ten or counts down, and counts to one. The watchman changes the fifth signal. Special circuit, wherein the phase compensator includes a counter) 〇 Contains a carrier reply telecom counter (Confidence as described in the total phase of the sixth signal, the amount of error. Carrier reply circuit, wherein the frequency compensator "Detects within a fixed time period" that the phase compensator compensates to output the seventh signal, and the digitally controlled oscillator in the seventh letter 2 neck rate, the fifth signal, and the seventh $ The carrier response circuit as described above includes a pair of mapping tables to map the second signal according to the eighth signal 5 tiger '. The solution to this case can be obtained by the following chart and details. Figure 1 : Conventional ATSC HDTV transmitting-end architecture. Figure 2: Conventional ATSC HDTV receiving-end architecture. Figure 3: Conventional ATSC HDTV data area frame. Figure 4: Carrier response circuit system of the preferred embodiment of the present case. Figure 5: Example of the preferred embodiment of the present case. Leading behind detection mechanism

Figure 6 Figure 7 Model of the case Figure 8 Figure 9 Simulation of the preferred embodiment of the case when the frequency I 4 g 1 of this case is 0kHZ. + / -7200kHZ / Sec simulation. Thousands of you move to f ten: the wafer map of the preferred embodiment of this case. Table · The preferred embodiment of this case, An, error and frequency drift. Comparison of the maximum frequency figure under the bandwidth of the road: multiplier phase detection compensator phase compensator digitally controlled oscillator 4 2: low-pass filter 4 4: phase detector 4 6: frequency compensator Sx • Xth Signal recovery circuit, which is divided into the following 4 1 4 3 4 5 4 7 device 44, phase compensator 45, frequency ^ leading / lagging phase detection and other components, Dou Niuniu stand, 丨 甬 j 益 46, digital Control Oscillator 47 Temple > and. A phase detector 44 and a phase compensation detection compensator 43 are formed. The function of the multiplier is to reduce the frequency of the second fundamental frequency, and the maximum error of the carrier frequency is 〇〇〇 field ~ The wave filter treats the data as noise and divides it. ㈣Η Measure the probability of correctness. So here's low

V. Description of the invention (6) The pass filter only needs _ bandwidth is about 20kHZ in the lead -... / not every value (in the number) affects the probability of error. The device is reduced to calculate the wrong phase for smoothing, so we have If you are in the lead, you can control one of the oscillators, so if you can use $, you can use the system to make the frequency. The main purpose is to control the oscillators. This information is used to detect the occurrence of the fundamental frequency. In addition, when the power input is behind, reducing the overall phase generator is a very high-level IIR. The cut-off frequency behind detection is exactly considered as a guide signal, so the entire resource is then lowered by about 25%. Road 4 5 mainly sends signals to Only one confidence meter will phase several systems. Because the area is wasted, his phase is completed by first-order phase-locking. The frequency error is very small, but the phase is lost. Therefore, the rate compensation circuit can compensate for the additional phase produced by the frequency error. This low-pass filter is the channel of Chihime's life. See about 8MHZ. Among the mechanisms, as shown in Figure Wuhu, r > jb JL ·. And yes. The reason for the error is because of noise, and the guide ## is I ,,; The high guide is not solved. Therefore, there is a so-called detection error from the transmitting end to the receiving end, which is multiplied, filtered, and waved After removing some noise, you can push 0 to add the result of lead / lag detection to the digital control oscillator 47 to change the phase angle. The counter, when the confidence counter has accumulated i 6-bit oscillators reduce or increase the phase, bit jitter. The next pass is to use read-only memory to implement the entire digit. Only some logic gates whose four phases are implemented can be realized here. From these loop circuits. When using this first-order phase-locked loop back beyond the pull-in range, we use Delta-Sigma FLL technology to detect the frequency error. The total amount of phase shift generated by Delta-Sigma FLL is equal to the digital control amount. Increased due to digitally controlled oscillators

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The erroneous phase amount can be calculated, so r and the difference are compensated. The maximum frequency error is W to find the frequency I dare to be large I, the formula is as follows: corpse = (菩) χΛχ 士 X (1-2P «0 where step is the solution of each NC0 beating 21. 52M, Cf is the confidence counter The value of = 16, / 过, we further consider it, basically ± _ ", 25%. Do not sign + the frequency of the mistake. Z is a fixed difference, possibly due to the previously mentioned The cause of the J-rate error is that the frequency of different slopes will drift. However, there is a large frequency change. These factors should be included in me :: under consideration. Therefore, it still moves when there is a frequency drift. , The formula is as follows: Dare to cook you 2H FD 1 ^ 6〇χ2) = 7ΑΛ FD = 24QfiTx jr = iTx〇J32284 PA Gamma = J? X 36CT x go x 24〇x (to) = j? Χ 3 91 Heart 1 g »4

Fmix. = ^ Snwx = ifx 0.02284 corpse 脳 κ istiwmaximaJfrequieiicydriftcompeiisatiii

Hmni = FnHK-rOD2284 Among them, the maximum frequency error and maximum frequency drift in each loop can be derived from the above two formulas. As shown in Table 1. See also In order to cope with large frequency fluctuations and reduce the convergence time of the entire carrier-back circuit and get the smallest phase noise, a confidence loop of ^ channel bandwidth is added here, as shown in Figure 6. The bandwidth of each loop in the design ^

V. Description of the invention (8) The system is one-half of the bandwidth, twice or less than the lower limit of the bandwidth; ;; f 2 The frequency is greater than the upper limit of the bandwidth, and the circuit can be dynamically changed. Go to another bandwidth, such as the boundary of the outbound loop bandwidth is 0k 1 above. And can be pushed • b5kHZ, 2 ″ 2kHZ, 10.5kHZ. System simulation 1 〇〇κί Tm /-One consideration is when the frequency error reaches the maximum bit. Whether the Hi complex circuit can catch up and lock the phase recovery current: Secondly, it is found that the situation of the entire carrier wave is the same as the puii_in phenomenon of the general phase-locked loop when the frequency has not yet been caught. The bottom half of the same figure can be clear. Seeing the rate: the phase of the transmission = and the receiving end has been increasing, but when the frequency and frequency reach a steady state, the entire phase difference is here, the phase is locked, and the carrier is synchronized. In Figure 8, we must clearly prove that when there is no error in the frequency, it is the front: r! Stable carrier synchronization is achieved. It can be seen from the figure that although the frequency of the digitally controlled oscillator is randomly jumped at /, There is even a phenomenon that the error rate of the staff increases. However, this is due to the whole: back:. See noise from a steady state that has not been reduced to a maximum. Therefore, when the loop bandwidth is gradually reduced, the entire carrier will be synchronized. If we use a fixed time to change the bandwidth, the non-convergence time will be too long, and even more serious will cause the loss of phase due to the unsuitable relationship of the selected loop bandwidth. In Figure IX, we take into account the frequency drift.

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When there is a drift in the check rate, {No, the phase can still be locked. False = The frequency drifts at a slope of + / _ 720 0K / SEC. You can see from the difference calculation formula that this slope is at the boundary of the loop bandwidth. Therefore, it can be seen that the carrier recovery circuit can still lock this slope , But the whole thing is a lot bigger. In the second half of the figure, when we can observe-shift, a very drastic frequency change will occur, and a confidence counter with a bandwidth of =: 2 will detect the change, and then the phase is still ΐ, ί; Increase the loop bandwidth to prevent phase loss, and wait for the frequency to go wrong. ι: Switch to a small loop bandwidth. At the same time, the reason why it can be seen on this graph that it is small and then becomes large again is the confidence of the loop bandwidth = the phenomenon of retransmission. In this case, it can not be said that the phase is not: 、, m ^ When the frequency at the end of the transmission drifts At that time, the phase will naturally change after the adjustment of B: 〇, B. The synchronization of the entire carrier is determined based on the phase after modulation. Therefore, the carrier is still synchronized. m Hardware implementation and layout diagram In hardware, we are using TSMc MU standard cell single-chip process to achieve the chip. The main considerations on the hardware are: finite character length, c ugly _ ^ 4 pass from Tian Wen Keli π 丨 knife μ ^ ^ ^ s branch simulation results and use hardware description language model 丨 1 Such as Tian Fu,, Li Li ^ and consideration of overflow. In addition, 疋, 疋 ,,,, and the logic transferred from the Standard Cell

/ 〇225 V. Description of the invention (10) How to edit the series and the only 4 provided by c IC In addition, we have also added 1 | | For functional testing. Real: = Γ = 1000um * 80 0um A small. The main circuit uses the main delay path to find out. The longest hesis frequency is 21.52MHZ, so it is not right. S is the circuit operation. The layout of this chip will not cause timing disorder. Surgery. In the i-t communication system, the synchronization of the carrier is the key technology of the system. At the edge, we use the leading digital concepts such as lead / lag detection and difference / accumulation lock to apply in the circuit different from the traditional carrier response. It also uses the characteristics that only appear in the VSB mode to simplify the design of the circuit. The J QAM 0 system is unstable because it operates in a first-order phase-locked loop system. In the design of the ΪIR low-pass filter, because its function is only to filter out some noise, it can meet the design requirements with only a first-order low-pass filter, which greatly reduces the implementation of the chip. Hardware waste. / The specification required for the entire system is the requirement to reduce the frequency error of 10KHZ to 2kHZ. Our proposed circuit can pull 1⑽kjjz below 100Hz, and the phase noise performance is only within 6 degrees of the phase. error. Because the dynamic loop bandwidth designed above can prevent great frequency changes, it can also shorten the convergence by 100KHZ frequency error.

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To stable time. By I, +, Μ% # Only 3000 advantages are used, so in the implementation of the chip ^ TSMC standard cell 0 35u t ^ 800um size.面积 U.35u China-Japan daily film area is 1000 questions * Circuit Power: Direction · L, because this plan only completes the carrier response ^ Road 10's δ and juice, but there is also timing response in the entire ATSc HDTV, 2 Device and so on @@ Therefore in the next stage-the goal is to put these circuits: mouth in "I have combined analog digital converters in order to complete the integration. In addition, we also want to use previous all-digital concepts such as lead / lag detection and difference / accumulated frequency-locked loops to incorporate into future design concepts, because many of today's designs are directly analogous to previous development Circuits use special conversion techniques to become digital circuits. Therefore, if the concept of digital can be used directly to develop circuits, I believe that there may be opportunities for breakthroughs in hardware savings and design complexity. Indicating that the above-mentioned 'the patentability of this case is sufficient and the patent application is filed according to law, but the above embodiments are not enough to cover the entire case, so the scope of patent application is attached. References [1] Advenced Television System Committee, ATSC Digital Television Standards, Sept. 1995.

[2] Advanced Television System Committee, Guide to the use of ATSC Digital Television Standards, Oct.

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[3] Wayne Bretl, " VSB Modem Subsystem Design for Grand Alliance Digital Television Receivers ",

1995, IEEE

[4] Lim, H, eta 1., 丨 Low-Comp 1 ex ty Reciever Algorithms for the Grand-A11iance VSB HDTV system, " IEEE Trans. On Consumer Electronic, Vo 1. 42, No. 3, August 1996, pp640-650 · [5] Sgrignoli, G ·, W · Bertl, and R · Citta, n VSB Modulation Used for Terrestrial and Cabal Broadcasts, f, IEEE Trans. On Consumer Electronics, Vol. 41, No. 3, Aug. 1995, pp. 367-382.

[6] Bertl, W., G. Sgrignoli, G., and P. Snopko, " VSB Modem Subsystem Design for Grand Alienance Digital Televsion Recievers, 丨, IEEE Trans. N Consumer Electronics, Vol. 41, No. 3 , Aug. 1995, pp.773-786.

[7] Best, RE, Phase-Locked Loops-Theory, Desgn, and Applications 2nd Ed, McGraw-Hill, Inc., New York, USA ·, 1993 [8] S. Yin Yin, CC Su, M · T Shiue, LY Huang, CK Wang, SJ Jou, WI Way, MA New VSB Modulation Technique and Shaping Filter Design n IEEE International Symposium on Volume: 4, 1996

D: \ A \ case \ c60 苏朝琴 \ p60-002 · ptd Page 15 476225 V. Description of the Invention (13), Page (s): 312 -315 νο1.4 · 4 [9] I. Galton, MA practical second-order delta-sigma frequency-to-Digital Converter, M Proc. Of 1 9 9 5 IEEE Int. Symp. Circuits and Systems, Vo 1. 3 of 4, pp. 5-8 [10] I. Galton, William Huff, Paolo Carbone, and Eric Siragusa, MA Delta-si gma PLL for 14-b, 50kSamp1e / s Frequency-to-Digital Conversion of a 10MHZ FM signal, " Solid-State Circuits, IEEE Journal of Volume: 33 12, Dec. 1998 , Page (s): 2042-2053

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Claims (1)

476225 6. Application Patent Scope 1. A carrier reply circuit is used in a data transmission system and includes: a multiplier to multiply a first signal and a second signal of the data transmission system to generate a first Three signals; a low-pass filter, which is electrically connected to the multiplier, thereby filtering out noise of the third signal to generate a fourth signal; a phase detection compensator, which is electrically connected to the low-pass A filter to detect a phase of the fourth signal to generate a fifth signal and a sixth signal; a frequency compensator electrically connected to the phase detection compensator so as to The six signals generate a seventh signal; and a digitally controlled oscillator is electrically connected to the frequency compensator to generate the second signal according to the fifth signal, the seventh signal, and an eighth signal. 2. The carrier recovery circuit described in item 1 of the scope of patent application, wherein the data transmission system is a digital video transmission system. 3. The carrier recovery circuit as described in item 2 of the scope of the patent application, wherein the digital video transmission system is a residual sideband video transmission (VSB Video T r n s m i s s i ο η) system. 4. The carrier recovery circuit according to item 1 of the scope of patent application, wherein the first signal includes a carrier signal and a data signal. 5. The carrier recovery circuit as described in item 4 of the scope of patent application, wherein the data signal is a digital video signal. 6. The carrier reply circuit as described in item 1 of the scope of the patent application, wherein the second signal is a local carrier signal, and the carrier reply circuit is used for the operation. D: \ A \ case \ c60 Su Chaoqin \ p60-002 · ptd page 17 476225 6. Patent application scope _____ works to synchronize with a carrier signal of the first signal. 7. According to the carrier recovery circuit described in item i of the patent application scope, the third signal includes one of the first signal and the second signal, wherein the noise is included. The carrier signal recovery circuit as described in item 7 of the scope of patent application, the miscellaneous sfl includes a data signal which is one of the first signals. > In this 9, the carrier recovery circuit as described in item 7 of the patent application range, the error amount includes a phase error amount and a frequency error amount. Wherein, the 10, the carrier response as described in the first scope of the patent application, and the fourth signal include the error between the first signal and the second signal. Among them, 1 1, as described in the first scope of the patent application The carrier responds to the difference by $. The fifth signal is a phase error amount. ′ Of which 1 2. The carrier response as described in item 1 of the scope of patent application. The seven signals are a frequency error amount. Among them, 1. The carrier recovery circuit according to item 1 of the scope of patent application, wherein the eighth signal is a frequency preset value. Among them, as in the carrier recovery circuit described in item 1 of the scope of patent application, the phase detection compensator includes a phase detector and a phase compensator, and the phase detector informs the phase compensator that the first Four signals = two 'The error amount is advanced or backward, so that the phase compensator counts up or = bit counts, and when the count reaches a specific value, the fifth signal is changed. " Next 15 5. The carrier recovery circuit as described in item 1 of Shen Qing's patent scope, wherein the delta phase detection method includes a confidence counter (C 〇 η ^ 丨 d e n c e Counter) ° D: \ A \ case \ c60 Su Chaoqin \ p60-002 · ptd% 18 1 '-— 476225 6. Application for patent scope 1 6. Carrier recovery circuit as described in item 1 of patent application scope, where the frequency compensator is In accordance with the sixth signal, the total phase compensated by the phase compensator within the fixed time is detected to output the seventh signal, and the seventh signal is a frequency error amount. 17. The carrier recovery circuit according to item 1 of the scope of patent application, wherein the digitally controlled oscillator includes a pair of mapping tables to map out according to the eighth signal, the fifth signal and the seventh signal. The second signal. D: \ A \ case \ c60 苏朝琴 \ p60-002. Ptd page 19